CN107968057B - Wafer retesting method - Google Patents
Wafer retesting method Download PDFInfo
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- CN107968057B CN107968057B CN201711177120.9A CN201711177120A CN107968057B CN 107968057 B CN107968057 B CN 107968057B CN 201711177120 A CN201711177120 A CN 201711177120A CN 107968057 B CN107968057 B CN 107968057B
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012360 testing method Methods 0.000 claims abstract description 179
- 238000013102 re-test Methods 0.000 claims abstract description 44
- 238000003070 Statistical process control Methods 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- 230000026676 system process Effects 0.000 claims abstract description 4
- 239000013078 crystal Substances 0.000 claims description 12
- 230000004913 activation Effects 0.000 claims description 8
- 238000012797 qualification Methods 0.000 claims description 7
- 238000010998 test method Methods 0.000 claims 1
- 239000002699 waste material Substances 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000010391 action planning Effects 0.000 description 3
- 229940095676 wafer product Drugs 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The invention provides a wafer retest method, which is applied to a manufacturing execution system and comprises the following steps: after the wafer test equipment tests the wafer, sending a test result formed by the test to a wafer receiving test unit; the wafer test unit sends the test result to a statistical process control system; the statistical process control system processes the test result according to a preset control rule to form a corresponding trigger instruction; the statistical process control system sends the trigger instruction to a manufacturing execution system; the manufacturing execution system selects a corresponding processing grade according to the trigger instruction, and outputs a retest item corresponding to the processing grade to the wafer test equipment; and the wafer test equipment performs retesting on the wafer to be tested according to the retesting items. The technical scheme has the beneficial effects that the manual intervention is effectively reduced, and further the wafer scrapping and the waste of the wafer testing equipment capacity caused by the manual misjudgment are avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a wafer retesting method.
Background
As shown in fig. 1, when a conventional wafer testing apparatus 1 performs an electrical test on a wafer, a wafer receiving testing unit 2 sends a testing result formed by the test to a statistical process control system 4, the statistical process control system 4 analyzes the testing result to send the analysis result to a manufacturing execution system 5, the manufacturing execution system 5 selectively activates an out-of-control action planning unit, and after the out-of-control action planning unit is triggered, a client 6 captures testing result data through an analysis processing data tool 3 to determine a wafer parameter that fails to be tested, so as to search a corresponding operation program to finally determine a retesting scheme that needs to be executed by the wafer testing apparatus 1. Where taking a lot of time (about 2 hours) to make a retest determination in the runaway action planning unit is extremely inefficient; and the subsequent retest is greatly influenced by human factors due to ginseng and judgment, and the condition of selecting wrong test items occurs, so that the wafer product is scrapped due to test failure and the capacity of the wafer test equipment is wasted.
Disclosure of Invention
In view of the above problems in the prior art, a retest method for retesting a wafer after testing is provided, which can select a processing priority for retesting the wafer according to a test result and select a corresponding test item according to the processing priority for retesting the wafer.
The specific technical scheme is as follows:
a retest method of the crystal circle, apply to the manufacturing execution system, including the test equipment of the crystal circle, crystal circle receives the test unit, the statistical process control system, wherein, set up multiple treatment levels in advance in the said manufacturing execution system, and every said treatment level has a retest project arranged sequentially correspondingly, the said retest project is used for carrying out the retest to the crystal circle;
the method comprises the following steps:
step S1, after the wafer testing equipment tests the wafer, sending a test result formed by the test to the wafer receiving testing unit;
step S2, the wafer test unit sends the test result to the statistical process control system;
step S3, the statistical process control system processes the test result according to a preset control rule to form a corresponding trigger instruction;
step S4, the statistical process control system sends the trigger command to the manufacturing execution system;
step S5, the manufacturing execution system selects the corresponding processing class according to the trigger instruction, and outputs the retest item corresponding to the processing class to the wafer test equipment;
and step S6, the wafer test equipment retests the wafer to be tested according to the retest item.
Preferably, the wafer testing apparatus is configured to perform an electrical test on the wafer, and the method for testing the wafer includes:
defining a plurality of test points on the wafer in advance;
testing the plurality of test points through the wafer test equipment to obtain test parameters of the test points;
the test result comprises the number of the test points which are qualified and unqualified, and the test parameters of the test points.
Preferably, the control rule preset by the manufacturing execution system includes:
obtaining the qualified rate of the test points according to the qualified and unqualified numbers of the test points;
and respectively setting the qualification rates of the test points to different values, and taking the qualification rates set to different values as a plurality of control rules.
Preferably, after the wafer testing device performs the test on the wafer, the wafer testing device forms the test result into a file with a predetermined format and sends the file to the wafer receiving and testing unit.
Preferably, the trigger command generated by the statistical process control system further includes:
the detaining code is used for locking the wafer needing to be retested;
an activation code to activate the retest item in the manufacturing execution system.
Preferably, the statistical control system is preset with standard withholding codes of multiple levels, and the standard withholding codes represent the processing levels;
and the statistical process control system matches the withholding codes with a plurality of preset standard withholding codes, and activates and acquires the retest items corresponding to the standard withholding codes of the current level according to the activation codes after the matching is passed.
Preferably, the number of the test points on the wafer is 9.
Preferably, an analysis processing tool and a client are also provided;
receiving the test result obtained by the wafer receiving test unit through the analysis processing tool, and analyzing and processing the test result to obtain an analysis result;
the client is used for displaying the analysis result in the client.
The technical scheme has the following advantages or beneficial effects: the processing priority for retesting the wafer is selected according to the test result, and the corresponding test items are selected according to the processing priority for retesting the wafer, so that the test efficiency and the test accuracy are improved, the manual intervention is effectively reduced, and the wafer scrapping and the waste of the wafer test equipment capacity caused by the manual misjudgment are avoided.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a partial schematic view of a background art;
FIG. 2 is a flowchart illustrating a method for retesting a wafer according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The technical scheme of the invention comprises a wafer retest method.
The embodiment of the retest method of a kind of crystal circle, apply to the manufacturing execution system, including the test equipment of crystal circle, crystal circle and receive the test unit, the statistical process control system, wherein, set up multiple treatment levels in advance in the manufacturing execution system, and each treatment level has a retest project of arranging sequentially correspondingly, the retest project is used for carrying out the retest to the crystal circle;
as shown in fig. 2, the method comprises the following steps:
step S1, after the wafer testing equipment tests the wafer, sending a test result formed by the test to the wafer receiving testing unit;
step S2, the wafer test unit sends the test result to the statistical process control system;
step S3, the statistical process control system processes the test result according to the preset control rule to form a corresponding trigger instruction;
step S4, the statistical process control system sends the trigger command to the manufacturing execution system;
step S5, the manufacturing execution system selects the corresponding processing grade according to the trigger instruction, and outputs the retest item corresponding to the processing grade to the wafer test equipment;
and step S6, the wafer testing equipment retests the wafer to be tested according to the retest item.
The wafer testing method aims at solving the problems that in the prior art, when the retest of the wafer is judged to be performed, the wafer product is scrapped due to the test failure and the productivity of the wafer testing equipment is wasted.
Here, the error in selecting the test item refers to that the fail wafer is not noticed and the retest is not performed, that the fail wafer is noticed after the MAP (layout) is tested, so that the retest 9 points (9 points refer to test points on the wafer) is retested again, that the W wafer cannot be shipped due to the fail parameter fail, that the Recipe (test item) not containing the fail parameter is selected by mistake, and the like.
According to the wafer retest method, after the test result of the wafer is obtained, the test result is analyzed through the statistical process control system to form the corresponding trigger instruction, after the manufacturing execution system receives the trigger instruction, the corresponding processing priority is automatically selected according to the trigger instruction, and then the test item corresponding to the currently selected processing priority is obtained to retest the wafer, so that the manual intervention can be effectively reduced, and the wafer scrapping and the waste of the wafer test equipment capacity caused by the manual misjudgment are avoided.
In a preferred embodiment, the wafer test apparatus is used for performing electrical tests on a wafer, and the method for testing the wafer comprises:
defining a plurality of test points on a wafer in advance;
testing the plurality of test points through wafer test equipment to obtain test parameters of the test points;
the test result comprises the number of the test points which are qualified and unqualified, and the test parameters of the test points. In a preferred embodiment, the preset control rules of the manufacturing execution system include:
obtaining the qualification rate of the test points according to the qualified and unqualified numbers of the test points;
and respectively setting the qualification rates of the test points to different values, and taking the qualification rates set to different values as a plurality of control rules.
In a preferred embodiment, after the wafer testing device performs the test on the wafer, the wafer testing device sends the test result to the wafer receiving testing unit in a file with a predetermined format.
In a preferred embodiment, the statistical process control system generated trigger instructions further comprise:
the detaining code is used for locking the wafer needing to be retested;
the activation code is used for activating the retest item in the manufacturing execution system.
In a preferred embodiment, a plurality of levels of standard withholding codes are preset in the statistical control system, and the standard withholding codes represent processing levels;
and the statistical process control system matches the withholding codes with a plurality of preset standard withholding codes, and after the matching is passed, the retest item corresponding to the standard withholding code of the current level is obtained according to the activation of the activation code.
In the above technical solution, the control parameters in the control rule may include (multi-point OOS (out of specification limit) Fail/Warning, single-point OOS (out of specification limit), single-point OOC (out of specification limit), etc.) the multi-point and the single-point are test points on the wafer;
the control rule judges the test result according to each control parameter so as to finally output a control instruction containing the activation code and the detaining code to the manufacturing execution system.
In a preferred embodiment, the number of test points on the wafer is 9.
In the above technical solution, the wafer testing device mainly tests the test points defined on the wafer, and obtains whether the test points are qualified or unqualified, and the test parameters of the qualified test points and the test parameters of the unqualified test points through the electrical test of the test points.
In a preferred embodiment, an analysis processing tool and a client are also provided;
receiving a test result obtained by the wafer receiving test unit through the analysis processing tool, and analyzing and processing the test result to obtain an analysis result;
the client is used for displaying the analysis result in the client.
In the technical scheme, the analysis result can be obtained through the analysis processing of the analysis processing tool on the test result by the user at the client, and then the user can timely know and obtain the wafer which needs to be retested.
As shown in fig. 1:
the wafer testing equipment 1 is connected with the wafer receiving testing unit 2, and the wafer testing equipment sends a testing result formed by testing to the wafer receiving testing unit 2;
the wafer receiving and testing unit 2 is connected with the statistical process control system 4, the wafer receiving and testing unit 2 is used for sending the received testing result to the statistical process control system 4, processing and analyzing the testing result through the statistical process control system 4 to obtain a trigger instruction, and sending the trigger instruction to the manufacturing execution system 5 connected with the statistical process control system 4;
the manufacturing execution system 5 is connected with the wafer test equipment 1, the manufacturing execution system 5 is used for forming a corresponding retest item according to the trigger instruction and outputting the retest item to the wafer test equipment 1, and the test equipment 1 executes a corresponding retest operation on the wafer according to the retest item;
the analysis processing tool 3 is connected to the wafer receiving and testing unit 2 and the client 6, the analysis processing tool is used for analyzing the testing result to obtain an analysis result and outputting the analysis result to the client 6 for displaying, the client 6 is further connected to the statistical process control system 4, and data of the statistical process control system 4 for processing and analyzing the testing result can also be obtained.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (6)
1. A retest method of the crystal circle, apply to the manufacturing execution system, including the test equipment of the crystal circle, crystal circle receives the test unit, the statistical process control system, characterized by that, set up multiple treatment levels in advance in the said manufacturing execution system, and every said treatment level has a retest project arranged sequentially correspondingly, the said retest project is used for carrying out the retest to the crystal circle;
the method comprises the following steps:
step S1, after the wafer testing equipment tests the wafer, sending a test result formed by the test to the wafer receiving testing unit;
step S2, the wafer receiving test unit sends the test result to the statistical process control system;
step S3, the statistical process control system processes the test result according to a preset control rule to form a corresponding trigger instruction;
step S4, the statistical process control system sends the trigger command to the manufacturing execution system;
step S5, the manufacturing execution system selects the corresponding processing grade according to the trigger instruction, and outputs the retest item corresponding to the processing grade to the wafer test equipment;
step S6, the wafer testing equipment retests the wafer according to the retest item;
the trigger command generated by the statistical process control system further includes:
the detaining code is used for locking the wafer needing to be retested;
an activation code to activate the retest item in the manufacturing execution system;
the statistical process control system is preset with standard withholding codes of a plurality of grades, and the standard withholding codes represent the processing grades;
and the statistical process control system matches the withholding codes with a plurality of preset standard withholding codes, and activates and acquires the retest items corresponding to the standard withholding codes of the current level according to the activation codes after the matching is passed.
2. The method of claim 1, wherein the wafer test apparatus is configured to perform electrical testing on the wafer, the method of testing the wafer comprising:
defining a plurality of test points on the wafer in advance;
testing the plurality of test points through the wafer test equipment to obtain test parameters of the test points;
the test result comprises the number of the test points which are qualified and unqualified, and the test parameters of the test points.
3. The retesting method according to claim 2, wherein the control rules preset by the manufacturing execution system include:
obtaining the qualified rate of the test points according to the qualified and unqualified numbers of the test points;
and respectively setting the qualification rates of the test points to different values, and taking the qualification rates set to different values as a plurality of control rules.
4. The retest method of claim 2, wherein the wafer test equipment sends the test result to the wafer receiving test unit in a file with a predetermined format after performing the test on the wafer.
5. The retest method of claim 2, wherein the number of test points on said wafer is 9.
6. The retesting method according to claim 1, further providing an analysis processing tool and a client;
receiving the test result obtained by the wafer receiving test unit through the analysis processing tool, and analyzing and processing the test result to obtain an analysis result;
the client is used for displaying the analysis result in the client.
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| CN201711177120.9A CN107968057B (en) | 2017-11-22 | 2017-11-22 | Wafer retesting method |
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| CN201711177120.9A CN107968057B (en) | 2017-11-22 | 2017-11-22 | Wafer retesting method |
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| CN107968057B true CN107968057B (en) | 2020-04-24 |
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| CN114527366A (en) * | 2021-12-31 | 2022-05-24 | 杭州广立微电子股份有限公司 | WAT automatic retest method |
| TWI807744B (en) * | 2022-03-30 | 2023-07-01 | 欣銓科技股份有限公司 | Immediate backtest method for wafer test |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01244380A (en) * | 1988-03-25 | 1989-09-28 | Nec Yamaguchi Ltd | Ic tester |
| CN102692569A (en) * | 2011-03-25 | 2012-09-26 | 台湾积体电路制造股份有限公司 | Adaptive test sequence for testing integrated circuits |
| CN104614656A (en) * | 2013-11-05 | 2015-05-13 | 京元电子股份有限公司 | Semiconductor chip retest system and retest method thereof |
| CN104889077A (en) * | 2014-03-07 | 2015-09-09 | 泰克元有限公司 | Sorting machine for test of semiconductor member and testing support method of the sorting machine |
| CN105161439A (en) * | 2015-07-22 | 2015-12-16 | 上海华力微电子有限公司 | Wafer testing management system and method |
| CN105702595A (en) * | 2014-11-27 | 2016-06-22 | 华邦电子股份有限公司 | Wafer yield judging method and wafer qualification test multivariable detection method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7396693B2 (en) * | 2005-09-14 | 2008-07-08 | Semiconductor Manufacturing International (Shanghai) Corporation | Multiple point gate oxide integrity test method and system for the manufacture of semiconductor integrated circuits |
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- 2017-11-22 CN CN201711177120.9A patent/CN107968057B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01244380A (en) * | 1988-03-25 | 1989-09-28 | Nec Yamaguchi Ltd | Ic tester |
| CN102692569A (en) * | 2011-03-25 | 2012-09-26 | 台湾积体电路制造股份有限公司 | Adaptive test sequence for testing integrated circuits |
| CN104614656A (en) * | 2013-11-05 | 2015-05-13 | 京元电子股份有限公司 | Semiconductor chip retest system and retest method thereof |
| CN104889077A (en) * | 2014-03-07 | 2015-09-09 | 泰克元有限公司 | Sorting machine for test of semiconductor member and testing support method of the sorting machine |
| CN105702595A (en) * | 2014-11-27 | 2016-06-22 | 华邦电子股份有限公司 | Wafer yield judging method and wafer qualification test multivariable detection method |
| CN105161439A (en) * | 2015-07-22 | 2015-12-16 | 上海华力微电子有限公司 | Wafer testing management system and method |
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