CN107943183A - A kind of voltage reference circuit of super low-power consumption - Google Patents

Abstract

The invention belongs to electronic circuit technology field, particularly relates to a kind of voltage reference circuit of super low-power consumption.A kind of the problem of present invention cannot be operated in ultra-low operating voltage for existing band-gap reference, it is proposed that new super low-power consumption voltage reference circuit for being operated in 0.45V.The technical scheme is that a kind of ultralow pressure super low-power consumption voltage reference circuit for being operated in 0.45V, including bias current module, high and low gate source voltage generation module and voltage subtraction module.The present invention utilizes voltage subtraction module output voltage benchmark, and by the selection of field-effect transistor structure parameter, reduces the temperature coefficient of voltage reference.A kind of ultralow pressure super low-power consumption voltage reference circuit for being operated in 0.45V proposed by the present invention, it can be operated under very low supply voltage, power consumption is only several nanowatts, any kind of bipolar transistor need not be used, integrated circuit can be made using standard CMOS process, so that its scope of application and flexibility significantly improve.

Description

An ultra-low power consumption voltage reference circuit

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to an ultra-low voltage and ultra-low power consumption voltage reference circuit which can work at 0.45V.

Background technique

The voltage reference circuit is an indispensable part of all electronic systems. In some special environments, not only the voltage generated by the voltage reference circuit is required not to change with the change of the power supply voltage and temperature, but also it is required to work with extremely low power consumption in ultra- under low supply voltage. Traditional bandgap references are the most widely used, but limited by their turn-on voltage, they cannot work at ultra-low supply voltages.

Contents of the invention

The purpose of the present invention is to solve the problem that the existing bandgap reference cannot work at ultra-low working voltage, and propose a novel ultra-low power consumption voltage reference circuit which can work at 0.45V.

The technical solution of the present invention is an ultra-low power consumption voltage reference circuit that can work at 0.45V, including a bias current module, a high and low gate-source voltage generation module, and a voltage subtraction module;

The bias current module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a resistor R; the source of the first PMOS transistor MP1 is connected to a power supply, and its gate Connect the drain of the second PMOS transistor MP2; the source of the second PMOS transistor MP2 is connected to the power supply, and its gate and drain are interconnected; the gate and drain of the first NMOS transistor MN1 are interconnected, and its drain is connected to the first The drain of the PMOS transistor MP1, the source of the first NMOS transistor MN1 are grounded; the drain of the second NOMS transistor MN2 is connected to the drain of the second PMOS transistor MP2, and the gate of the second NOMS transistor MN2 is connected to the gate of the first PMOS transistor MP1 The drain, the source of the second NOMS transistor MN2 is grounded after passing through the resistor R; wherein, the connection point between the gate of the first PMOS transistor MP1, the gate and the drain of the second PMOS transistor MP2 is the output terminal of the bias current module, and the output Bias voltage VB1;

The high and low gate-source voltage generating module includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a low-threshold NMOS transistor MNLV and a high-threshold NMOS transistor MNHV; the source of the third PMOS transistor MP3 is connected to a power supply, and its gate is connected to Bias voltage VB1; the source of the fourth PMOS transistor MP4 is connected to the power supply, and its gate is connected to the bias voltage VB1; the drain of the low-threshold NMOS transistor MNLV is connected to the drain of the third PMOS transistor MP3, and the low-threshold NMOS The gate and drain of the transistor MNLV are interconnected, and the source thereof is grounded; the drain of the high-threshold NMOS transistor MNHV is connected to the drain of the fourth PMOS transistor MP4, and the gate and drain of the high-threshold NMOS transistor MNHV are interconnected, its source is grounded;

The voltage subtraction module includes a fifth PMOS transistor MP5, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; the source of the fifth PMOS transistor MP5 is connected to a power supply, and its gate is connected to a bias voltage VB1; the third The drain of the NMOS transistor MN3 is connected to the drain of the fifth PMOS transistor MP5, the drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4; the drain of the fourth NMOS transistor MN4 is connected to the third NMOS transistor MN3 The source of the fourth NMOS transistor MN4 is connected to the drain of the third PMOS transistor MP3, and the source of the fourth NMOS transistor MN4 is grounded; the source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4 The connection point is the output terminal of the voltage reference circuit, which outputs the reference voltage VREF. .

The ultra-low power consumption voltage reference circuit capable of working at 0.45V of the present invention can be used to make an integrated circuit, and the integrated circuit is made by standard CMOS technology.

The beneficial effect of the present invention is that the ultra-low power consumption voltage reference circuit of the present invention can work at 0.45V, compared with the existing bandgap reference, the minimum working voltage can reach 0.45V; In terms of implementation process, it can be implemented using a standard CMOS process; in terms of power consumption, its power consumption is only a few nanowatts, which is far lower than that of traditional bandgap references.

Description of drawings

Fig. 1 block diagram of circuit structure of the present invention;

Fig. 2 circuit structure diagram of the bias current module proposed by the present invention;

Fig. 3 is a circuit structure diagram of the high and low gate-source voltage generation module proposed by the present invention;

Fig. 4 is a circuit structure diagram of the voltage subtraction module proposed by the present invention.

Detailed ways

The specific embodiment of the present invention is described below in conjunction with accompanying drawing

The structure of a novel ultra-low power consumption voltage reference circuit of the present invention which can work at 0.45V is shown in Fig. 1, which consists of a bias current module, a high and low gate-source voltage generation module and a voltage subtraction module. The following describes the circuit structure and connection relationship of the modules respectively.

As shown in FIG. 2 , the circuit structure of the bias current module includes a PMOS transistor MP1 , a PMOS transistor MP2 , an NMOS transistor MN1 , an NMOS transistor MN2 and a resistor R. MN1 and MN2 work in the subthreshold region, and the difference between their gate-source voltages is a voltage proportional to temperature (PTAT, Proportional to absolute temperature). The difference between the gate-source voltages just acts on the resistor R, and the PTAT voltage Convert to PTAT current IBIAS.

In the bias current module, the specific connection relationship of the circuit is shown in Figure 2. The source of the PMOS transistor MP1 is connected to the power supply voltage VDD, and the drain is connected to the drain of the NMOS transistor MN1 and the gates of the NMOS transistor MN1 and NMOS transistor MN2; the source of the PMOS transistor MP2 is connected to the power supply voltage VDD, and the gate is connected to the drain to output The bias voltage VB1 is connected to the gate of the PMOS transistor MP1 and the drain of the NMOS transistor MN2; the source of the NMOS transistor MN1 is connected to the ground potential VSS; the source of the NMOS transistor MN2 is connected to the upper end of the resistor R; the lower end of the resistor R is connected to the ground Potential VSS.

As shown in FIG. 3 , the high and low gate-source voltage generation module includes PMOS transistor MP3, PMOS transistor MP4, NMOS transistor MNLV and NMOS transistor MNHV. MP3 and MP4 are used to provide current, MNLV is a low-threshold NMOS transistor, its threshold voltage is VTH1, MNHV is a high-threshold NMOS, its threshold voltage is VTH2, both MNLV and MNHV work in the sub-threshold region, used to generate two temperature-dependent Inversely proportional (CTAT, Complementary to absolute temperature) gate-source voltage VGS1, VGS2:

Among them, m is the subthreshold slope factor, V _T is the hot spot pressure, μ _n is the electron mobility, k ₁ , k ₂ are the current provided by MP3 and MP4 and the multiple of the bias current, (W/L) ₁ , (W /L) ₂ are the width-to-length ratios of MNLV and MNHV, respectively.

In the high and low gate-source voltage generating modules, the circuit connection relationship is shown in Figure 3. The source of the PMOS transistor MP3 is connected to the power supply voltage VDD, the drain is connected to the gate and drain of the NMOS transistor MNLV, and the output voltage VGS1 is connected, and the gate is connected to the bias voltage VB1; the source of the PMOS transistor MP4 is connected to the power supply voltage VDD, and the drain The pole is connected to the gate and drain of the NMOS transistor MNHV, and outputs the voltage VGS2; the drain of the NMOS transistor MNLV is connected to the ground potential VSS; the drain of the NMOS transistor MNHV is connected to the ground potential VSS.

As shown in FIG. 4, the voltage subtraction module includes a PMOS transistor MP5, an NMOS transistor MN3, and an NMOS transistor MN4. MP5 is used to provide current. Both MN3 and MN4 are low-threshold NMOS tubes, and both work in the sub-threshold region. The circuit connection relationship is shown in Figure 4. The source of the PMOS transistor MP5 is connected to the power supply voltage VDD, the drain is connected to the drain of the NMOS transistor MN3, and the gate is connected to the bias voltage VB1; the gate of the NMOS transistor MN3 is connected to the voltage VGS2, and the source is connected to The drain of the NMOS transistor MN4 outputs the reference voltage VREF; the source of the NMOS is connected to the ground potential VSS, and the gate is connected to the voltage VGS1.

The gate-source voltage VGS3 of MN3 can be expressed as:

The gate-source voltage VGS4 of MN4 can be expressed as:

Available:

Substitute VGS1 and VGS2 to get:

Since the threshold voltages can be expressed as:

VTH1(T)＝VTH1(T ₀ )+K _th1 (TT ₀ )

VTH2(T)＝VTH2(T ₀ )+K _th2 (TT ₀ )

It is further simplified to:

Take the first derivative of it to get:

Choose the appropriate Can make it equal to 0, that is, get a voltage that does not change with temperature. Among them, K is Boltzmann's constant, equal to 1.38×10^-23J/K, q is the unit charge, equal to 1.6×10C; VTH1(T ₀ ), VTH2(T ₀ ) are respectively MNLV and MNHV at temperature T ₀ The threshold voltage of K _th2 and K _th1 are the temperature coefficients of VTH1 and VTH2 respectively. The above parameters can be found in the process manual. In the present invention, VTH1(T ₀ ) and VTH2(T ₀ ) are 292mV and 455mV respectively, k ₁ and k ₂ are 2 and 5 respectively, (W/L) ₁ and (W/L) ₂ are both 2μm/10μm, (W/L) ₃ and (W/L) ₄ are 2 μm/10 μm and 3.5 μm/10 μm, respectively.

A kind of ultra-low power consumption voltage reference circuit proposed by the present invention can work at 0.45V. Hspice simulation shows that in the temperature range from -40°C to 150°C, the temperature coefficient of VREF under tt corner is only 47ppm/°C . Under typical conditions (tt corner, 27°C), the power supply voltage VDD = 0.45V, the total current consumption is 21nA, and the total power consumption is 9.45nW.

In summary, it can be seen that the ultra-low power consumption voltage reference circuit proposed by the present invention can work at a low power supply voltage of 0.45V, the power consumption is only 9.45nW, and the operating temperature range is -40 °C to 150 °C, which significantly improves its scope of application and flexibility.

Claims (1)

1. a kind of voltage reference circuit of super low-power consumption, including bias current module, height gate source voltage generation module and voltage Subtraction block, it is characterised in that：

The bias current module includes the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1, the second NMOS tube MN2 and resistance R；The source electrode of the first PMOS tube MP1 connects power supply, its grid connects the drain electrode of the second PMOS tube MP2；2nd PMOS The source electrode of pipe MP2 connects power supply, its grid and drain interconnection；The grid and drain interconnection of first NMOS tube MN1, its drain electrode connect first The drain electrode of PMOS tube MP1, the source electrode ground connection of the first NMOS tube MN1；The drain electrode of 2nd NOMS pipes MN2 connects the second PMOS tube MP2's Drain electrode, the grid of the 2nd NOMS pipes MN2 connect the drain electrode of the first PMOS tube MP1, after the source electrode of the 2nd NOMS pipes MN2 is by resistance R Ground connection；Wherein, the first PMOS tube MP1 grids, the second PMOS tube MP2 grids and the tie point of drain electrode are the defeated of bias current module Outlet, output bias voltage VB1；

The height gate source voltage generation module includes the 3rd PMOS tube MP3, the 4th PMOS tube MP4, Low threshold NMOS tube MNLV With high threshold NMOS tube MNHV；The source electrode of the 3rd PMOS tube MP3 connects power supply, its grid meets bias voltage VB1；Described 4th The source electrode of PMOS tube MP4 connects power supply, its grid meets bias voltage VB1；The drain electrode of the Low threshold NMOS tube MNLV connects the 3rd The drain electrode of PMOS tube MP3, the grid and drain interconnection of Low threshold NMOS tube MNLV, its source electrode ground connection；The high threshold NMOS tube The drain electrode of MNHV connects the drain electrode of the 4th PMOS tube MP4, the grid and drain interconnection of high threshold NMOS tube MNHV, its source electrode ground connection；

The voltage subtraction module includes the 5th PMOS tube MP5, the 3rd NMOS tube MN3, the 4th NMOS tube MN4；Described 5th The source electrode of PMOS tube MP5 connects power supply, its grid meets bias voltage VB1；The drain electrode of the 3rd NMOS tube MN3 connects the 5th PMOS tube The drain electrode of MP5, the drain electrode of the 3rd NMOS tube MN3 connect the drain electrode of the 4th PMOS tube MP4；The drain electrode of the 4th NMOS tube MN4 connects The source electrode of 3rd NMOS tube MN3, the grid of the 4th NMOS tube MN4 connect the drain electrode of the 3rd PMOS tube MP3, the 4th NMOS tube MN4's Source electrode is grounded；The tie point of 3rd NMOS tube MN3 source electrodes and the 4th NMOS tube the MN4 drain electrode is the output of voltage reference circuit End, output reference voltage VREF.