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CN107919343A - 使用埋入式架桥硅穿通孔内连件的半导体封装 - Google Patents

使用埋入式架桥硅穿通孔内连件的半导体封装 Download PDF

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Publication number
CN107919343A
CN107919343A CN201710081919.1A CN201710081919A CN107919343A CN 107919343 A CN107919343 A CN 107919343A CN 201710081919 A CN201710081919 A CN 201710081919A CN 107919343 A CN107919343 A CN 107919343A
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redistribution layer
hole
layer structure
semiconductor packages
silicon
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施信益
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Micron Technology Inc
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Micron Technology Inc
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Priority to CN202010661926.0A priority Critical patent/CN111769093B/zh
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

本发明公开了一种半导体封装，包含：一树脂模塑封装衬底，包含树脂模塑堆芯、多个贯穿树脂模塑堆芯的金属插塞、前侧重分布层结构，以及背侧重分布层结构；一架桥硅穿通孔内连件，埋设于树脂模塑堆芯内，其中架桥硅穿通孔内连件包含一硅基底部、一整体构成在硅基底部上的重分布层结构，以及多个设于硅基底部中的穿硅通孔；一第一半导体芯片及一第二半导体芯片，设于前侧重分布层结构上，其中第一半导体芯片与第二半导体芯片位于共平面。

Description

使用埋入式架桥硅穿通孔内连件的半导体封装
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种2.5D晶圆级封装，其使用树脂模塑封装衬底及埋入式架桥硅穿通孔内连件。
背景技术
2.5D半导体封装，例如CoWoS(Chip-On-Wafer-On-Substrate)技术是本领域所已知的，CoWoS技术通常使用穿硅通孔(TSV)技术将多个芯片结合至单一装置中。
此架构提供了更高密度的互连、降低整体互连长度以及减轻相关的电阻电容负载，从而于更小的形状因子上提高性能及减少功耗。
以往，2.5D半导体封装在硅穿通孔(through-silicon-via,TSV)硅中介层上并排放置多个芯片。芯片通过微凸块与硅中介层贴合，其中微凸块的直径约10μm。硅中介层是通过控制崩塌芯片连接(C4)凸块与封装衬底贴合，其中C4凸块的直径约100μm。
发明内容
本发明涉及一种2.5D半导体封装，其使用树脂模塑封装衬底及埋入式架桥硅穿通孔内连件。
本发明一方面，提出一种半导体封装，包含有：一树脂模塑封装衬底，其包含一树脂模塑堆芯、多个金属插塞，贯穿树脂模塑堆芯的一正面及一背面、一前侧重分布层结构，整体构成在树脂模塑堆芯的正面上，以及一背侧重分布层结构，整体构成在树脂模塑堆芯的背面上。
一架桥硅穿通孔内连件，埋设于树脂模塑堆芯内，其中架桥硅穿通孔内连件包含一硅基底部、一内埋的重分布层结构，整体构成在硅基底部上，以及多个穿硅通孔，设于硅基底部中。
一第一半导体芯片，设于前侧重分布层结构上；一第二半导体芯片，设于前侧重分布层结构上，其中第一半导体芯片与第二半导体芯片位于共平面。多个锡球，设于背侧重分布层结构的一下表面上。
本发明另一方面，提出一种制作半导体封装的方法，首先，提供一第一载板；然后，于第一载板上形成一模版层；再于模版层中形成多个导孔；接着，分别于多个导孔中形成金属插塞；随后移除模版层，于第一载板上留下金属插塞；然后，于第一载板上安装一架桥硅穿通孔内连件。
之后，形成一模塑料，将金属插塞与架桥硅穿通孔内连件包覆起来；接着，抛光模塑料与架桥硅穿通孔内连件，显露出架桥硅穿通孔内连件的穿硅通孔以及埋设在模塑料中的金属插塞。
随后，于模塑料上形成一背侧重分布层结构；再于背侧重分布层结构上形成多个锡球；然后移除所述第一载板；接着，将一第二载板与多个锡球贴合；之后，于模塑料上形成一前侧重分布层结构；接着，将一第一半导体芯片与一第二半导体芯片安置于前侧重分布层结构上；最后，移除第二载板。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
附图包括对本发明的实施例提供进一步的理解，及被并入且构成说明书中的一部份。附图说明一些本发明的实施例，并与说明书一起用于解释其原理。
图1至图3是根据本发明的实施例所绘示的制作架桥硅穿通孔内连件的示例性方法。
图4至图14是根据本发明的实施例所绘示的制作2.5D半导体封装的示例性方法的剖面图，其使用树脂模塑封装衬底及埋入式架桥硅穿通孔内连件。
其中，附图标记说明如下：
100 半导体衬底
110 金属插塞
100a 正面
100b 背面
200 重分布层(RDL)结构
202 介电层
204 金属层
208 接触垫
210 连接件
101 硅穿通孔内连件
300 载板
500 模版层
501 导孔
510 金属插塞
t 厚度
601 硅穿通孔内连件安装区域
550 模塑料
550a 表面
700 重分布层(RDL)结构
712 介电层
714 金属层
718 接触垫
810 锡球
802 防焊层
320 载板
900 重分布层(RDL)结构
10 树脂模塑封装衬底
912 介电层
914 金属层
918 接触垫
11 半导体芯片
12 半导体芯片
111 金属凸块
121 金属凸块
P1 间距
P2 间距
1 晶圆级封装
1a 半导体封装
具体实施方式
在下文中，加以陈述本发明的具体实施方式，该些具体实施方式可参考相对应的附图，使该些附图构成实施方式的一部分。同时也借由说明，揭露本发明可据以施行的方式。该等实施例已被清楚地描述足够的细节，使本领域技术人员可据以实施本发明。其他实施例亦可被加以施行，且对于其结构上所做的改变仍属本发明所涵盖的范畴。
因此，下文的细节描述将不被视为一种限定，且本发明所涵盖的范畴仅被所附的权利要求书以及其同意义的涵盖范围。本发明的一或多个实施例将参照附图描述，其中，相同附图标记始终用以表示相同元件，且其中阐述的结构未必按比例所绘制。
术语“芯片”、“半导体芯片”及“半导体晶粒”于整个说明书中可互换使用。
文中所使用的术语“晶圆”及“衬底”包括任何具有暴露表面的结构，于所述表面上根据本发明沉积一层，例如，形成例如重分布层的电路结构。术语“衬底”被理解为包括半导体晶圆，但不限于此。术语“衬底”亦可用以指加工过程中的半导体结构，且可包括已被制造在其上的其它层。
请参考图1至图3。图1至图3是根据本发明的实施例所绘示的制作架桥硅穿通孔内连件的示例性方法。
如第1所示，首先，提供一半导体衬底(或晶圆)100。根据本发明一实施例，半导体衬底100可包含基材，例如：硅、锗、砷化镓、磷化铟，或碳化硅，用于结构支撑。或者，半导体衬底100可包含聚合物、氧化铍或其它适合用于结构支撑的低成本刚性材料。半导体衬底100具有相对的正面100a及背面100b。
然后，使用机械钻孔、激光钻孔，或深反应离子蚀刻(DRIE)结合金属电镀或沉积法形成多个金属插塞110，其通过部分半导体衬底100，金属插塞110从正面100a延伸至部份半导体衬底100，非完全的贯穿半导体衬底100。
根据本发明一实施例，金属插塞110可包含铝、铜、锡、镍、金、银、钛、钨、多晶硅，或其它合适的导电材料，其可以借由使用电解电镀、无电解电镀工艺，或其它合适的沉积工艺来形成。
如图2所示，用于布线电子信号的重分布层(RDL)结构200形成于正面100a上。RDL结构200可包含至少一介电层202以及至少一金属层204。
根据本发明一实施例，介电层202可包含例如聚亚酰胺(polyimide)等有机材料，或例如氮化硅、氧化硅，或其类似物等无机材料，但不限于此。
金属层204可包含铝、铜、钨、钛、氮化钛，或其类似物。根据所示实施例，金属层204可以包含多个细间距布线，接触垫208从介电层202的顶表面显露出来。连接件210(例如，微凸块)可以形成在接触垫208上。金属层204的一部分可以电连接至金属插塞110。
应理解的是，金属层204和接触垫208的层和布局仅用于说明的目的。根据设计要求，在其他实施例中，可以在RDL结构200中形成更多层的金属布线。
随后，如图3所示，对具有RDL结构200的半导体衬底100进行一切割工艺，并且通过晶圆切割工艺，切割成个别的硅穿通孔内连件101。
请参考图4至图14。图4至图14是根据本发明的实施例所绘示的制作2.5D半导体封装的示例性方法的剖面图，其使用树脂模塑封装衬底及埋入式架桥硅穿通孔内连件。
如图4所示，首先，提供一载板300。载板300可为一可被撕除的基材。载板300可包含玻璃、硅、陶瓷、金属或任何合适的支撑材料。可以在载板300的顶表面上提供介电层或钝化层。钝化层可以包括例如聚亚酰胺(PI)等有机材料或例如氮化硅、氧化硅，或其类似物等无机材料，但不限于此。
随后，在载板300上涂覆一模版层500。例如，模版层500可以是一光刻胶层，例如，I-line光刻胶层或定向自组装(DSA)材料，但不限于此。
借由例如光刻工艺在模版层500中形成导孔501。每个导孔501延伸通过模版层500的整个厚度。根据本发明一实施例，导孔501可具有相同的通孔直径或尺寸。根据本发明其他实施例，导孔501可具有不同的通孔直径。
如图5所示，在形成导孔501之后，分别于导孔501中形成金属插塞510。根据本发明一实施例，导孔501被金属完全填满，金属例如铜、钨、铝、钛、氮化钛或其类似物，从而形成金属插塞510。金属插塞510可以借由沉积、网版印刷或任何合适的方法形成。
可选择地，可以进行一化学机械抛光(CMP)工艺以去除导孔501外面的多余金属。根据本发明一实施例，金属插塞510可以具有与模版层500的厚度一样的高度。根据本发明一实施例，金属插塞510可以具有相同的通孔直径或尺寸。根据本发明其他实施例，金属插塞510可以具有不同的通孔直径。
根据本发明一实施例，金属插塞510可作为前侧RDL结构和背侧RDL结构(例如用于传递电源或接地信号)、散热件或应力调节件(虚设金属插塞)之间的互连。
如图6所示，在形成金属插塞510之后，完全移除模版层500，留下完整的金属插塞510。例如，当含有光刻胶层时，模板层500可以通过等离子体蚀刻或灰化工艺去除。此时，柱状金属插塞510被显露出来。这些柱状金属插塞510围绕硅穿通孔内连件安装区域601。
如图7所示，如图3所示的硅穿通孔内连件101被180度翻转并且安装在载板300内的硅穿通孔内连件安装区域601上。连接件210可以与载板300直接接触。金属插塞510可以具有比金属插塞110的直径更大的直径。
如图8所示，形成一模塑料550，将金属插塞510、硅穿通孔内连件101及载板300的顶表面包覆起来。可对模塑料550进行一固化工艺。模塑料550可包含环氧树脂和硅石填料的混合物，但不限于此。模塑料550的层厚度比硅穿通孔内连件101的厚度厚。RDL结构200埋设在模塑料550中(内埋的RDL结构)。
如图9所示，进行一抛光工艺，移除模塑料550的上部，以显露出金属插塞510的顶表面及金属插塞110的顶表面。此时，背面100b与模塑料550的表面550a共平面。
如图10所示，于模塑料550及金属插塞510上形成一重分布层(RDL)结构700。RDL结构700用作背侧(或PCB侧)RDL结构。RDL结构700可以包含至少一介电层712和至少一金属层714。
根据本发明一实施例，介电层712可包含例如聚亚酰胺(polyimide)等有机材料，或例如氮化硅、氧化硅，或其类似物等无机材料，但不限于此。
金属层714可包含铝、铜、钨、钛、氮化钛，或其类似物。根据所示实施例，金属层714可以包含多个布线，接触垫718从介电层712的顶表面显露出来。
应理解的是，金属层714和接触垫718的层和布局仅用于说明的目的。根据设计要求，在其他实施例中，可以在RDL结构700中形成更多层的金属布线。
随后，在接触垫718上形成锡球810，例如球型格栅矩阵(ball grid array,BGA)锡球。应理解的是，防焊层802可以形成在RDL结构700上。在形成锡球810之前，可以在接触垫718上形成凸块下金属(UBM)层(未明确示于图中)。
接着，如图11所示，移除载板300，暴露出金属插塞510的另一端和连接件210的顶表面。然后，将中间晶圆级产品接合到载板320，其中锡球810与载板320直接接触。载板320可包括玻璃、硅、陶瓷、金属或任何合适的支撑材料。可以在载板320上提供一黏着剂层(未明确示于图中)，并且锡球810可以通过黏着剂层黏附至载板320。
如图12所示，于模塑料550、金属插塞510及连接件210上形成一重分布层(RDL)结构900，完成具有树脂模塑堆芯(模塑料550)的树脂模塑封装衬底10。RDL结构900用作前侧(或芯片侧)RDL结构。RDL结构900可以包含至少一介电层912和至少一金属层914。
根据本发明一实施例，介电层912可包含例如聚亚酰胺(polyimide)等有机材料，或例如氮化硅、氧化硅，或其类似物等无机材料，但不限于此。
金属层914可包含铝、铜、钨、钛、氮化钛，或其类似物。根据所示实施例，金属层914可以包含多个布线，接触垫918从介电层914的顶表面显露出来。
应理解的是，金属层914和接触垫918的层和布局仅用于说明的目的。根据设计要求，在其他实施例中，可以在RDL结构900中形成更多层的金属布线。
如图13所示，将半导体芯片11与半导体芯片12设置在RDL结构900上。半导体芯片11与半导体芯片12可为覆晶芯片。半导体芯片11与半导体芯片12分别通过接触垫918和金属凸块111及121电连接至RDL结构900。
根据本发明一实施例，金属凸块111及121具有一凸块间距P1，其与半导体芯片11与半导体芯片12的输出/输入垫间距相同。例如，凸块间距P1可以小于100微米。锡球810具有一锡球间距P2，其与一印刷电路板(PCB)或母板上的球垫间距相同。
可选择地，另一种模塑料可以通过转移模塑施加到半导体芯片11和半导体芯片12上，但不限于此。随后，可以移除载板320。
如图14所示，可进行一切割工艺，将晶圆级封装1切割成个别的2.5D半导体封装1a。根据本发明一实施例，省略了安装在半导体芯片和封装衬底之间的常规中介层元件。
本发明一方面，提出一种半导体封装1a，包含有：一树脂模塑封装衬底10，其包含一树脂模塑堆芯(即模塑料550)、多个金属插塞510，贯穿树脂模塑堆芯550的一正面及一背面、一前侧重分布层结构900，整体构成在树脂模塑堆芯550的正面上，以及一背侧重分布层结构700，整体构成在树脂模塑堆芯550的背面上。在前侧RDL结构900和树脂模塑堆芯550之间或在背侧RDL结构700和树脂模塑堆芯550之间没有形成间隙。
一架桥硅穿通孔内连件101，埋设于树脂模塑堆芯550内，其中架桥硅穿通孔内连件101包含一硅基底部100、一内埋的重分布层结构200，整体构成在硅基底部100上，以及多个穿硅通孔110，设于硅基底部100中。
多个连接件210，埋设于树脂模塑堆芯550内，其中多个连接件210介于架桥硅穿通孔内连件101的重分布层结构200与前侧重分布层结构900之间。
一第一半导体芯片11，设于前侧重分布层结构900上；一第二半导体芯片12，设于前侧重分布层结构900上，其中第一半导体芯片11与第二半导体芯片12位于共平面。多个锡球810，设于背侧重分布层结构700的一下表面上。
根据本发明一实施例，第一半导体芯片11与第二半导体芯片12经由前侧重分布层结构900与多个金属插塞510电连接至背侧重分布层结构700。根据本发明一实施例，电源信号或接地信号经由多个金属插塞510传递，因为金属插塞510的较大直径能够提供较低的电阻和改善的信号完整性。
根据本发明一实施例，第一半导体芯片11与第二半导体芯片12通过前侧重分布层结构900、或以其他方式经由前侧重分布层结构900、多个连接件210及重分布层结构200彼此电连接。因此，硅穿通孔内连件101用作第一半导体芯片11和第二半导体芯片12之间的信号传输桥，并且可以被称为架桥硅穿通孔内连件。
根据本发明一实施例，第一半导体芯片11与第二半导体芯片12通过前侧重分布层结构900、多个连接件210、重分布层结构200及金属插塞110与重分布层结构700互相电连接。例如，可以通过此路径传递例如高频信号等的数字信号。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (16)

1.一种半导体封装，其特征在于，包含有：
一树脂模塑封装衬底，包含一树脂模塑堆芯、多个金属插塞，贯穿所述树脂模塑堆芯的一正面及一背面、一前侧重分布层结构，整体构成在所述树脂模塑堆芯的所述正面上，以及一背侧重分布层结构，整体构成在所述树脂模塑堆芯的所述背面上；
一架桥硅穿通孔内连件，埋设于所述树脂模塑堆芯内，其中所述架桥硅穿通孔内连件包含一硅基底部、一内埋的重分布层结构，整体构成在所述硅基底部上，以及多个穿硅通孔，设于所述硅基底部中，其中所述多个穿硅通孔电连接所述背侧重分布层结构；
多个连接件，埋设于所述树脂模塑堆芯内，其中所述多个连接件介于所述架桥硅穿通孔内连件的所述重分布层结构与所述前侧重分布层结构之间；
一第一半导体芯片，设于所述前侧重分布层结构上；
一第二半导体芯片，设于所述前侧重分布层结构上，其中所述第一半导体芯片与所述第二半导体芯片位于共平面；以及
多个锡球，设于所述背侧重分布层结构的一下表面上。
2.根据权利要求1所述的半导体封装，其特征在于，所述第一半导体芯片与所述第二半导体芯片分别通过多个第一金属凸块与多个第二金属凸块设置在所述前侧重分布层结构上。
3.根据权利要求2所述的半导体封装，其特征在于，所述多个第一金属凸块与所述多个第二金属凸块具有一凸块间距，其与所述第一半导体芯片与所述第二半导体芯片的输出/输入垫间距相同。
4.根据权利要求3所述的半导体封装，其特征在于，所述凸块间距小于100微米。
5.根据权利要求3所述的半导体封装，其特征在于，所述锡球具有一锡球间距，其与一印刷电路板或母板上的球垫间距相同。
6.根据权利要求1所述的半导体封装，其特征在于，所述第一半导体芯片与所述第二半导体芯片经由所述前侧重分布层结构与所述多个金属插塞电连接至所述背侧重分布层结构。
7.根据权利要求6所述的半导体封装，其特征在于，电源信号或接地信号经由所述多个金属插塞传递。
8.根据权利要求1所述的半导体封装，其特征在于，所述第一半导体芯片与所述第二半导体芯片通过所述前侧重分布层结构、所述多个连接件与所述架桥硅穿通孔内连件的所述重分布层结构互相电连接。
9.根据权利要求1所述的半导体封装，其特征在于，数字信号经由所述前侧重分布层结构、所述多个连接件、所述架桥硅穿通孔内连件的所述重分布层结构，及所述架桥硅穿通孔内连件的所述多个穿硅通孔传递。
10.根据权利要求1所述的半导体封装，其特征在于，所述架桥硅穿通孔内连件被一模塑料模封包覆。
11.一种制作半导体封装的方法，其特征在于，包含有：
提供一第一载板；
于所述第一载板上形成一模版层；
于所述模版层中形成多个导孔；
分别于所述多个导孔中形成金属插塞；
移除所述模版层，于所述第一载板上留下所述些金属插塞；
于所述第一载板上安装一架桥硅穿通孔内连件；
形成一模塑料，将所述些金属插塞与所述架桥硅穿通孔内连件包覆起来；
抛光所述模塑料与所述架桥硅穿通孔内连件，显露出所述架桥硅穿通孔内连件的穿硅通孔以及埋设在所述模塑料中的所述些金属插塞；
于所述模塑料上形成一背侧重分布层结构；
于所述背侧重分布层结构上形成多个锡球；
移除所述第一载板；
将一第二载板与所述多个锡球贴合；
于所述模塑料上形成一前侧重分布层结构；
将一第一半导体芯片与一第二半导体芯片安置于所述前侧重分布层结构上；以及
移除所述第二载板。
12.根据权利要求11所述的制作半导体封装的方法，其特征在于，所述模版层包含一光刻胶层或一定向自组装材料。
13.根据权利要求11所述的制作半导体封装的方法，其特征在于，所述架桥硅穿通孔内连件包含一硅基底部、一重分布层结构，整体构成在所述硅基底部上，以及多个穿硅通孔，设于所述硅基底部中。
14.根据权利要求13所述的制作半导体封装的方法，其特征在于，多个连接件，其中所述多个连接件介于所述架桥硅穿通孔内连件的所述重分布层结构与所述前侧重分布层结构之间。
15.根据权利要求13所述的制作半导体封装的方法，其特征在于，所述多个连接件被所述模塑料模封包覆。
16.根据权利要求11所述的制作半导体封装的方法，其特征在于，所述多个导孔被金属完全填满，如此形成所述些金属插塞。
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US10833052B2 (en) 2020-11-10
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