CN107863066A - Shift register, display panel, display device and driving method - Google Patents
Shift register, display panel, display device and driving method Download PDFInfo
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- CN107863066A CN107863066A CN201711236517.0A CN201711236517A CN107863066A CN 107863066 A CN107863066 A CN 107863066A CN 201711236517 A CN201711236517 A CN 201711236517A CN 107863066 A CN107863066 A CN 107863066A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a shift register, a display panel, a display device and a driving method. According to the invention, the first output end of the trigger in the shift register provides the first pulse signal to the first output end of the shift register, the first NOR gate in the shift register provides the second pulse signal to the second output end of the shift register, and the shift register circuit for providing the first pulse signal and the shift register circuit for providing the second pulse signal are arranged in the same shift register circuit, so that the area of the display panel occupied by the shift register circuits is reduced, and the design of a narrow frame is facilitated. Meanwhile, the NOR gate circuit is adopted to enable the low level output of the shift register to be more stable, and the NOR gate circuit is more beneficial to the output of the second output end of the shift register.
Description
Technical field
The present embodiments relate to display technology field, more particularly to a kind of shift register, display panel, display device
And driving method.
Background technology
With the development of Display Technique, the dimensions of display is more and more diversified, and frame is more and more narrow.Organic light emission
Diode (Organic Light-Emitting Diode, OLED) display is because having the characteristics such as frivolous, power saving, more and more extensively
It is used in generally in various portable electric appts.
Pel array is generally included in OLED display panel and each OLED into array provides the picture of driving current
Plain drive circuit.Multiple shift LDs for providing signal to pixel-driving circuit are typically also set up in OLED display panel
Device, circuit layout shared by the shift register is bigger, is unfavorable for the developing direction that display panel realizes narrow frame.
The content of the invention
The present invention provides a kind of shift register, display panel, display device and driving method, reduces shift LD electricity
The area for the display panel that road takes, is advantageously implemented the design of narrow frame.Make the low level output of shift register more simultaneously
Stable, the second output end output to shift register is more favourable.
In a first aspect, the embodiments of the invention provide a kind of shift register, it is defeated that the shift register includes the first signal
Enter end, secondary signal input and the 3rd signal input part, the first output end, the second output end, trigger and first or non-
Door；
The trigger signal input of the trigger electrically connects with first signal input part, the set of the trigger
Input electrically connects with the secondary signal input CK；The trigger includes at least one nor gate, the trigger
First output end is used to provide the first pulse signal to the first output end of the shift register；
The first input end of first nor gate electrically connects with the second output end of the trigger, and described first or non-
Second input of door electrically connects with the 3rd signal input part, and first nor gate is used for the shift register
Second output end provides the second pulse signal.
Second aspect, the embodiment of the present invention additionally provide a kind of display panel, and the display panel includes multiple present invention and appointed
The shift register that embodiment of anticipating provides, multiple shift register cascades, the first signal of shift register described in rear stage are defeated
Enter end to electrically connect with the second output end of the trigger of shift register described in its upper level.
The third aspect, the embodiment of the present invention additionally provide a kind of display device, and it is any real that the display device includes the present invention
The display panel of example offer is provided.
Fourth aspect, the embodiment of the present invention additionally provide a kind of driving method, and any embodiment of the present invention can be driven to provide
Display panel work, the driving method includes：
The first clock signal is provided to first clock cable, second clock is provided to the second clock signal wire
Signal；
Wherein, first clock signal and the second clock signal include periodically alternate first level signal
With second electrical level signal；
Duration of the first level signal in first clock signal covers the in the second clock signal
The duration of two level signals；
Duration of the first level signal in the second clock signal covers the in first clock signal
The duration of two level signals.
The present invention will can be used to provide the first pulse by setting trigger and the first nor gate in a shift register
The shift register circuit of the second pulse signal of shift register circuit and offer of signal is arranged at same shift register circuit
In, the area of the display panel shared by shift register circuit is reduced, is advantageously implemented the design of narrow frame.Meanwhile use
OR-NOT circuit makes the low level output of shift register more stable, and the second output end output to shift register is more favourable.
Brief description of the drawings
Fig. 1 is a kind of electrical block diagram of shift register provided in an embodiment of the present invention；
Fig. 2 is a kind of driver' s timing figure provided in an embodiment of the present invention；
Fig. 3 is the structural representation of another shift register provided in an embodiment of the present invention；
Fig. 4 is another driver' s timing figure provided in an embodiment of the present invention；
Fig. 5 is the circuit structure diagram of nor gate in shift register provided in an embodiment of the present invention；
Fig. 6 is the circuit structure diagram of the first phase inverter provided in an embodiment of the present invention；
Fig. 7 is the electrical block diagram of another shift register provided in an embodiment of the present invention；
Fig. 8 is the electrical block diagram of another shift register provided in an embodiment of the present invention；
Fig. 9 is the electrical block diagram of another shift register provided in an embodiment of the present invention；
Figure 10 is the electrical block diagram of another shift register provided in an embodiment of the present invention；
Figure 11 is a kind of structural representation of display panel provided in an embodiment of the present invention；
Figure 12 is another driver' s timing figure provided in an embodiment of the present invention；
Figure 13 is a kind of structural representation of display device provided in an embodiment of the present invention.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
Part related to the present invention rather than entire infrastructure are illustrate only in description, accompanying drawing.
Fig. 1 is a kind of electrical block diagram of shift register provided in an embodiment of the present invention, and the present embodiment is advantageous to
The narrow frame design of OLED display panel is realized, with reference to figure 1, the shift register includes the first signal input part STV, the second letter
Number input CK and the 3rd signal input part CKB, the first output end emit, the second output end Gout, trigger D1 and first
Nor gate Q1；
Trigger D1 trigger signal input D electrically connects with the first signal input part STV, the set input of trigger
CP electrically connects with secondary signal input CK；Trigger D1 includes at least one nor gate, trigger D1 the first output end
For providing the first pulse signal to the first output end emit of shift register；
First nor gate Q1 first input end electrically connects with trigger D1 the second output end Q, the first nor gate Q1's
Second input electrically connects with the 3rd signal input part CKB, and the first nor gate Q1 is used for the second output end to shift register
Gout provides the second pulse signal.
Wherein, the first pulse signal that the first output end emit of shift register is provided can be used as luminous for driving
The LED control signal of control signal wire.The second pulse signal that second output end Gout of shift register is provided can conduct
For driving the scanning drive signal of scan signal line.
Wherein, trigger D1 can be d type flip flop, trigger D1 the first output endIt is trigger D1 the second output
Hold Q non-value.When pulse-free signal acts on, when secondary signal input CK is " 0 " or " 1 ", trigger D1 is blocked, no matter the
Why one signal input part STV input signals are worth, d type flip flop D1 the first output endWith the second output end Q output state
Keep constant, it is and identical on last stage.When there is impulse action, in the rising edge or trailing edge of pulse, now trigger D1
It is defeated in secondary signal input CK with reset and set function, such as the trigger D1 in rising edge triggering mode
Enter the rising edge time of pulse signal, trigger D1 the first output endChange with the second output end Q signal condition, triggering
The signal of device D1 the second output end Q outputs is identical with the state of the first signal input part STV signals inputted, other times section
The signal of trigger D1 the second output end Q outputs keeps it in the rising edge of secondary signal input CK input pulse signals
The state at quarter, until next rising edge of secondary signal input CK input pulse signals arrives, the second of trigger D1 exports
The signal intensity for holding Q outputs is identical with the state of the signal of the first signal input part CK inputs.Wherein " 1 " can represent high electricity
Flat, " 0 " represents low level.For the trigger D1 in trailing edge triggering mode, believe in secondary signal input CK input pulses
Number trailing edge arrive when, trigger D1 the first output endChange with the second output end Q signal condition, trigger D1's
The signal of second output end Q outputs is identical with the state of the first signal input part STV signals inputted, other times section trigger
The signal of D1 the second output end Q outputs keeps its shape at the trailing edge moment of secondary signal input CK input pulse signals
State, until next trailing edge of secondary signal input CK input pulse signals arrives, trigger D1 the second output end Q is exported
Signal intensity be with the first signal input part CK input signal state it is identical.Believe when the first signal input part STV is inputted
Number it is " 1 ", when secondary signal input CK produces trailing edge, trigger D1 the first output endExport " 0 ", the second output end
Q exports " 1 ".The first output end emit output low level signals of shift register, trigger D1 the second output end Q outputs
High level signal gives the first nor gate Q1 first input end.No matter the 3rd signal input part CKB exports " 1 " or " 0 ", and displacement is posted
Second output end Gout of storage exports low level.
When the first signal input part STV input signals are " 0 ", and secondary signal input CK produces trailing edge, d type flip flop
D1 the first output endExport " 1 ", the second output end Q outputs " 0 ".The high electricity of the first output end emit outputs of shift register
The first nor gate Q1 first input end is given in ordinary mail number, " 0 " of the second output end Q outputs.When the 3rd signal input part CKB is inputted
When " 0 ", the second output end Gout output high level of shift register；When the 3rd signal input part CKB inputs " 1 ", displacement
The second output end Gout output low levels of register.
Exemplarily, Fig. 2 is a kind of driver' s timing figure provided in an embodiment of the present invention, with reference to figure 1 and Fig. 2, wherein E1 tables
Show the signal of the first output end output of shift register, G1 represents the signal of the second output end output of shift register, M1
Represent the signal of trigger D1 the second output end Q outputs.At the k1 moment, the secondary signal input CK inputs of shift register
The trailing edge of signal arrives, and the enabling signals of the first signal input part STV inputs of shift register is low level, trigger D1
The second output end output signal state change, the states of trigger D1 the second output end Q output signals and the first signal
The state of input STV input signals is identical, is low level.From the K1 moment to the t1 stages at K2 moment, the of shift register
The signal of binary signal input CK inputs does not produce trailing edge, in this stage, trigger D1 the first output endWith second
The signal of output end Q outputs is constant, first output end identical with the K1 momentFor high level, the second output end Q is low level.
At the K2 moment, the trailing edge of the secondary signal input CK input signals of shift register arrives, trigger D1 the second output
The state change of Q output signals is held, the state change of the second output end Q output signals is to be inputted with the first signal input part STV
The state of signal is identical, and because the signal of the first signal input part STV inputs is high level, trigger D1 the second output end Q is defeated
Go out high level.Stage after the K2 moment, although the signal of shift register D1 secondary signal input CK inputs occurs
Trailing edge, but the first signal input part STV input signals for high level, therefore trigger D1 the second output end Q continue it is defeated
Go out high level.In the t1 stages, trigger D1 the second output end output Q1 output low levels, i.e. M nodes are low level, M nodes
Signal and the 3rd signal end CKB input signal input the first nor gate Q1, in the t11 stages, shift register the 3rd letter
Number input CKB input high level signals, in the t11 stages, the first nor gate Q1 output high level.In the t12 stages, the 3rd signal
Input CKB input low levels, the first nor gate Q1 output high level, i.e. t12 stages, the second output end of shift register
Gout exports high level.
It should be noted that said process is only to a kind of example that transistor is PMOS transistor, when transistor is
During nmos pass transistor, driver' s timing is opposite with the low and high level of the timing diagram in Fig. 2.
The technical scheme of the embodiment of the present invention, by the first output end of trigger in shift register to shift register
The first output end the first pulse signal is provided, the first nor gate in shift register is second defeated to the shift register
Go out end and the second pulse signal is provided, by for providing the shift register circuit of the first pulse signal and providing the second pulse signal
Shift register circuit be arranged in same shift register circuit, i.e., same shift register can export turntable driving letter
Number, and can output LED control signal, the same two kinds of signal of shift register output, save the number of shift register
Amount, reduces the area of the display panel shared by shift register circuit, is advantageously implemented the design of narrow frame.And using the
One OR-NOT circuit, the first nor gate export the second pulse signal to the second output end for shifting shift register, shift LD
The output of device level is more stable, such as shift register exports low level for a long time, and nor gate output low level is stable, improves electricity
The reliability on road.
Fig. 3 is the structural representation of another shift register provided in an embodiment of the present invention, as shown in figure 3, trigger
D1 includes the first phase inverter F1, the second nor gate Q2, the 3rd nor gate Q3, four nor gate Q4 and the 5th nor gate Q5；
First phase inverter F1 input electrically connects with the first signal input part STV, the first phase inverter F1 output ends and the
Two nor gate Q2 first input end electrical connection；
Second nor gate Q2 the second input electrically connects with secondary signal input CK, the second nor gate Q2 output end
Electrically connected with the first input end of the 4th or non-Q4 doors；
3rd nor gate Q3 first input end electrically connects with the first signal input part STV, and the second of the 3rd nor gate Q3
Input electrically connects with secondary signal input CK, the 3rd nor gate Q3 output end and the 5th nor gate Q5 first input end
Electrical connection；
Four nor gate Q4 the second input electrically connects with the 5th nor gate Q5 output end, and four nor gate Q4's is defeated
Go out end to electrically connect with the first output end emit of shift register；
5th nor gate Q5 the second input electrically connects with four nor gate Q4 output end, and the 5th nor gate Q5's is defeated
Go out end to electrically connect with the first nor gate Q1 first input end.
Fig. 4 is another driver' s timing figure provided in an embodiment of the present invention.As shown in Figure 3 and Figure 4, when shift register
The first pulse signal that first output end emit is provided, which can be used as, to be used to drive the LED control signal of LED control signal line,
The second pulse signal that second output end Gout of shift register is provided can be as the scanning for driving scan signal line
During drive signal, scanning drive signal and LED control signal can be supplied to picture by scan line and LED control signal line respectively
Plain circuit, the transistor turns in image element circuit are driven, to be charged to pixel process, when the transistor of driving is PMOS transistor
Turned on during the grid access low level of PMOS transistor, detailed process illustrates shift LD by taking PMOS transistor as an example herein
The operation principle of device.
As shown in figure 4, the first signal input part STV input enabling signal, the timing diagram of the first phase inverter F1 output ends with
It is on the contrary, the timing diagram of the N nodes in i.e. Fig. 4.The enabling signal sequential inputted due to N nodes and the first signal input part STV
On the contrary, four nor gate Q4 and the 5th nor gate Q5 forms latch.Only have in the signal of secondary signal input CK inputs
When high level saltus step is low level, one in the second nor gate Q2 and the 3rd nor gate Q3 could export low level, could be right
The latch that four nor gate Q4 and the 5th nor gate Q5 is formed carries out set, such as four nor gate Q4 output end output
" 0 ", the output end output " 1 " of the 5th nor gate is puts 1, and four nor gate Q4 output end exports " 1 ", the 5th nor gate Q5's
Output end output " 0 " is to set to 0.In other stages, the latch that four nor gate Q4 and the 5th nor gate Q5 are formed remains original
State it is constant.At the K1 moment, when secondary signal input CK starts to input effective low level, in secondary signal input CK
Produce trailing edge, N nodes be high level, the second nor gate Q2 output low levels, and the 3rd nor gate Q3 exports high level, the 4th or
NOT gate Q4 exports high level, and four nor gate Q4 exports high level to the first output end emit of shift register, shift LD
The first output end emit output high level of device；5th nor gate exports low level, i.e. the second output end Q (M of trigger D1
Point) output low level.In the t11 stages, four nor gate Q4 and the 5th nor gate Q5 output keep it is constant, with the K1 moment just as.
In the t12 stages, in the t12 stages, when secondary signal input CK input high levels, the second nor gate Q2 output low levels, the
Three nor gate Q3 export low level, and the latch that four nor gate Q4 and the 5th nor gate Q5 are formed maintains the state in t11 stages
It is constant.M nodes are low level, the signal of the low level signal of M nodes and the 3rd signal input part CKB inputs input to first or
NOT gate Q1 two inputs, in the t11 stages, the first nor gate Q1 output high level, in the t12 stages, the first nor gate Q1 is defeated
Go out low level.At the K2 moment, the trailing edge of the signal of the secondary signal input CK inputs of shift register arrives, by high level
It is changed into low level, the signal of the first signal input part STV inputs is high level, and N nodes are low level, and the second nor gate Q2 is exported
High level, the 3rd nor gate Q3 output low levels, then four nor gate Q4 outputs low level, the 5th nor gate Q5 outputs are high electric
It is flat, the second output end Gout output low levels of shift register；Stage after K2, the first signal input part STV are height
Level, during secondary signal input CK input high levels, the second nor gate Q2 and the 3rd nor gate Q2 export low level, and the 4th
Nor gate Q4 and the 5th nor gate Q5 output remain unchanged, therefore after the K2 stages, output and the K2 stages of shift register
It is identical.
Fig. 5 is the circuit structure diagram of nor gate in shift register provided in an embodiment of the present invention, as shown in figure 5, displacement
Register also includes the first level signal input VGH and second electrical level signal input part VGL；First nor gate Q1, second or
It is at least one including the first transistor T1, in NOT gate Q2, the 3rd nor gate Q3, four nor gate Q4 and the 5th nor gate Q5
Two-transistor T2, third transistor T3 and the 4th transistor T4；
The first transistor T1 the first pole electrically connects with the first level signal VGH inputs, the second pole and second transistor
T2 the first pole electrical connection, grid electrically connect with the first input end A of the nor gate；
Second transistor T2 the second pole electrically connects with the output end X of the nor gate, the second of grid and the nor gate defeated
Enter to hold B to electrically connect；
Third transistor T3 the first pole electrically connects with second electrical level signal input part VGL, the second pole and second transistor
T2 the second pole electrical connection, grid electrically connect with second transistor T2 grid；
4th transistor T4 the first pole electrically connects with second electrical level signal input part VGL, the second pole and third transistor
T3 the second pole electrical connection, grid electrically connect with the first transistor T1 grid；
Wherein, the first transistor T1 is identical with second transistor T2 conducting channel, third transistor T3 and the 4th crystal
Pipe T4 conducting channel is identical, and the first transistor T1 and third transistor T3 conducting channel is different.
By taking Fig. 5 as an example, and using the first transistor T1 and second transistor T2 as PMOS, third transistor T3 and the 4th is brilliant
Body pipe T4 is NMOS tube, and the signals of the first level signal input VGH inputs is high level signal, second electrical level signal input part
The signal of VGL inputs is to illustrate the course of work of the nor gate exemplified by low level signal.When the first input end A of nor gate is height
Level, when the second input B is high level, the first transistor T1 and second transistor T2 cut-offs, third transistor T3 and the 4th
Transistor T4 is turned on, third transistor T3 and the 4th transistor T4 by second electrical level signal input part VGL signal transmit to or
The output end X of NOT gate, nor gate output low level signal.When the first input end A of nor gate is high level, the second input B
For low level when, the first transistor T1 and third transistor T3 cut-off, second transistor T2 and the 4th transistor T4 conducting, now
Second electrical level signal input part VGL signal is transmitted to the output end X of nor gate, nor gate and exports low electricity by the 4th transistor T4
Ordinary mail number.When the first input end A of nor gate is low level, when the second input B is high level, the first transistor T1 and the 3rd
Transistor T3 is turned on, and second transistor T2 and the 4th transistor T4 cut-offs, now third transistor T3 is defeated by second electrical level signal
Enter to hold VGL signal to transmit to the output end X of nor gate, nor gate output low level signal.As the first input end A of nor gate
For low level, when the second input B is low level, the first transistor T1 and second transistor T2 conductings, third transistor T3 and
4th transistor T4 ends, and now the first transistor T1 and second transistor T2 is by the first level signal input VGH signal
Transmit to the output end X of nor gate, nor gate output high level signal.It follows that as the first input end A of nor gate and
When two input B are low level, the output end X of nor gate exports the first level signal input VGH signal, works as nor gate
First input end A and the second input B it is at least one when being high level, the output end X output second electrical level signals of nor gate
Input VGL signal.As seen from Figure 4, when nor gate output end X outputs second electrical level signal input part VGL signal,
Only by a transistor (third transistor T3 either the 4th transistor T4) when exporting low level signal, therefore output end
The pressure difference of the signal and second electrical level signal input part VGL of X outputs is smaller, i.e. the signal voltage and second electrical level of nor gate output
Signal input part VGL signal voltage difference is small, and the level signal stability of output is good.And general, second electrical level signal input
It is low level to hold VGL signals, refers to the waveform in Fig. 2, G1 signals keep low level for a long time, and nor gate output is low
Level signal is relatively stable, in this way, the circuit in shift register can keep stable state for a long time, what raising circuit worked can
By property.
It should be noted that the type of transistor is only a kind of example in Fig. 5, in other embodiment party of the embodiment of the present invention
In formula, the first transistor T1 and second transistor T2 can also be NMOS tubes, and third transistor T3 and the 4th transistor T4 are
PMOS.
The technical scheme of the present embodiment, the signal of the first level signal input is exported by nor gate or second electrical level is believed
The signal of number input, only pass through a transistor when exporting the signal of second electrical level signal input part, the signal of output and
The signal difference of second electrical level signal input part is small, and the level signal stability of output is good.
Fig. 6 is the circuit structure diagram of the first phase inverter provided in an embodiment of the present invention.As shown in fig. 6, the first phase inverter F1
Including the 5th transistor T5 and the 6th transistor T6.
5th transistor T5 the first pole electrically connects with the first level signal input VGH, the second pole and the first phase inverter
F1 output end electrical connection and the electrical connection of grid and the first phase inverter F1 input；
6th transistor T6 the first pole electrically connects with second electrical level signal input part VGL, the second pole and the 5th transistor
T5 the second pole electrical connection and grid electrically connect with the 5th transistor T5 grid.
5th transistor T5 and the 6th transistor T6 conducting channel is different.
As shown in fig. 6, exemplarily, the 5th transistor T5 is PMOS, the 6th transistor T6 is NMOS tube.When first anti-
During phase device F1 input C input high levels, the 5th transistor T5 cut-offs, the 6th transistor T6 conductings, the first phase inverter F1's
The signal of output end Y output second electrical level signal input part VGL inputs；When the first phase inverter F1 input C input low levels
When, the 5th transistor T5 conductings, the 6th transistor T6 ends, and the first phase inverter F1 the first level signal of output end Y outputs is defeated
The signal for entering to hold VGH to input.
When the first level signal input VGH signal is high level, second electrical level signal input part VGL signal is low
During level, when the first phase inverter F1 input C is high level, it exports low level, and high electricity is exported when input C is low level
It is flat, realize anti-phase effect.
It should be noted that the 5th transistor T5 can also be NMOS tube, the 6th transistor T6 is PMOS, and its work is former
Reason is similar with the operation principle of the circuit shown in Fig. 6, and here is omitted.
Fig. 7 is the electrical block diagram of another shift register provided in an embodiment of the present invention, as shown in fig. 7,
On the basis of above-described embodiment, the shift register also includes M the second phase inverter F2；
First the second phase inverter F2 input electrically connects with the first nor gate Q1 output end；
Second to the second phase inverter of m-th F2 input electrically connects with its previous second phase inverter F2 output end；
The second phase inverter of m-th F2 output end electrically connects with the second output end Gout of shift register；
Wherein M is the integer more than or equal to 1.
As shown in fig. 7, the type for the signal that the second phase inverter F2 number needs to export according to shift register determines, example
Such as when shift register output end electrically connects with a scan line, scan line and the switching transistor of the image element circuit in pixel
Grid connects, and the channel type for the switching transistor that can be connected according to scan line determines.When the switch crystal in image element circuit
The transistor for P-channel is managed, grid needs to access low level signal when it is turned on, therefore the second phase inverter F2 can include even number
It is individual；When the switching transistor in image element circuit is the transistor of N-channel, grid needs to access high level signal when it is turned on,
Therefore the second phase inverter F2 can include odd number.Second phase inverter F2 is used for the driving fan-out capability for improving shift register,
Second phase inverter F2 number can determine according to the type of the switching transistor in image element circuit, improve shift register
Flexibility, add the use range of shift register.
Fig. 8 is the electrical block diagram of another shift register provided in an embodiment of the present invention, as shown in figure 8, should
Shift register also includes N number of 3rd phase inverter；
The input of first the 3rd phase inverter and trigger D1 the first output endElectrical connection；
Second electrically connects with the output end of its previous 3rd phase inverter to the input of the phase inverter of n-th the 3rd；
The output end of the phase inverter of n-th the 3rd electrically connects with the first output end emit of shift register；
Wherein N is the integer more than or equal to 1.
As shown in figure 8, the 3rd phase inverter F3 number can equally be driven by the signal connection scan line of shift register output
The channel type of switching transistor in dynamic image element circuit determines.When the transistor in image element circuit be P-channel transistor,
3rd phase inverter F3 can include even number, and when the transistor that the transistor in image element circuit is N-channel, the 3rd phase inverter F3 can
With including odd number.3rd phase inverter F3 number can determine according to the type of the transistor in image element circuit, same to improve
The flexibility of shift register, add the use range of shift register.
It should be noted that the second phase inverter F2 and the 3rd phase inverter F3 structure can be with the first phase inverter F1 structure
It is identical.Concrete structure is as shown in fig. 6, here is omitted.
Fig. 9 is the electrical block diagram of another shift register provided in an embodiment of the present invention, as shown in figure 9, should
Shift register also includes M the second phase inverter F2 and N number of 3rd phase inverter F3.Second phase inverter F2's and the 3rd phase inverter F3
Number can determine according to the channel type of switching transistor in image element circuit.
It should be noted that when the transistor in the image element circuit on display panel uses same type of transistor, as
The scanning signal and LED control signal that plain circuit needs are opposite, therefore the first output end emit of shift register and the
Two output end Gout useful signal is opposite, for example, for the transistor in image element circuit using PMOS transistor come
Saying, the second output end Gout exports low level pulse signal, and the first output end emit exports the pulse signal of high level, or
For the transistor in image element circuit using for nmos pass transistor, the pulse of the second output end Gout output high level is believed
Number, the first output end emit exports low level pulse signal.Therefore, the second phase inverter F2 and the 3rd phase inverter F3 number one
As it is unequal, i.e. M and N are unequal.
Figure 10 is the electrical block diagram of another shift register provided in an embodiment of the present invention, as shown in Figure 10,
The shift register also includes reseting module R1, reset signal input RESET, the first level signal input VGH；
Reseting module R1 includes the 7th transistor T7 and the 8th transistor T8, the 7th transistor T7 the first pole and the first electricity
Flat signal input part VGH electrical connections, the second pole are electrically connected with the first nor gate Q1 first input end and grid is believed with resetting
Number input RESET electrical connection；
8th transistor T8 the first pole electrically connects with the first level signal input VGH, the second pole is with trigger D1's
First output endElectrical connection and grid electrically connect with reset signal input RESET.
As shown in Figure 10, when the 7th transistor T7 and the 8th transistor T8 are PMOS, reset signal input is passed through
RESET inputs low voltage signal to the 7th transistor T7 and the 8th transistor T8 grid turn it on, and the first level signal is defeated
Enter to hold the first output end emit and trigger D1 of VGH signal write-in shift register the second output end, namely M nodes.
Low level signal is needed when the transistor in shift register is resetted, the first level signal input VGH inputs low electricity
It is flat to be resetted, high level signal, the first level signal input are needed when the transistor in shift register is resetted
VGH input high levels are resetted.
It should be noted that when the 7th transistor T7 and the 8th transistor T8 are NMOS tube, reset signal input
RESET high input voltage signals, which turn it on, to be resetted.Figure 10 is only a kind of example, rather than to the 7th transistor T7 and
Eight transistor T8 type is defined.
The technical scheme of the present embodiment, by setting reseting module and reset signal input shift register in work
Work carries out homing action before starting, and so as to prevent shake of the shift register when opening, improves shift register
The stability of output signal.
Figure 11 is a kind of structural representation of display panel provided in an embodiment of the present invention, as shown in figure 11, the display surface
Plate includes the shift register that multiple any of the above-described embodiments provide, and individual shift register is cascaded, rear stage shift register
The first signal input part STV electrically connected with the trigger D1 of its upper level shift register the second output end (i.e. M nodes).
As shown in figure 11, the display panel include n shift register VSR1, VSR2, VSRn, after
First signal input part STV of the one-level shift register and trigger D1 of its upper level shift register the second output end electricity
Connection, namely the electrical connection of M nodes.For example, second level shift register VSR2 the first signal input part STV shifts with the first order
Register VSR1 trigger D1 the second output end electrical connection, i.e., the M nodes in shift register.Third level shift register
VSR3 the first signal input part STV is connected with second level shift register VSR2 M nodes.
N shift register of cascade, when the trigger D1 of upper level shift register the second output end (i.e. M points) is defeated
When going out significant level, the first signal input part STV input significant levels of the shift register of rear stage.Therefore, rear stage is worked as
Shift register secondary signal input CK input significant level when, the trigger D1 of the shift register of rear stage has
Reset and set function.
The technical scheme of the present embodiment, including the shift register that any embodiment provides, therefore possess any embodiment
The beneficial effect of the shift register of offer.
On the basis of above-described embodiment, as shown in figure 11, the display panel also includes multi-strip scanning line and a plurality of luminous
Control signal wire；
First output end emit of multiple shift registers is corresponded with a plurality of LED control signal line 101 and electrically connected；
Second output end Gout of multiple shift registers is corresponded with multi-strip scanning line 102 and electrically connected.
Second output end Gout of multiple shift registers exports the scan line 102 that scanning signal electrically connects to it step by step,
Scanning signal 102 in scan line drives the image element circuit in pixel line by line.First output end emit of multiple shift registers
The LED control signal line 101 that output LED control signal electrically connects to it step by step, LED control signal line 101 drive picture line by line
Image element circuit in element.
Specifically, the second output end Gout of multiple shift registers is corresponded with multi-strip scanning line 102 and electrically connected, and is used
In the conduction and cut-off for controlling the transistor being connected in display panel in image element circuit with scan line 102, multiple shift registers
First output end emit is corresponded with a plurality of LED control signal line 101 and electrically connected, for controlling pixel electricity in display panel
The conduction and cut-off for the transistor that Lu Zhongyu LED control signals line 101 connects.
On the basis of above-described embodiment, with continued reference to Figure 11, the display panel also include the first clock cable CLK1,
Second clock signal wire CLK2 and line trigger signal CP；
First order shift register VSR1 first input end STV electrically connects with line trigger signal CP；
Second input CK of odd level shift register electrically connects with the first clock cable CLK1, the 3rd input
CKB electrically connects with second clock signal wire CLK2；
3rd input CKB of even number Ghandler motion bit register electrically connects with the first clock cable CLK1, the second input
CK electrically connects with second clock signal wire CLK2.
Figure 12 is another driver' s timing figure provided in an embodiment of the present invention.Wherein, CK1 represents the first clock cable
The first clock signal on CLK1, CK2 represent the second clock signal on second clock signal wire CLK2, the first clock signal
CK1 and second clock signal CK2 includes periodically alternate first level signal and second electrical level signal.Such as Figure 11 and Figure 12
It is shown, CK timing diagram in the timing diagram such as Figure 12 of the first clock signal on the first clock cable CLK1, second clock letter
The timing diagram of CKB in the timing diagram such as Figure 12 of second clock signal on number line CLK2, STV1 are on line trigger signal CP
Signal.First clock signal and the sequential of the second clock signal on second clock signal wire CLK2 are opposite.As shown in Figure 12,
Second electrical level on the duration covering second clock signal wire CLK2 of the first level signal on one clock cable CLK1
The duration of signal；The duration of the first level signal on second clock signal wire CLK2 covers the first clock cable
The duration of second electrical level signal on CLK1.Wherein, the first level signal is high level signal, and second electrical level signal is low
Level signal, or the first level signal are low level signal, and second electrical level signal is high level signal.
With continued reference to Figure 11 and Figure 12, wherein, E1, E2, E3 and E4 represent the of first order shift register VSR1 respectively
Signal, the third level shift LD of the first output end output of the signal, second level shift register VSR2 of the output of one output end
The signal of the first output end output of the signal and fourth stage shift register VSR4 of device VSR3 the first output end output.G1、
G2, G3 and G4 represent signal, the second level shift register of first order shift register VSR1 the second output end output respectively
The signal and the fourth stage of the second output end output of the signal, third level shift register VSR3 of VSR2 the second output end output
The signal of shift register VSR4 the second output end output.M1, M2, M3 and M4 represent first order shift register VSR1 respectively
The signals of M nodes, the second level shift register VSR2 signal of M nodes, third level shift register VSR3 M nodes
The signal of signal and the fourth stage shift register VSR4 M nodes.By taking first and second grade of shift register (VSR1 and VRS2) as an example
Illustrate the course of work.Signal on the K1 moment, line trigger signal CP is low level, signal on the first clock cable CLK1
Trailing edge arrives.First order shift register VSR1 the second input CK is become by high level turns to low level, first order displacement
The signal of the second output end Q outputs of trigger D1 in register VSR1 and first order shift register VSR1 the first input
Hold STV signal (STV1) identical, be the signal of low level, now first order shift register VSR1 the 3rd input CKB
For high level, therefore the 3rd of the low level of trigger D1 the second output end Q outputs and first order shift register VSR1 is defeated
The high level for entering to hold CKB to export is inputted to the first nor gate Q1 two inputs, and the first nor gate Q1 exports low level to the
One-level shift register VSR1 the second output end Gout, while the low level of M nodes output is transmitted to second level shift LD
Device VSR2 the first signal input part STV.First order trigger D1 the first output endHigh level to the first order is exported to shift
Register VSR1 the first output end emit.First order shift register VSR1 the first output end emit output high level.
T1 the and t2 stages at K1 moment to K3 moment, the first output end and the second output end of first order shift register are defeated
It is identical in the K1 stages with it to go out signal.In the t1 stages, first order shift register VSR1 the second output end Gout exports low electricity
It is flat, in the t2 stages, due to the 3rd signal input part input low level of the first shift register, first order shift register VSR1
The second output end Gout output high level.In the t1 stages, the secondary signal input CK inputs of second level shift register are
High level, the output of the first output end and the output of the second output end of the trigger of second level shift register keep constant, and it is touched
Send out the output end of device first output low level, the second output end output high level；First output end of second level shift register is defeated
Go out low level, the second output end output low level.
At the K3 moment, the trailing edge of signal arrives on first order shift register VSR1 the first clock cable CLK1.The
One-level shift register VSR1 the second input CK is become by high level turns to low level, and the first signal input part STV is high electricity
It is flat, the trigger D1 of first order shift register the first output end output low level, the second output end output high level.
In stage after the K3 moment, first order shift register VSR1 the first signal input part STV is high level always,
First output end of first order shift register and the output of the second output end keep constant, identical with the K3 stages.
For second level shift register VSR2, at the K2 moment, the trailing edge of signal arrives on the first clock cable CLK1.
Second level shift register VSR2 the second input CK is become by high level turns to low level, in the shift register VSR2 of the second level
Trigger D1 the second output end Q outputs signal and second level shift register VSR2 first input end STV signal
(M1) it is identical, it is low level, now second level shift register VSR2 the 3rd input CKB signal is high level, therefore
What the trigger D1 low level of the second output end Q outputs exported with second level shift register VSR2 the 3rd input CKB
High level is inputted to the first nor gate Q1 two inputs, and the first nor gate Q1 exports low level to second level shift register
VSR2 the second output end Gout, while the low level of M nodes output is transmitted to third level shift register VSR3 the first letter
Number input STV.Second level shift register VSR2 trigger D1 the first output endHigh level to the second level is exported to move
Bit register VSR2 the first output end emit.Second level shift register VSR1 the first output end emit output high level.
T2 and t3 stages, second level shift register VSR2 repeat the work in first order shift register VSR1 t1 stages and t2 stages
Process.
In this way, the first output end of first order shift register and the first output end of second level shift register are defeated successively
Go out LED control signal, the first output end of first order shift register and the first output end of second level shift register are successively
Export scanning drive signal.By that analogy, the first output end of n levels shift register is sequentially output LED control signal, and second
Output end is sequentially output scanning drive signal, and here is omitted.
Figure 13 is a kind of structural representation of display device provided in an embodiment of the present invention, and the display device 110 includes upper
The display panel of any embodiment offer is provided.As shown in figure 13, the display device 110 includes display panel 111.The display device
The beneficial effect of the display panel of any embodiment offer is provided.
The embodiment of the present invention additionally provides a kind of driving method for the display panel for driving above-described embodiment to provide, above-mentioned
On the basis of embodiment, the driving method includes：
The first clock signal is provided to the first clock cable, second clock signal is provided to second clock signal wire.
Wherein, the first clock signal and second clock signal include periodically alternate first level signal and the second electricity
Ordinary mail number.
Second electrical level letter in the duration covering second clock signal of the first level signal in first clock signal
Number duration.
The duration of the first level signal in second clock signal covers the second electrical level letter in the first clock signal
Number duration.
Pay attention to, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other more equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (14)
1. a kind of shift register, it is characterised in that defeated including the first signal input part, secondary signal input and the 3rd signal
Enter end, the first output end, the second output end, trigger and the first nor gate；
The trigger signal input of the trigger electrically connects with first signal input part, the set input of the trigger
End electrically connects with the secondary signal input；The trigger includes at least one nor gate, and the first of the trigger is defeated
Go out end to be used to provide the first pulse signal to the first output end of the shift register；
The first input end of first nor gate electrically connects with the second output end of the trigger, first nor gate
Second input electrically connects with the 3rd signal input part, and first nor gate is used for the second of the shift register
Output end provides the second pulse signal.
2. shift register according to claim 1, it is characterised in that the trigger is d type flip flop.
3. shift register according to claim 2, it is characterised in that the trigger includes the first phase inverter, second
Nor gate, the 3rd nor gate, four nor gate and the 5th nor gate；
The input of first phase inverter electrically connects with first signal input part, first inverter output and institute
State the first input end electrical connection of the second nor gate；
Second input of second nor gate electrically connects with the secondary signal input, the output of second nor gate
End electrically connects with the first input end of the four nor gate；
The first input end of 3rd nor gate electrically connects with first signal input part, and the second of the 3rd nor gate
Input electrically connects with the secondary signal input, the output end of the 3rd nor gate and the first of the 5th nor gate
Input electrically connects；
Second input of the four nor gate electrically connects with the output end of the 5th nor gate, the four nor gate
Output end electrically connects with the first output end of the shift register；
Second input of the 5th nor gate electrically connects with the output end of the four nor gate, the 5th nor gate
Output end electrically connects with the first input end of first nor gate.
4. shift register according to claim 3, it is characterised in that the shift register, which also includes the first level, to be believed
Number input and second electrical level signal input part；First nor gate, second nor gate, the 3rd nor gate, institute
State at least one including the first transistor, second transistor, third transistor in four nor gate and the 5th nor gate
With the 4th transistor；
First pole of the first transistor electrically connects with the first level signal input, the second pole and second crystal
The first pole electrical connection of pipe, grid electrically connect with the first input end of the nor gate；
Second pole of the second transistor electrically connects with the output end of the nor gate, the second input of grid and the nor gate
Electrical connection；
First pole of the third transistor electrically connects with second electrical level signal input part, the second pole and the second transistor
The electrical connection of second pole, grid electrically connect with the grid of the second transistor；
First pole of the 4th transistor electrically connects with the second electrical level signal input part, the second pole and the 3rd crystal
The second pole electrical connection of pipe, grid electrically connect with the grid of the first transistor；
The first transistor is identical with the conducting channel of the second transistor, the third transistor and the 4th crystal
The conducting channel of pipe is identical, and the first transistor is different with the conducting channel of the third transistor.
5. shift register according to claim 1, it is characterised in that first phase inverter include the 5th transistor and
6th transistor；
First pole of the 5th transistor electrically connects with the first level signal input, the second pole and first phase inverter
Output end electrically connects and the electrical connection of the input of grid and first phase inverter；
First pole of the 6th transistor electrically connects with second electrical level signal input part, the second pole and the 5th transistor
Second pole electrically connects and grid electrically connects with the grid of the 5th transistor.
5th transistor is different with the conducting channel of the 6th transistor.
6. shift register according to claim 1, it is characterised in that also including M the second phase inverters；
The input of first the second phase inverter electrically connects with the output end of first nor gate；
Second electrically connects with the output end of its previous second phase inverter to the input of the phase inverter of m-th second；
The output end of the phase inverter of m-th second electrically connects with the second output end of the shift register；
Wherein M is the integer more than or equal to 1.
7. shift register according to claim 1, it is characterised in that also including N number of 3rd phase inverter；
The input of first the 3rd phase inverter electrically connects with the first output end of the trigger；
Second electrically connects with the output end of its previous 3rd phase inverter to the input of the phase inverter of n-th the 3rd；
The output end of the phase inverter of n-th the 3rd electrically connects with the first output end of the shift register；
Wherein N is the integer more than or equal to 1.
8. shift register according to claim 1, it is characterised in that also including reseting module, reset signal input,
First level signal input；
The reseting module includes the 7th transistor and the 8th transistor, the first pole of the 7th transistor and the described first electricity
The electrical connection of flat signal input part, the second pole electrically connected with the first input end of first nor gate and grid with it is described multiple
Position signal input part electrical connection；
First pole of the 8th transistor electrically connects with the first level signal input, the second pole and the trigger
First output end electrically connects and grid electrically connects with the reset signal input.
9. shift register according to claim 8, it is characterised in that the 7th transistor and the 8th transistor
For P-type transistor, the first level signal input is used to receive high level signal.
10. a kind of display panel, it is characterised in that including the shift register described in multiple any one of claim 1-9；Its
In, multiple shift registers cascade, described in the first signal input part and its upper level of shift register described in rear stage
The second output end electrical connection of the trigger of shift register.
11. display panel according to claim 10, it is characterised in that also including multi-strip scanning line and a plurality of light emitting control
Signal wire；
First output end of multiple shift registers is corresponded with a plurality of LED control signal line and electrically connected；
Second output end of multiple shift registers is corresponded with a plurality of scan line and electrically connected.
12. the display panel according to claim 11, it is characterised in that also believe including the first clock cable, second clock
Number line and line trigger signal；
The first input end of shift register described in the first order electrically connects with the line trigger signal；
Second input of shift register described in odd level electrically connects with first clock cable, the 3rd input and institute
State the electrical connection of second clock signal wire；
3rd input of the extremely described shift register of even number electrically connects with first clock cable, the second input and institute
State the electrical connection of second clock signal wire.
13. a kind of display device, it is characterised in that including the display panel described in claim any one of 10-12.
A kind of 14. method for driving display panel as claimed in claim 12, it is characterised in that
The first clock signal is provided to first clock cable, second clock letter is provided to the second clock signal wire
Number；
Wherein, first clock signal and the second clock signal include periodically alternate first level signal and the
Two level signals；
The duration of the first level signal in first clock signal covers the second electricity in the second clock signal
The duration of ordinary mail number；
The duration of the first level signal in the second clock signal covers the second electricity in first clock signal
The duration of ordinary mail number.
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