CN113299223B - Display panel and display device - Google Patents
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- CN113299223B CN113299223B CN202110732575.2A CN202110732575A CN113299223B CN 113299223 B CN113299223 B CN 113299223B CN 202110732575 A CN202110732575 A CN 202110732575A CN 113299223 B CN113299223 B CN 113299223B
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- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 26
- 230000009471 action Effects 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 101001077374 Oryza sativa subsp. japonica UMP-CMP kinase 3 Proteins 0.000 description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention provides a display panel and a display device. The display panel includes: the driving circuit comprises a plurality of shift registers in cascade connection; the shift register comprises a control module, a first output module and a second output module; the control module is used for controlling voltage signals of the control end of the first output module and the control end of the second output module; the first output module is used for outputting a first scanning signal under the control of a voltage signal of a control end of the first output module, wherein the first scanning signal is a scanning signal with low level and effectiveness; the second output module is used for outputting a second scanning signal under the control of the voltage signal of the control end of the second output module, and the second scanning signal is a scanning signal with high level and effectiveness. The driving circuit in the embodiment of the invention can simultaneously provide the enabling signals for the n-type transistor and the p-type transistor in the pixel circuit, can reduce the number of the driving circuit, reduces the number of transistors in a non-display area, and is beneficial to narrowing the frame of the display panel.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
In semiconductor technology, transistor types include a p-type transistor and an n-type transistor, and enable signals of the p-type transistor and the n-type transistor are different. In some pixel circuits, including both p-type transistors and n-type transistors, driving circuits are required to be respectively provided for the p-type transistors and the n-type transistors to provide corresponding enabling signals, so that the number of driving circuits is increased, and the narrowing of the frame of the display panel is seriously affected.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for solving the problem of narrowing of a frame of the display panel.
An embodiment of the present invention provides a display panel including: the driving circuit comprises a plurality of shift registers in cascade connection;
the shift register comprises a control module, a first output module and a second output module;
the control module is used for controlling voltage signals of the control end of the first output module and the control end of the second output module;
the first output module is used for outputting a first scanning signal under the control of a voltage signal of a control end of the first output module, wherein the first scanning signal is a scanning signal with low level and effectiveness;
the second output module is used for outputting a second scanning signal under the control of the voltage signal of the control end of the second output module, and the second scanning signal is a scanning signal with high level and effectiveness.
The embodiment of the invention provides a display device, which comprises the display panel provided by any embodiment of the invention.
The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: the cascade shift register of the driving circuit comprises two output modules, wherein the first output module can output a first scanning signal for controlling the switching state of the p-type transistor under the control of the control module, and the second output module can output a second scanning signal for controlling the switching state of the n-type transistor under the control of the control module. The driving circuit can simultaneously provide enable signals for the n-type transistors and the p-type transistors in the pixel circuit, so that the number of the driving circuit can be reduced, the number of transistors in a non-display area can be reduced, and the frame of the display panel can be narrowed.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the invention;
FIG. 2 is a timing diagram of the pixel circuit of FIG. 1;
FIG. 3 is a schematic diagram of a driving circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the operation of the shift register;
FIG. 6 is a schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 9 is another timing diagram of shift register operation;
FIG. 10 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a driving circuit according to an embodiment of the invention;
fig. 12 is a schematic diagram of a display device according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The embodiment of the invention provides a display panel, which comprises a plurality of light emitting devices and a plurality of pixel circuits, wherein the pixel circuits are electrically connected with the light emitting devices and used for driving the light emitting devices to emit light. The light emitting device includes a first electrode, a light emitting layer, and a second electrode stacked in this order. In one embodiment, the light emitting device is an organic diode light emitting device; in another embodiment, the light emitting device is an inorganic diode light emitting device.
Fig. 1 is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the invention, and fig. 2 is a timing diagram of the pixel circuit in fig. 1. As shown in fig. 1, the pixel circuit is a 7T1C circuit, and the seven transistors are respectively: the driving transistor Tm, the data writing transistor T1, the threshold compensating transistor T2, the first reset transistor T3, the second reset transistor T4, the first light emission control transistor T5, and the second light emission control transistor T6. The first reset transistor T3 is configured to reset the N1 node, that is, reset the control terminal of the driving transistor Tm; the second reset transistor T4 is used to reset the first electrode of the light emitting device 10. Also illustrated in fig. 1 are a power signal terminal P, a data signal terminal D, a reset signal terminal Ref, a first control terminal S1-n, a second control terminal S2-P, a third control terminal S2-n, and a light emission control terminal E.
The threshold compensation transistor T2 and the first reset transistor T3 are n-type transistors, and the other transistors are p-type transistors. Optionally, the materials for fabricating the active layers of the threshold compensation transistor T2 and the first reset transistor T3 include metal oxides, and the materials for fabricating the active layers of the other transistors include silicon. In this embodiment, the leakage current of the threshold compensation transistor T2 and the first reset transistor T3 to the N1 node can be reduced, the potential stability of the N1 node in the light-emitting stage is ensured, the problem of flicker display under low-frequency driving is improved, and the display effect is improved.
In another pixel circuit, one of the threshold compensation transistor T2 and the first reset transistor T3 is an n-type transistor, which is not illustrated in the drawings.
As shown in the timing diagram of fig. 2, in the working period of the pixel circuit, control signals need to be provided to the four control terminals of the pixel circuit, respectively. The signals of the first control terminal S1-n and the third control terminal S2-n may be provided by two adjacent shift registers of the same driving circuit. The conventional arrangement requires three sets of driving circuits in the display panel, which are disposed in the non-display area of the display panel, resulting in an increase in the frame of the display panel.
Based on the above, the embodiment of the invention provides a driving circuit, which can simultaneously provide the enabling signal of an n-type transistor and the enabling signal of a p-type transistor during operation, meets the driving requirement of a pixel circuit, can reduce the number of the driving circuit, reduces the number of transistors in a non-display area, and is beneficial to narrowing the frame of a display panel.
Fig. 3 is a schematic diagram of a driving circuit according to an embodiment of the present invention, and as shown in fig. 3, the driving circuit includes a plurality of shift registers 20 in cascade connection. The shift register 20 includes a first output module 21, a second output module 22, and a control module 23. In fig. 3, an mth stage shift register 20 (m) and an mth-1 stage shift register 20 (m-1) are schematically shown, m being an integer not less than 2.
The control module 23 is configured to control voltage signals of the control terminal of the first output module 21 and the control terminal of the second output module 22.
The first output module 21 is configured to output a first scan signal under control of a voltage signal at a control terminal thereof, where the first scan signal is a scan signal with a low level and valid; the active low scan signal controls the transistor connected to the output terminal of the first output module 21 to be turned on when the first scan signal is a low signal, that is, the low signal is an enable signal of the transistor connected to the output terminal of the first output module 21. The first scan signal output from the first output module 21 can control the switching state of the p-type transistor.
The second output module 22 is configured to output a second scan signal under control of the voltage signal at the control terminal thereof, where the second scan signal is an active high scan signal. The active high scan signal is a high signal that controls the transistor connected to the second output module 22 to be turned on, i.e., the high signal is an enable signal of the transistor connected to the output terminal of the second output module 22. The second scan signal output by the second output module 22 can control the switching state of the n-type transistor.
Also illustrated in fig. 3 is a pixel circuit connected to the shift register.
For the pixel circuit driven by the mth stage shift register 20 (m), the output terminal of the first output module 21 is electrically connected to the second control terminal S2-p, and when the pixel circuit is driven, the first output module 21 provides the first scan signal to the second control terminal S2-p. The output terminal of the second output module 22 is electrically connected to the third control terminal S2-n, and the second output module 22 provides the second scan signal to the third control terminal S2-n when the driving pixel circuit is operated. The first control terminal S1-n in the pixel circuit is electrically connected to the output terminal of the second output module 22 of the m-1 st stage shift register 20 (m-1), and the second output module 22 provides the second scan signal to the first control terminal S1-n.
Referring to the timing diagram illustrated in fig. 2, the duty cycle of the pixel circuit includes: a reset phase t1, a data writing phase t2, and a light emitting phase t3.
In the reset phase t1: the second output module 22 of the m-1 stage shift register 20 (m-1) provides the second scan signal to the first control terminal S1-n, and the high level second scan signal can control the first reset transistor T3 to be turned on, and provide the signal of the reset signal terminal Ref to the control terminal of the driving transistor Tm to reset the control terminal of the driving transistor Tm.
In the data writing phase t2: the second output module 22 of the mth stage shift register 20 (m) provides the second scan signal to the third control terminal S2-n, and the high level second scan signal at this stage can control the second reset transistor T4 to be turned on, and provide the signal of the reset signal terminal Ref to the first electrode of the light emitting device 10 to reset the first electrode; the first output module 21 of the mth stage shift register 20 (m) provides the first scan signal to the second control terminal S2-p, and the low level first scan signal can control the data writing transistor T1 and the threshold compensating transistor T2 to be turned on, write the data voltage to the control terminal of the driving transistor Tm, and compensate the threshold voltage of the driving transistor Tm.
In the light-emitting phase t3: the light emission control terminal E provides an active level signal to control the first light emission control transistor T5 and the second light emission control transistor T6 to be turned on, and the driving transistor Tm provides a driving current to the light emitting device 10 to control the light emitting device 10 to emit light. The display panel provided by the embodiment of the invention further comprises a group of light-emitting driving circuits, and the light-emitting control end E is electrically connected with the light-emitting driving circuits.
In the display panel provided by the embodiment of the invention, the cascade shift register of the driving circuit comprises two output modules, the first output module can output a first scanning signal for controlling the switching state of the p-type transistor under the control of the control module, and the second output module can output a second scanning signal for controlling the switching state of the n-type transistor under the control of the control module. The driving circuit can simultaneously provide enable signals for the n-type transistors and the p-type transistors in the pixel circuit, so that the number of the driving circuit can be reduced, the number of transistors in a non-display area can be reduced, and the frame of the display panel can be narrowed.
Fig. 4 is a schematic diagram of a shift register according to an embodiment of the present invention, and as shown in fig. 4, the shift register 20 includes a first node N1 and a second node N2; the first node N1 and the second node N2 are electrically connected to the control module 23, respectively.
The first output module 21 includes a first output pull-down module 211, and a control end of the first output pull-down module 211 is electrically connected to the second node N2; the first output pull-down module 211 is configured to provide the low level signal of the first clock signal terminal CK1 to the output terminal OUT1 of the first output module 21 under the control of the voltage of the second node N2. That is, the first output pull-down module 211 is for controlling the output terminal OUT1 of the first output module 21 to output the low level signal of the first scan signal.
The second output module 22 includes a second output pull-up module 221, and a control end of the second output pull-up module 221 is respectively and electrically connected with the first node N1 and the second node N2; the second output pull-up module 221 is configured to provide the high level signal of the second clock signal terminal CK2 to the output terminal OUT2 of the second output module 22 under the control of the first node N1 voltage and the second node N2 voltage. That is, the second output pull-up module 221 is for controlling the output terminal OUT2 of the second output module 22 to output the high level signal of the second scan signal.
FIG. 5 is a timing diagram illustrating the operation of the shift register. As shown in fig. 5, the duty ratio of the clock signal provided from the second clock signal terminal CK2 is smaller than the duty ratio of the clock signal provided from the first clock signal terminal CK 1. The duty ratio is the ratio of the width of the high level to the period in one period. The arrangement can enable the low-level signal output by the first output module 21 to be an enabling signal of a p-type transistor, and the high-level signal output by the second output module 22 to be an enabling signal of an n-type transistor, so that the driving requirement of the pixel circuit can be met.
As shown in fig. 4, the first output module 21 further includes a first output pull-up module 212, and a control of the first output pull-up module 212 is electrically connected to the first node N1; the first output pull-up module 212 is configured to provide a signal of the first constant voltage terminal V1 to the output terminal OUT1 of the first output module 21 under the control of the voltage of the first node N1. Wherein the first constant voltage terminal V1 provides a high level constant signal.
The first output pull-up module 212 is configured to cooperate with the first output pull-down module 211, and after the first output pull-down module 211 controls the output terminal OUT1 of the first output module 21 to output a low-level signal of the first scanning signal, the first output pull-up module 212 controls the output terminal OUT1 to output a high-level signal of the first scanning signal, and the high-level signal of the first scanning signal controls the p-type transistor to be turned off, so as to ensure that the first scanning signal can meet the driving requirement of the pixel circuit.
With continued reference to fig. 4, the first output pull-down module 211 includes a first transistor M1, a control terminal of the first transistor M1 is electrically connected to the second node N2, a first terminal of the first transistor M1 is electrically connected to the first clock signal terminal CK1, and a second terminal of the first transistor M1 is electrically connected to the output terminal OUT1 of the first output module 21; when the second node N2 is at a low level, the first transistor M1 is turned on, and the signal of the first clock signal terminal CK1 is provided to the output terminal OUT1 of the first output module 21, and when the second node N2 is at a low level and the signal of the first clock signal terminal CK1 is at a low level, the output terminal OUT1 of the first output module 21 outputs the low level signal of the first scan signal.
The first output pull-up module 212 includes a second transistor M2, a control terminal of the second transistor M2 is electrically connected to the first node N1, a first terminal of the second transistor M2 is electrically connected to the first constant voltage terminal V1, and a second terminal of the second transistor M2 is electrically connected to the output terminal of the first output module 21. When the first node N1 is at a low potential, the second transistor M2 is turned on, and the signal of the first constant voltage terminal V1 is provided to the output terminal OUT1 of the first output module 21, and the output terminal OUT1 of the first output module 21 outputs a high level signal of the first scan signal.
As shown in fig. 4, the second output pull-up module 221 includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The control terminal of the third transistor M3 is electrically connected to the second node N2, the first terminal of the third transistor M3 is electrically connected to the second clock signal terminal CK2, and the second terminal of the third transistor M3 is electrically connected to the first terminal of the fourth transistor M4. The control terminal of the fourth transistor M4 is electrically connected to the first node N1, and the second terminal of the fourth transistor M4 is electrically connected to the output terminal OUT2 of the second output module 22. The control terminal of the fifth transistor M5 is electrically connected to the second node N2, the first terminal of the fifth transistor M5 is electrically connected to the second clock signal terminal CK2, and the second terminal of the fifth transistor M5 is electrically connected to the output terminal OUT2 of the second output module 22.
When the first node N1 is at a low potential, the fourth transistor M4 is turned on; when the second node N2 is at a low potential, the third transistor M3 and the fifth transistor M5 are turned on. When the first node N1 and the second node N2 are both at low potential, the third transistor M3 and the fourth transistor M4 are both turned on, and the high level signal of the second clock signal terminal CK2 can be provided to the output terminal OUT2 of the second output module 22, so that the output terminal OUT2 of the second output module 22 outputs the high level signal of the second scan signal. Meanwhile, when the second node N2 is at a low potential and the second clock signal terminal CK2 is a high level signal, the fifth transistor M5 is turned on, and can also supply the high level signal to the output terminal OUT2 of the second output module 22.
In another embodiment, fig. 6 is a schematic diagram of a shift register according to an embodiment of the present invention, as shown in fig. 6, the second output module 22 further includes a third node N3 and a second output pull-down module 222, and a control end of the second output pull-down module 222 is electrically connected to the third node N3; the second output pull-down module 222 is configured to provide the signal of the second constant voltage terminal V2 to the output terminal OUT2 of the second output module 22 under the control of the voltage of the third node N3. Wherein the second constant voltage terminal V2 provides a low level constant signal. The constant voltage signal provided by the second constant voltage terminal V2 is smaller than the constant voltage signal provided by the first constant voltage terminal V1.
The second output pull-down module 222 is configured to cooperate with the second output pull-up module 221, and after the second output pull-up module 221 controls the output terminal OUT2 of the second output module 22 to output the high level signal of the second scanning signal, the second output pull-down module 222 controls the output terminal OUT2 to output the low level signal of the second scanning signal, and the low level signal of the second scanning signal controls the n-type transistor to be turned off, so as to ensure that the second scanning signal can meet the driving requirement of the pixel circuit.
As shown in fig. 6, the second output pull-down module 222 includes an eighth transistor M8, a control terminal of the eighth transistor M8 is electrically connected to the third node N3, a first terminal of the eighth transistor M8 is electrically connected to the second constant voltage terminal V2, and a second terminal of the eighth transistor M8 is electrically connected to the output terminal OUT2 of the second output module 22. When the third node N3 is at a low potential, the eighth transistor M8 is controlled to be turned on, and a low level signal of the second constant voltage terminal V2 is provided to the output terminal OUT2 of the second output module 22, so that the output terminal OUT2 of the second output module 22 outputs a low level signal of the second scan signal.
As shown in fig. 6, the second output module 22 further includes an auxiliary pull-down module 223, the auxiliary pull-down module 223 is electrically connected to the third node N3, and the auxiliary pull-down module 223 is configured to stabilize the potential of the third node N3 under the control of the signal of the second clock signal terminal CK2 and the signal of the first clock signal terminal CK 1.
In the embodiment of the present invention, the second scan signal output by the output terminal OUT2 of the second output module 22 can be used to drive the pixel circuit to work, where the high level signal in the second scan signal is an active level signal. In order to ensure that the driving pixel circuit operates normally, it is necessary to maintain the low level signal for a longer period of time after the high level signal is supplied once by the second scanning signal, where the longer period of time is compared with the duration of the high level signal in the second scanning signal. By setting the auxiliary pull-down module 223 to stabilize the potential of the third node N3, the second output pull-down module 222 can be ensured to continuously provide the low level signal to the output terminal OUT2 of the second output module 22 under the control of the third node N3 at the time when the second scan signal is required to be the low level signal.
Specifically, the auxiliary pull-down module 223 includes a sixth transistor M6, a seventh transistor M7, and a first capacitor C1; the control terminal of the sixth transistor M6 is electrically connected to the second clock signal terminal CK2, the first terminal of the sixth transistor M6 is electrically connected to the second constant voltage terminal V2, and the second terminal of the sixth transistor M6 is electrically connected to the third node N3; the control terminal of the seventh transistor M7 is electrically connected to the first clock signal terminal CK1, the first terminal of the seventh transistor M7 is electrically connected to the second constant voltage terminal V2, and the second terminal of the seventh transistor M7 is electrically connected to the third node N3; the first electrode plate of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and the second electrode plate of the first capacitor C1 is electrically connected to the third node N3.
As understood by referring to the timing chart illustrated in fig. 5, as described in the above embodiment, at the time when the second clock signal terminal CK2 is at the high level (time t3 in fig. 5), the second output pull-up module 221 supplies the high level signal of the second clock signal terminal CK2 to the output terminal OUT2 of the second output module 22 under the control of the voltage of the first node N1 and the voltage of the second node N2, and at this time, the output terminal OUT2 of the second output module 22 outputs the high level signal, which is the enable signal for driving the N-type transistor in the pixel circuit. That is, in the period of the shift register operation, the output terminal OUT2 of the second output module 22 needs to be controlled to output the low level signal at a time other than the time t3 to meet the driving requirement of the second scan signal on the pixel circuit.
At time t4, the second clock signal terminal CK2 is a low level signal, the first clock signal terminal CK1 is a high level signal, at this time, the sixth transistor M6 is turned on, the seventh transistor M7 is turned off, and the sixth transistor M6 provides the low level signal of the second constant voltage terminal V2 to the third node N3 after being turned on, so that the low level signal of the second constant voltage terminal V2 is provided to the output terminal OUT2 of the second output module 22 through the second output pull-down module 222 under the control of the third node N3, so that the output terminal OUT2 of the second output module 22 outputs the low level signal of the second scan signal.
At time t5, the second clock signal terminal CK2 is a low level signal, the first clock signal terminal CK1 is a low level signal, and both the sixth transistor M6 and the seventh transistor M7 are turned on to provide the low level signal of the second constant voltage terminal V2 to the third node N3 to stabilize the potential of the third node N3.
At time t6, the second clock signal terminal CK2 and the first clock signal terminal CK1 are both high signals, and the sixth transistor M6 and the seventh transistor M7 are both turned off, and the third node N3 can maintain a low potential to control the second output pull-down module 222 to be turned on by virtue of the action of the first capacitor C1.
The second output module 22 outputs the high level signal of the second scan signal at time t3, and after outputting the high level signal, the second output module 22 outputs the low level signal of the second scan signal, and the output time of the low level signal is longer than the output time of the high level signal. The first output module 21 outputs the low level signal of the first scan signal at time t4, and after outputting the low level signal, the first output module 21 outputs the high level signal of the first scan signal, and the output time of the high level signal is longer than the output time of the low level signal. The second output module 22 still needs to maintain outputting the low level signal for a long time after t6, and the output of the low level signal of the first scan signal can be ensured by the auxiliary pull-down module 223.
Further, fig. 7 is a schematic diagram of another shift register according to an embodiment of the present invention, as shown in fig. 7, the second output module 22 further includes a first protection module 224, a control end of the first protection module 224 is electrically connected to the second node N2, a first end of the first protection module 224 is electrically connected to the second clock signal end CK2, and a second end of the first protection module 224 is electrically connected to the third node N3; the first protection module 224 is configured to control the second output pull-down module 224 to be turned off when the second output pull-up module 221 is turned on. The first protection module 224 can ensure that the output terminal OUT2 of the second output module 22 can normally output a high-level signal, so as to avoid the interference to the output of the high-level signal caused by the second output pull-down module 224 being turned on when the second output pull-up module 221 works.
As shown in fig. 7, the first protection module 224 includes a ninth transistor M9, a control terminal of the ninth transistor M9 is electrically connected to the second node N2, a first terminal of the ninth transistor M9 is electrically connected to the second clock signal terminal CK2, and a second terminal of the ninth transistor M9 is electrically connected to the third node N3. As can be seen from the above embodiments, when the first node N1 and the second node N2 are both at low potential, the third transistor M3 and the fourth transistor M4 are both turned on, the high-level signal of the second clock signal terminal CK2 can be provided to the output terminal OUT2 of the second output module 22, and at this time, the high-level signal of the second scan signal output by the output terminal OUT2 can be used as the enable signal of the N-type transistor in the pixel circuit. By setting the first protection module, when the second node N2 is at a low potential, the ninth transistor M9 can be controlled to be turned on, and then the high level signal of the second clock signal terminal CK2 is provided to the third node N3 through the ninth transistor M9, so as to control the eighth transistor M8 to be in a turned-off state, so that the signal of the second constant voltage terminal V2 is prevented from being provided to the output terminal OUT2 of the second output module 22, and interference is prevented from being caused to the signal of the output terminal OUT2 of the second output module 22.
In another embodiment, fig. 8 is a schematic diagram of another shift register according to an embodiment of the present invention, and as shown in fig. 8, the control module 23 includes a first node control module 231 and a second node control module 232. Wherein,,
the first node control module 231 is electrically connected with the input terminal IN of the shift register, the third clock signal terminal CK3, the second constant voltage terminal V2 and the second node N2; the first node control module 231 is configured to control the voltage of the first node N1 according to the signal of the input terminal IN of the shift register, the signal of the third clock signal terminal CK3, the signal of the second constant voltage terminal V2, and the signal of the second node N2; wherein, the period of the signal of the third clock signal terminal CK3 is the same as the period of the signal of the first clock signal terminal CK 1.
The second node control module 232 is electrically connected to the input terminal IN, the first clock signal terminal CK1, and the first constant voltage terminal V1 of the shift register; the second node control module 232 is configured to control the voltage of the second node N2 according to the signal at the input terminal IN of the shift register, the signal at the first clock signal terminal CK1, and the signal at the first constant voltage terminal V1.
The signal of the first clock signal terminal CK1, the signal of the third clock signal terminal CK3, the signal of the first constant voltage terminal V1, the signal of the second constant voltage terminal V2, and the signal of the input terminal IN of the shift register cooperate to control the potential of the first node N1 and the potential of the second node N2, so that the output terminal OUT1 of the first output module 21 can output a first scan signal while the output terminal OUT2 of the second output module 22 can output a second scan signal when the shift register works, wherein a low level signal IN the first scan signal can be used as an enable signal of a p-type transistor IN the pixel circuit, and a high level signal IN the second scan signal can be used as an enable signal of an N-type transistor IN the pixel circuit. The driving circuit can work together with the pixel circuit, simultaneously enable signals are respectively provided for the n-type transistor and the p-type transistor in the pixel circuit, the number of the driving circuits can be reduced, the number of transistors in a non-display area is reduced, and the narrowing of the frame of the display panel is facilitated.
As shown in fig. 8, the first node control module 231 includes a tenth transistor M10 and an eleventh transistor M11. The control terminal of the tenth transistor M10 is electrically connected to the third clock signal terminal CK3, the first terminal of the tenth transistor M10 is electrically connected to the second constant voltage terminal V2, and the second terminal of the tenth transistor M10 is electrically connected to the first node N1; the control terminal of the eleventh transistor M11 is electrically connected to the second node N2, the first terminal of the eleventh transistor M11 is electrically connected to the input terminal IN of the shift register, and the second terminal of the eleventh transistor M11 is electrically connected to the first node N1.
The second node control module 232 includes a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14; the control end of the twelfth transistor M12 is electrically connected with the third clock signal end, the first end of the twelfth transistor M12 is electrically connected with the input end IN of the shift register, and the second end of the twelfth transistor M12 is electrically connected with the second node N2; the control terminal of the thirteenth transistor M13 is electrically connected to the first clock signal terminal, the first terminal of the thirteenth transistor M13 is electrically connected to the second terminal of the fourteenth transistor M14, and the second terminal of the thirteenth transistor M13 is electrically connected to the second node N2; the control terminal of the fourteenth transistor M14 is electrically connected to the first node N1, and the first terminal of the fourteenth transistor M14 is electrically connected to the first constant voltage terminal V1.
As shown in fig. 8, the control module 23 further includes a fifteenth transistor M15, a second capacitor C2, and a third capacitor C3. The control terminal of the fifteenth transistor M15 is electrically connected to the second constant voltage terminal V2, the first terminal of the fifteenth transistor M15 is connected to the fourth node N4, and the second terminal of the fifteenth transistor M15 is connected to the second node N2. The fifteenth transistor M15 is normally-on, and can reduce the leakage current from the second node N2 to the fourth node N4 in the second node N2 potential maintaining stage. The second capacitor C2 is used for maintaining the potential of the second node N2, and the third capacitor C3 is used for maintaining the potential of the first node N1.
FIG. 9 is another timing diagram of shift register operation. The following describes the operation of the shift register according to the embodiment of the present invention with reference to the timing sequence in fig. 9. As shown in the figure 9 of the drawings,
at time t 1', the input terminal IN of the shift register inputs a start signal, the first clock signal terminal CK1 provides a high level signal, the second clock signal terminal CK2 provides a high level signal, and the third clock signal terminal CK3 provides a low level signal. The third clock signal terminal CK3 controls the tenth transistor M10 and the twelfth transistor M12 to be turned on; after the tenth transistor M10 is turned on, writing a low level signal of the second constant voltage terminal V2 to the first node N1; after the twelfth transistor M12 is turned on, the low level signal input from the input terminal IN is written into the fourth node N4, and the fifteenth transistor M15 is turned on, and the low level signal is written into the second node N2 from the fourth node N4 (this is the cause of the potential drop of the second node N2 at the 1 position); while the fourth node N4 controls the eleventh transistor M11 to turn on, writing a low level signal input from the input terminal IN to the first node N1. The first node N1 and the second node N2 are both low at this stage, that is, the control module 23 controls the first node N1 and the second node N2 to be both low at this stage.
When both the first node N1 and the second node N2 are low, for the first output module 21: the first output pull-down module 211 and the first output pull-up module 212 are both on. The second transistor M2 is turned on under the control of the first node N1, and a high level signal of the first constant voltage terminal V1 is supplied to the output terminal OUT1; the first transistor M1 is turned on under the control of the second node N1, and supplies the high level signal of the first clock signal terminal CK1 to the output terminal OUT1; the output terminal OUT1 of the first output module 21 outputs a high level signal of the first scan signal at this time.
When both the first node N1 and the second node N2 are low, for the second output module 22: the second output pull-up module 221 is turned on and the second output pull-down module 222 is turned off. The fourth transistor M4 is turned on under the control of the first node N1, and the third transistor M3 is turned on under the control of the second node N2, so that the high level signal of the second clock signal terminal CK2 is supplied to the output terminal OUT2 through the third transistor M3 and the fourth transistor M4; meanwhile, the second node N2 controls the fifth transistor M5 to be turned on, and supplies the high level signal of the second clock signal terminal CK2 to the output terminal OUT2; the output terminal OUT2 of the second output module 22 outputs the high level signal of the second scan signal at this time. The high level signal of the second scan signal is an enable signal for controlling the n-type transistor in the pixel circuit. In this stage, the second node N2 controls the ninth transistor M9 to be turned on, and the high-level signal of the second clock signal terminal CK2 is supplied to the third node N3, and the eighth transistor M8 can be controlled to be turned off when the third node N3 is at a high potential.
At time t 2', the third clock signal terminal CK1 changes from the low level signal to the high level signal, and both the tenth transistor M10 and the twelfth transistor M12 are turned off. The second clock signal terminal CK2 changes from a high level signal to a low level signal, and the signal transition of the second clock signal terminal CK2 has a coupling effect on the potential of the second node N2, so that the potential of the second node N2 is continuously pulled down, as shown in position 2 illustrated in fig. 9. Meanwhile, the signal transition of the second clock signal terminal CK2 has a coupling effect on the potential of the first node N1, so that the potential of the first node N1 is pulled down, as shown in position 3 illustrated in fig. 9. However, IN this stage, the fourth node N4 maintains the low level of the previous stage to control the eleventh transistor M11 to be turned on, and the high level signal of the input terminal IN is written into the first node N1, so that the potential of the first node N1 is pulled up again after being briefly pulled down. Therefore, at this stage, the first node N1 is at a high potential and the second node N2 is at a low potential. That is, the control module 23 controls the first node N1 to be high and the second node N2 to be low at this stage.
When the first node N1 is at a high potential and the second node N2 is at a low potential, the first output module 21: the first output pull-down module 211 is open and the first output pull-up module 212 is closed. The second transistor M2 is turned off; the first transistor M1 is turned on to supply the high level signal of the first clock signal terminal CK1 to the output terminal OUT1 of the first output module 21, and at this time, the output terminal OUT1 of the first output module 21 continues to output the high level signal of the first scan signal.
When the first node N1 is at a high potential and the second node N2 is at a low potential, the second output module 22: the second node N2 controls the fifth transistor M5 and the ninth transistor M9 to turn on, and the fifth transistor M5 supplies the low level signal of the second clock signal terminal CK2 to the output terminal OUT2; the ninth transistor M9 supplies the low level signal of the second clock signal terminal CK2 to the third node N3, and in addition, the second clock signal terminal CK2 is turned on to control the sixth transistor M6 to turn on, the low level signal of the second constant voltage terminal V2 is supplied to the third node N3, and at this stage, the third node N3 is low and maintains the low level by the action of the first capacitor C1 to control the eighth transistor M8 to turn on and the low level signal of the second constant voltage terminal V2 is supplied to the output terminal OUT2. At this time, the output terminal OUT2 of the second output module 22 outputs a low level signal of the second scan signal.
At time t 3', the first clock signal terminal CK1 changes from a high level signal to a low level signal, the first clock signal terminal CK1 has a coupling effect on the second node N2, and the potential of the second node N2 is continuously pulled down when the first clock signal terminal CK1 signal jumps, as shown in position 4 illustrated in fig. 9. At this time, the second node N2 is at a low level, and the first node N1 maintains a high level at the previous time.
At this stage, for the first output module 21: the first clock signal terminal CK1 is a low level signal, the first transistor M1 is turned on under the control of the potential of the second node N2, and the low level signal of the first clock signal terminal CK1 is supplied to the output terminal OUT1, at this time, the output terminal OUT1 of the first output module 21 outputs the low level signal of the first scan signal, which can be used as an enable signal of the p-type transistor in the pixel circuit.
At this stage, for the second output module 22: the low potential of the second node N2 controls the fifth transistor M5 and the ninth transistor M9 to be turned on, and the fifth transistor M5 supplies the low level signal of the second clock signal terminal CK2 to the output terminal OUT2; the ninth transistor M9 supplies the low level signal of the second clock signal terminal CK2 to the third node N3, and in addition, the first clock signal terminal CK1 is low to control the sixth transistor M6 to be turned on, the low level signal of the second constant voltage terminal V2 is supplied to the third node N3, and at this stage, the third node N3 is low to control the eighth transistor M8 to be turned on, and the low level signal of the second constant voltage terminal V2 is supplied to the output terminal OUT2. At this time, the output terminal OUT2 of the second output module 22 outputs a low level signal of the second scan signal.
At time t 4', the second node N2 is at a low potential, the first node N1 is at a high potential, the output terminal OUT1 of the first output module 21 outputs a high level signal of the first scan signal, and the output terminal OUT2 of the second output module 22 outputs a low level signal of the second scan signal. The switching state of each transistor in the shift register in this period is substantially the same as the time t 2', and will not be described here again.
At time t 5', the third clock signal terminal CK3 is a low level signal, the second clock signal terminal CK2 is a high level signal, and the first clock signal terminal CK1 is a high level signal. After the tenth transistor M10 is turned on under control of the signal of the third clock signal terminal CK3, the low-level signal of the second constant voltage terminal V2 is written into the first node N1, so that the first node N1 changes from high to low. After the twelfth transistor M12 is turned on under the control of the signal of the third clock signal terminal CK3, the high-level signal of the input terminal IN is written into the second node N2, and at this time, the second node N2 is changed from the low potential to the high potential. At this stage, the first node N1 is low and the second node N2 is high.
When the first node N1 is at a low potential and the second node N2 is at a high potential, the first output module 21: the first transistor M1 is turned off, the second transistor M2 is turned on under the control of the first node N1, a high level signal of the first constant voltage terminal V1 is supplied to the output terminal OUT1 of the first output module 21, and the output terminal OUT1 of the first output module 21 outputs a high level signal of the first scan signal.
When the first node N1 is at a low potential and the second node N2 is at a high potential, the second output module 22: the third transistor M3 is turned off, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off, and the second output pull-up module 221 is turned off; the ninth transistor M9 is also turned off. In this stage, the sixth transistor M6 and the seventh transistor M7 in the auxiliary pull-down module 223 are turned off, the third node N3 maintains a low voltage by the first capacitor C1 to control the eighth transistor M8 to turn on, and the eighth transistor M8 provides the low level signal of the second constant voltage terminal V2 to the output terminal OUT2 after turning on. The output terminal OUT2 of the second output module 22 outputs the low level signal of the second scan signal at this time.
In addition, at other times than the times t1 'to t 5', the auxiliary pull-down module 223 in the second output module 22 is configured to stabilize the potential of the third node N3 under the combined action of the signal of the first clock signal terminal CK1, the signal of the second clock signal terminal CK2, and the first capacitor C1, so that the third node N3 maintains a low potential to control the eighth transistor M8 to be turned on, and provide the low level signal of the second constant voltage terminal V2 to the output terminal OUT2.
In addition, at other times than the times t1 'to t 5', when the first node N1 is at a low potential and the first clock signal terminal CK1 is at a low level signal, the thirteenth transistor M13 and the low fourteenth transistor M14 are simultaneously turned on, and then the high level signal of the first constant voltage terminal V1 is supplied to the fourth node N4, so that the second node N2 can be at a high potential and the potentials of the first node N1 and the second node N2 are opposite.
Through the analysis of the timing sequence of fig. 9, the shift register provided in the embodiment of the present invention can control the first output module 21 to output the first scan signal, where the first scan signal is a scan signal with a low level and valid, and can also control the second output module 22 to output the second scan signal, where the second scan signal is a scan signal with a high level and valid. Also, the output timing of the low level signal of the first scan signal is after the output timing of the high level signal of the second scan signal, so that the second scan signal can control the first reset transistor T3 and the threshold compensation transistor T2 to be turned on in the pixel circuit as illustrated in fig. 1 (the above-described embodiment illustrates that the second scan signal can be supplied from the shift register of the adjacent stage), and the first scan signal can control the data write transistor T1 and the second reset transistor T4 to be turned on in the pixel circuit as illustrated in fig. 1. Therefore, a group of driving circuits can work together with the pixel circuit, and simultaneously enable signals are respectively provided for n-type transistors and p-type transistors in the pixel circuit, so that the number of the driving circuits can be reduced, the number of transistors in a non-display area is reduced, and the narrowing of the frame of the display panel is facilitated.
As shown in the dashed line in fig. 9, in the embodiment of the present invention, when the shift register is driven to operate, the rising edge of the signal at the second clock signal terminal CK2 is delayed from the falling edge of the signal at the third clock signal terminal CK 3. Alternatively, the rising edge of the signal of the second clock signal terminal CK2 is delayed by about 1 μs from the falling edge of the signal of the third clock signal terminal CK 3. At time t 5' illustrated in fig. 9, the voltage of the third clock signal terminal CK3 changes from high to low, and the potential of the second node N2 changes from low to high. In an initial period in which the voltage of the third clock signal terminal CK3 starts to be low from high, the start of the second node N2 is changed from low to high, if the signal of the second clock signal terminal CK2 is already high in this initial period, the ninth transistor M9 (the first protection module 224) is not turned off in time when the second node N2 is still at a lower potential, the high level signal of the second clock signal terminal CK2 is given to the third node N3, so that the third node N3 is high, and the eighth transistor M8 is turned off. Meanwhile, when the second node N2 is still at a lower potential, the fifth transistor M5 is not turned off in time, so that a part of the high level of the second clock signal terminal CK2 is output to the output terminal OUT2 of the second output module 22, resulting in abnormal output of the second scan signal. In the embodiment of the invention, the timing sequence of the clock signal is designed, the rising edge of the signal of the second clock signal end CK2 is set to be delayed from the falling edge of the signal of the third clock signal end CK3, and in the initial period of time t 5', the second clock signal end CK2 provides a low-level signal with one time to control the sixth transistor M6 to be turned on, the low-level signal of the second constant voltage end V2 is written into the third node N3, the eighth transistor M8 can be controlled to be turned on in time, and the low-level signal is timely output to the output end OUT2 of the second output module 22, so that the output end OUT2 of the second output module 22 can continuously output the low-level signal of the second scanning signal in the period of time, and the normal output of the second scanning signal is ensured.
In another embodiment, fig. 10 is a schematic diagram of another shift register according to an embodiment of the present invention, as shown in fig. 10, where the second output module 22 further includes a sixteenth transistor M16 and a fourth capacitor C4 based on the embodiment of fig. 8. The control terminal of the sixteenth transistor M16 is connected to the second constant voltage terminal V2, the first terminal of the sixteenth transistor M16 is connected to the first plate of the fourth capacitor C4, the second terminal of the sixteenth transistor M16 is connected to the output terminal OUT2 of the second output module 22, and the second plate of the fourth capacitor C4 is connected to the third node N3. The sixteenth transistor M16 is in a normally-on state, and when the third node N3 maintains the low potential to control the eighth transistor M8 to be turned on so as to output a low level signal to the output terminal OUT2 of the second output module 23, the low level signal of the output terminal OUT2 is transferred to the first plate of the fourth capacitor C4 through the sixteenth transistor M16, and due to the bootstrap effect of the fourth capacitor C4, the second plate of the fourth capacitor C4 is also in a low potential, and the second plate of the fourth capacitor C4 is connected to the third node N3, so that the third node N3 can be assisted to maintain the low potential.
Fig. 11 is a schematic diagram of a driving circuit according to an embodiment of the present invention, and fig. 11 illustrates a cascade connection of the m-1 st stage shift register 20 (m-1) to the m+2 th stage shift register 20 (m+2).
As shown in fig. 11, the display panel includes a first power line VGH, a second power line VGL, a first clock signal line 1CK, a second clock signal line 1XCK, a third clock signal line 2CK, and a second clock signal line 2XCK. The first clock signal line 1CK and the second clock signal line 1XCK are a group of clock signal lines, and the third clock signal line 2CK and the second clock signal line 2XCK are a group of clock signal lines.
The first constant voltage terminal V1 of each stage of shift register 20 is electrically connected to the first power line VGH, and the second constant voltage terminal V2 of each stage of shift register 20 is electrically connected to the second power line VGL.
The description will be given taking m as an odd number as an example. The first clock signal terminals CK1 of the even-numbered stage shift registers 20 are electrically connected to the first clock signal line 1CK, the second clock signal terminals CK2 of the even-numbered stage shift registers 20 are electrically connected to the third clock signal line 2CK, and the third clock signal terminals CK3 of the even-numbered stage shift registers 20 are electrically connected to the second clock signal line 1 XCK. The first clock signal terminals CK1 of the odd-numbered stage shift registers 20 are electrically connected to the second clock signal lines 1XCK, the second clock signal terminals CK2 of the odd-numbered stage shift registers 20 are electrically connected to the fourth clock signal lines 2XCK, and the third clock signal terminals CK3 of the odd-numbered stage shift registers 20 are electrically connected to the first clock signal lines 1 CK.
The input terminal IN of the 1 st stage shift register 20 is connected to the start signal terminal, the input terminal IN of the m-th stage shift register 20 (m) is electrically connected to the output terminal OUT1 of the first output module 21 of the m-1 st stage shift register 20 (m-1), and the input terminal IN of the m+1 th stage shift register 20 (m+1) is electrically connected to the output terminal OUT1 of the first output module 21 of the m-th stage shift register 20 (m). That is, IN the cascade shift register, the input terminal IN of the shift register is connected to the output terminal OUT1 of an output module 21 IN the shift register of the previous stage, except for the shift register of the 1 st stage.
Fig. 12 is a schematic diagram of a display device according to an embodiment of the present invention, and as shown in fig. 12, the display device includes a display panel 100 according to any embodiment of the present invention. The display device in the embodiment of the invention can be any device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book, a television, a smart watch and the like.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (14)
1. A display panel, comprising: the driving circuit comprises a plurality of shift registers which are cascaded;
the shift register comprises a control module, a first output module and a second output module;
the control module is used for controlling voltage signals of the control end of the first output module and the control end of the second output module;
the first output module is used for outputting a first scanning signal under the control of a voltage signal of a control end of the first output module, and the first scanning signal is a scanning signal with low level and effectiveness;
the second output module is used for outputting a second scanning signal under the control of the voltage signal of the control end of the second output module, and the second scanning signal is a scanning signal with high level and effectiveness;
The shift register comprises a first node and a second node; the first node and the second node are respectively and electrically connected with the control module;
the first output module comprises a first output pull-down module, and the control end of the first output pull-down module is electrically connected with the second node; the first output pull-down module is used for providing a low-level signal of a first clock signal end to the output end of the first output module under the control of the second node voltage;
the second output module comprises a second output pull-up module, and the control end of the second output pull-up module is respectively and electrically connected with the first node and the second node; the second output pull-up module is used for providing a high-level signal of a second clock signal end to the output end of the second output module under the control of the first node voltage and the second node voltage;
the duty ratio of the clock signal provided by the second clock signal end is smaller than that of the clock signal provided by the first clock signal end.
2. The display panel of claim 1, wherein the display panel comprises,
the first output module further comprises a first output pull-up module, and the control of the first output pull-up module is electrically connected with the first node; the first output pull-up module is used for providing a signal of a first constant voltage end to an output end of the first output module under the control of the first node voltage.
3. The display panel of claim 2, wherein the display panel comprises,
the first output pull-down module comprises a first transistor, a control end of the first transistor is electrically connected with the second node, a first end of the first transistor is electrically connected with the first clock signal end, and a second end of the first transistor is electrically connected with an output end of the first output module;
the first output pull-up module comprises a second transistor, a control end of the second transistor is electrically connected with the first node, a first end of the second transistor is electrically connected with the first constant voltage end, and a second end of the second transistor is electrically connected with an output end of the first output module.
4. The display panel of claim 1, wherein the display panel comprises,
the second output pull-up module comprises a third transistor, a fourth transistor and a fifth transistor;
the control end of the third transistor is electrically connected with the second node, the first end of the third transistor is electrically connected with the second clock signal end, and the second end of the third transistor is electrically connected with the first end of the fourth transistor;
the control end of the fourth transistor is electrically connected with the first node, and the second end of the fourth transistor is electrically connected with the output end of the second output module;
The control end of the fifth transistor is electrically connected with the second node, the first end of the fifth transistor is electrically connected with the second clock signal end, and the second end of the fifth transistor is electrically connected with the output end of the second output module.
5. The display panel of claim 1, wherein the display panel comprises,
the second output module further comprises a third node and a second output pull-down module, and the control end of the second output pull-down module is electrically connected with the third node; the second output pull-down module is used for providing a signal of a second constant voltage end to the output end of the second output module under the control of the third node voltage.
6. The display panel of claim 5, wherein the display panel comprises,
the second output module further comprises an auxiliary pull-down module, the auxiliary pull-down module is electrically connected with the third node, and the auxiliary pull-down module is used for stabilizing the potential of the third node under the control of the signal of the second clock signal end and the control of the signal of the first clock signal end.
7. The display panel of claim 6, wherein the display panel comprises,
the auxiliary pull-down module comprises a sixth transistor, a seventh transistor and a first capacitor;
The control end of the sixth transistor is electrically connected with the second clock signal end, the first end of the sixth transistor is electrically connected with the second constant voltage end, and the second end of the sixth transistor is electrically connected with the third node;
the control end of the seventh transistor is electrically connected with the first clock signal end, the first end of the seventh transistor is electrically connected with the second constant voltage end, and the second end of the seventh transistor is electrically connected with the third node;
the first polar plate of the first capacitor is electrically connected with the first clock signal end, and the second polar plate of the first capacitor is electrically connected with the third node.
8. The display panel of claim 5, wherein the display panel comprises,
the second output module further comprises a first protection module, a control end of the first protection module is electrically connected with the second node, a first end of the first protection module is electrically connected with the second clock signal end, and a second end of the first protection module is electrically connected with the third node;
the first protection module is used for controlling the second output pull-down module to be closed when the second output pull-up module is opened.
9. The display panel of claim 8, wherein the display panel comprises,
the second output pull-down module comprises an eighth transistor, and the first protection module comprises a ninth transistor;
the control end of the eighth transistor is electrically connected with the third node, the first end of the eighth transistor is electrically connected with the second constant voltage end, and the second end of the eighth transistor is electrically connected with the output end of the second output module;
the control terminal of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the second clock signal terminal, and the second terminal of the ninth transistor is electrically connected to the third node.
10. The display panel of claim 1, wherein the display panel comprises,
the control module comprises a first node control module and a second node control module;
the first node control module is electrically connected with the input end of the shift register, the third clock signal end, the second constant voltage end and the second node; the first node control module is configured to control a voltage of the first node according to a signal of an input end of the shift register, a signal of the third clock signal end, a signal of the second constant voltage end, and a signal of the second node; wherein, the period of the signal of the third clock signal end is the same as the period of the signal of the first clock signal end;
The second node control module is electrically connected with the input end of the shift register, the first clock signal end and the first constant voltage end; the second node control module is used for controlling the voltage of the second node according to the signal of the input end of the shift register, the signal of the first clock signal end and the signal of the first constant voltage end.
11. The display panel of claim 10, wherein the display panel comprises,
the first node control module includes a tenth transistor and an eleventh transistor;
the control end of the tenth transistor is electrically connected with the third clock signal end, the first end of the tenth transistor is electrically connected with the second constant voltage end, and the second end of the tenth transistor is electrically connected with the first node;
the control end of the eleventh transistor is electrically connected with the second node, the first end of the eleventh transistor is electrically connected with the input end of the shift register, and the second end of the eleventh transistor is electrically connected with the first node;
the second node control module includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;
the control end of the twelfth transistor is electrically connected with the third clock signal end, the first end of the twelfth transistor is electrically connected with the input end of the shift register, and the second end of the twelfth transistor is electrically connected with the second node;
The control end of the thirteenth transistor is electrically connected with the first clock signal end, the first end of the thirteenth transistor is electrically connected with the second end of the fourteenth transistor, and the second end of the thirteenth transistor is electrically connected with the second node;
the control terminal of the fourteenth transistor is electrically connected to the first node, and the first terminal of the fourteenth transistor is electrically connected to the first constant voltage terminal.
12. The display panel of claim 1, wherein the display panel comprises,
in one working cycle of the shift register: the output timing of the low level signal of the first scan signal is after the output timing of the high level signal of the second scan signal.
13. The display panel of claim 1, wherein the display panel comprises,
in the driving circuit:
the input end of the shift register of the 1 st stage is electrically connected with the initial signal end;
the input end of the m-th stage shift register is electrically connected with the output end of the first output module of the m-1-th stage shift register, and m is an integer not less than 2.
14. A display device comprising the display panel according to any one of claims 1 to 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN113963652B (en) * | 2021-11-12 | 2023-08-18 | 武汉天马微电子有限公司 | Display panel and driving method thereof |
| US12307948B2 (en) | 2022-06-30 | 2025-05-20 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, method of manufacturing the same and display device |
| CN115578979B (en) * | 2022-09-30 | 2024-09-13 | 厦门天马微电子有限公司 | Driving circuit, display panel and display device |
| CN118098107A (en) * | 2022-11-28 | 2024-05-28 | Oppo广东移动通信有限公司 | Scanning control circuit, display module and display device |
| CN115731839B (en) * | 2022-11-29 | 2024-07-19 | 云谷（固安）科技有限公司 | Display driving circuit and display device |
| CN116030762B (en) * | 2023-02-22 | 2025-04-08 | 京东方科技集团股份有限公司 | Display substrate, driving method thereof and display device |
| CN116564215A (en) * | 2023-05-26 | 2023-08-08 | 合肥维信诺科技有限公司 | Gate driving circuit, display panel and display device |
| CN116959356A (en) * | 2023-07-25 | 2023-10-27 | 云谷（固安）科技有限公司 | Shift register, scanning drive circuit and display panel |
| CN119380640A (en) * | 2023-07-26 | 2025-01-28 | 武汉华星光电半导体显示技术有限公司 | Gate drive circuit and display panel |
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