CN107845620A - Substrate structure and method for fabricating the same - Google Patents
Substrate structure and method for fabricating the same Download PDFInfo
- Publication number
- CN107845620A CN107845620A CN201610856776.2A CN201610856776A CN107845620A CN 107845620 A CN107845620 A CN 107845620A CN 201610856776 A CN201610856776 A CN 201610856776A CN 107845620 A CN107845620 A CN 107845620A
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- Prior art keywords
- layer
- board structure
- preparation
- protective layer
- insulating protective
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- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 152
- 239000011241 protective layer Substances 0.000 claims abstract description 52
- 238000005728 strengthening Methods 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000002360 preparation method Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 7
- 238000003466 welding Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000000084 colloidal system Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000012856 packing Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000005452 bending Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000012792 core layer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000002386 leaching Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
A substrate structure and a method for fabricating the same, comprising: the substrate structure comprises a substrate body, a circuit layer formed on the substrate body, an insulating protective layer formed on the substrate body and the circuit layer and exposing a part of the circuit layer, and a strengthening layer arranged on the exposed part of the circuit layer, so that the thickness of metal above the circuit layer is increased through the strengthening layer, and the substrate structure is prevented from warping and deforming when stressed.
Description
Technical field
The present invention particularly relates to a kind of board structure and its preparation method for having line layer on a kind of board structure.
Background technology
With booming and encapsulation technology the evolution of electronic industry, the size or volume of semiconductor package
Constantly reduce therewith, use the purpose for making the semiconductor package reach compact.
Figure 1A and Figure 1B is the diagrammatic cross-section of the preparation method of existing encapsulating structure.First, as shown in Figure 1A, base is encapsulated in one
Plate 1 puts setting semiconductor wafer 6 on brilliant side 10a, and is electrically connected with the package substrate 1 and the semiconductor by multiple bonding wires 7
Chip 6.Afterwards, as shown in Figure 1B, using mould 9 formed packing colloid 8 on the package substrate 1 to coat the semiconductor wafer
6。
The structure of existing package substrate 1 mainly includes a substrate body 10, multiple line layers 11 and an at least welding resisting layer
12.The line layer 11, can also be in the spacious area of substrate body 10 in addition to comprising conductive trace (figure omits) and electric contact mat 110
An at least copper sheet 111 (plant ball side 10b as shown in Figure 1A) is set up in place of (non-electrical wiring region), to improve the package substrate 1
The problem of radiating, and at least one opening 120 can be formed by removing the part material of the welding resisting layer 12, and expose the copper sheet
111, and then increase the radiating effect of the line layer 11.
However, in existing encapsulating structure 1, when the opening 120 of the welding resisting layer 12 is excessive, the welding resisting layer 12 and the line layer
Great difference in height r can be produced between 11, therefore when 1 stress of package substrate, the torque of bending, and the package substrate can be produced
1 thickness in the region of the opening 120 is also relatively thin, causes stress tolerance poor, and molding is carried out (i.e. so that working as
Form the packing colloid 8) when, after the mould flowing pressure of the packing colloid 8 is bestowed on the package substrate 1, as shown in Figure 1B, the base
Warpage (warpage) deformation occurs because of pressure differential caused by two-way pressure difference for plate body 10.
In addition, to also result in the semiconductor wafer 6 chipping (rent K as shown in Figure 1B) for the situation of warpage, cause
Reduce product yield.
Therefore, the variety of problems of above-mentioned prior art how is overcome, it is real into the problem for desiring most ardently solution at present.
The content of the invention
In view of the disadvantages of above-mentioned prior art, the present invention provides a kind of board structure and its preparation method, to avoid substrate
The situation of buckling deformation occurs when stress for structure.
Board structure, including：Substrate body；Line layer, it is formed in the substrate body；Insulating protective layer, it is formed
On the substrate body and the line layer, and the part surface of the line layer is made to expose to the insulating protective layer；And strengthening layer,
It is on the exposed parts surface of the line layer.
The present invention also provides a kind of preparation method of board structure, including：There is provided one has the base of line layer and insulating protective layer
Plate body, wherein, in the substrate body, the insulating protective layer is located on the substrate body and the line layer line layer,
And the part surface of the line layer is made to expose to the insulating protective layer；And strengthening layer is formed in the exposed parts table of the line layer
On face.
In foregoing board structure and its preparation method, the insulating protective layer has multiple perforates, to make the part of the line layer
It is surface exposed in those perforates.
In foregoing board structure and its preparation method, the line layer includes electric contact mat and miscellaneous function portion, to make the electricity
Property engagement pad and miscellaneous function portion expose to the insulating protective layer.
In foregoing board structure and its preparation method, the material of the strengthening layer is identical with the material of the line layer.
In foregoing board structure and its preparation method, the material for forming the strengthening layer is metal.
In foregoing board structure and its preparation method, in addition to surface-treated layer is formed on the strengthening layer.For example, the surface
The surface of process layer flushes the surface of the insulating protective layer.Include forming diaphragm in the insulating protective layer and the surface treatment again
On layer.
In foregoing board structure and its preparation method, the height of the strengthening layer is less than, more than or equal to the insulating protective layer
Highly.
In foregoing board structure and its preparation method, in addition to diaphragm is formed on the insulating protective layer and the strengthening layer.
From the foregoing, it will be observed that the board structure and its preparation method of the present invention, are mainly formed at the outer of the line layer by the strengthening layer
Reveal on surface, to increase the line layer thickness overall with strengthening layer, that is, increase metal thickness and lift structure intensity, with
Avoid the board structure from producing the situation of bending moment when stress, and the stress tolerance of the board structure can be lifted, therefore work as
When carrying out molding, it is avoided that the situation of buckling deformation occurs for the substrate body, and be avoided that to connect and be placed in the substrate knot
The chipping situation of the electronic installation of such as chip on structure, and then lift product yield.
Brief description of the drawings
Figure 1A to Figure 1B is the diagrammatic cross-section of the preparation method of existing encapsulating structure；And
Fig. 2A to Fig. 2 C is the diagrammatic cross-section of the preparation method of the board structure of the present invention；And
Fig. 3 A and Fig. 3 B are the diagrammatic cross-section of Fig. 2 B other embodiments.
Symbol description:
1 package substrate
10,20 substrate bodies
10a puts brilliant side
10b plants ball side
11,21 line layers
110,210 electric contact mats
111 copper sheets
12 welding resisting layers
120 openings
2 board structures
211 miscellaneous function portions
22 insulating protective layers
22a isolating parts
22b covering parts
220 perforates
23,33 strengthening layers
24 surface-treated layers
25 diaphragms
6 semiconductor wafers
7 bonding wires
8 packing colloids
9 moulds
R differences in height
K rents
H, t, H height.
Embodiment
Illustrate embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this explanation
Content disclosed in book understands other advantages and effect of the present invention easily.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only coordinating specification to be taken off
The content shown, for the understanding and reading of those skilled in the art, the enforceable qualifications of the present invention are not limited to, therefore
Do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, do not influenceing the present invention
Under the effect of can be generated and the purpose that can reach, it all should still fall and obtain the model that can cover in disclosed technology contents
In enclosing.Meanwhile in this specification it is cited such as " on ", " first ", " second " and " one " term, be merely convenient to describe
Understand, and be not used to limit the enforceable scope of the present invention, its relativeness is altered or modified, and technology is being changed without essence
Inside hold, when being also considered as the enforceable category of the present invention.
Fig. 2A to Fig. 2 C is the diagrammatic cross-section of the preparation method of the board structure 2 of the present invention.
As shown in Figure 2 A, there is provided one has at least substrate body 20 of a line layer 21 and an insulating protective layer 22, wherein,
In the substrate body 20, the insulating protective layer 22 is located on the substrate body 20 and the line layer 21 line layer 21, and
The part surface of the line layer 21 is made to expose to the insulating protective layer 22.
In the present embodiment, the substrate body 20 is the circuit configurations with core layer or seedless central layer (coreless),
And the substrate body 20 puts brilliant side with planting ball side with relative, wherein, Fig. 2A is to show any for putting brilliant side and plant ball side
The construction of person.It should be appreciated that ground, the substrate body 20 also can be other bearing wafers bearing part (such as wafer (wafer)) or
Other have metal line (routing) support plate, however it is not limited to above-mentioned.
In addition, the line layer 21 can be single or multiple lift, wherein, Fig. 2A is the construction of display outermost line layer.Specifically
Ground, the line layer 21 reroutes road floor (redistribution layer, abbreviation RDL) to be fanned out to (fan out) type, and is formed
The material of the line layer 21 is metal, and it may be selected, and ductility is higher and the preferable metal of conductibility, such as copper material.Should for example, working as
When substrate body 20 is the circuit configurations with core layer, the side such as machine drill or laser can be utilized according to the demand of upper and lower line layer 21
Formula and coordination galvanization metal fabrication methods turn on the through hole of upper and lower line layer 21 to be formed in the core layer.
Also, the line layer 21 includes conductive trace (figure omits), electric contact mat 210 and miscellaneous function portion 211 etc..Specifically
Ground, the miscellaneous function portion 211 are, for example, a sheet, and it can improve the electrical and engineering properties of the board structure 2, such as provide and dissipate
Heat, prevent cross-talk (cross talk), static discharge (Electrostatic Discharge, abbreviation ESD) and electromagnetic interference
The functions such as the generation of (Electromagnetic interference, abbreviation EMI).
In addition, the insulating protective layer 22 is welding resisting layer, such as green paint, it has multiple perforates 220, to make the line layer 21
Part surface exposes to those perforates 220.For example, the insulating protective layer 22 definition has an isolating part 22a (such as lower half) and one
Covering part 22b (such as first half).Specifically, isolating part 22a abuts the line layer 21, with provide respectively the conductive trace, electrically
Insulation effect between engagement pad 210 or miscellaneous function portion 211, and covering part 22b covers the line layer 21 and the isolating part
22a, it is electrically insulated effect with offer with avoiding the line layer 21 from being stained, and is opened in covering part 22b formed with those
Hole 220, to define those electric contact mats 210 electrically engage or define the miscellaneous function portion 211 to be dissipated
Heat.
As shown in Figure 2 B, a strengthening layer 23 is formed on the line layer 21 exposed outside in those perforates 220, to strengthen the base
The electrical and engineering properties of harden structure 2, for example, improving structural strength and radiating and other effects.
In the present embodiment, the material that forms the strengthening layer 23 is metal, such as electro-coppering, makes the material of the strengthening layer 23
It is identical with the material of the line layer 21.It should be appreciated that ground, the material of the strengthening layer 23 also can be other metal materials for being easy to radiating,
Such as gold, silver, aluminium, and it is formed using preparation methods such as other evaporations, sputter, chemical plating, electroless-platings.
In addition, the strengthening layer 23 substrate sheet relative less than the insulating protective layer 22 with respect to the height h of the substrate body 20
The height t of body 20.
Also, the strengthening layer 23 is applied to the line layer 21 in any one put brilliant side and plant ball side of the substrate body 20.
As shown in Figure 2 C, could be alternatively formed again a surface-treated layer 24 on the strengthening layer 23 using as anti oxidation layer, and
The strengthening layer 23 is avoided to aoxidize, and the surface-treated layer 24 is, for example, to be beneficial to the follow-up material for carrying out welding manufacture method.Then,
In follow-up manufacture method, the board structure 2 can on those electric contact mats 210 (surface-treated layer 24) combine such as soldered ball
Conducting element is put such as semiconductor package part or the electronic installation of other structures (such as chip) (figure omits) for connecing, and be available for it is follow-up again
Carry out molding (forming packing colloid).
In the present embodiment, the material for forming the surface-treated layer 24 is ni au (Ni/Au), changes nickel palladium leaching gold
(Electroless Nickel/Electroless Palladium/Immersion Gold, abbreviation ENEPIG), directly leaching gold
(Direct Immersion Gold, abbreviation DIG) or other materials.
The preparation method of the present invention is formed on the exposed surface of the line layer 21 by the strengthening layer 23, to reduce the perforate
Difference in height at 220 between the insulating protective layer 22 and metal surface, to avoid the board structure 2 from producing bending force when stress
The situation of square, and stress tolerance of the board structure 2 at the perforate 220 can be lifted, therefore when carrying out molding,
It is avoided that the situation of buckling deformation occurs for the substrate body 20, and then avoids connecing and be placed on the board structure 2 such as the electronics of chip
The chipping situation of device, lift product yield.
If in addition, the surface of the surface-treated layer 24 flushes the surface of the insulating protective layer 22, as shown in Figure 2 C, can be beneficial to
The use of product.For example, when the board structure 2 is applied to plug socket (socket) (direct insertion memory in such as computer
Plug clip in body module or video game etc.) when, the insulating protective layer 22 is flushed by the surface of the surface-treated layer 24
Surface, be avoided that in swapping process, plugging member occur and blocks or the bad situation of other plugs.It should be appreciated that ground, such as schemes
Shown in 3A, if the strengthening layer 33 is equal to the insulating protective layer 22 with respect to the substrate body 20 with respect to the height t of the substrate body 20
Height t when, can also be avoided that in swapping process, plugging member occurs and blocks or the bad situation of other plugs.
Also, the thickness of the strengthening layer 23 according to the different demands of product, can be adjusted.If for example, the board structure 2 passes through different side
Property conducting resinl (Anisotropic Conductive Film, abbreviation ACF) combines chip, other soft or hard plates or liquid crystal display
During the various electronic components such as device (liquid-crystal display, abbreviation LCD), the strengthening layer 33 is with respect to the substrate body 20
Height H can be more than the insulating protective layer 22 with respect to the substrate body 20 height t, as shown in Figure 3 B, to provide appropriate thickness
Conducting particles in degree crushing anisotropic conductive adhesive paste (ACF).Specifically, height H of the strengthening layer 33 with respect to the substrate body 20
Height t about 10um of the insulating protective layer 22 with respect to the substrate body 20 need to be higher than, in favor of crushing anisotropic conductive adhesive paste (ACF)
In conducting particles.
No matter in addition, the height h of the strengthening layer 23,33, t, why is H, and alternative is (as transported the board structure 2
During) diaphragm 25 is formed on the insulating protective layer 22 and the strengthening layer 23,33 (or the surface-treated layer 24), to keep away
Exempt from strengthening layer 23,33 (or the surface-treated layer 24) scratch.In an embodiment, the diaphragm 25 may be, for example, adhesive tape.
The present invention provides a kind of board structure 2 again, including：One substrate body 20, at least a line layer 21, an insulation protection
The strengthening layer 23,33 of layer 22 and one.
An at least line layer 21 is laid with described substrate body 20, and the line layer 21 includes multiple electric contact mats
210 and at least one miscellaneous function portion 211.
Described insulating protective layer 22 is in the substrate body 20 and the line layer 21, to make the part of the line layer 21
Surface (electric contact mat 210 and miscellaneous function portion 211) exposes to the insulating protective layer 22.
Described strengthening layer 23,33 is on the exposed parts surface of the line layer 21.
In an embodiment, the insulating protective layer 22 has multiple perforates 220, to make the part surface of the line layer 21
(such as the electric contact mat 210 and miscellaneous function portion 211) exposes to those perforates 220.
In an embodiment, the material of the strengthening layer 23,33 is identical with the material of the line layer 21.
In an embodiment, the material for forming the strengthening layer 23,33 is metal.
In an embodiment, the board structure 2 includes a surface-treated layer 24 again, and it is formed on the strengthening layer 23.Example
Such as, the upper surface of the upper surface flush of the surface-treated layer 24 insulating protective layer 22.Or the board structure 2 may include one
Diaphragm 25, it is formed on the insulating protective layer 22 and the surface-treated layer 24.
In an embodiment, the height H, t of the strengthening layer 33 are more than or equal to the height t of the insulating protective layer 22.
In an embodiment, the height h of the strengthening layer 23 is less than the height t of the insulating protective layer 22.
In an embodiment, the board structure 2 includes a diaphragm 25 again, and it is strong with this that it is formed at the insulating protective layer 22
Change on layer 33.
In summary, board structure of the invention and its preparation method, by the design of the strengthening layer, with increase the line layer and
The integral thickness of strengthening layer, that is, increase metal thickness and lift structure intensity, to avoid the board structure from being produced when stress
The situation of bending moment, and the stress tolerance of the board structure can be lifted, therefore it is avoided that buckling deformation occurs for the substrate body
Situation, to lift product yield.
Above-described embodiment is only to the principle and its effect of the illustrative present invention, not for the limitation present invention.Appoint
What those skilled in the art can modify under the spirit and scope without prejudice to the present invention to above-described embodiment.Therefore originally
The rights protection scope of invention, should be as listed by claims.
Claims (22)
1. a kind of board structure, it is characterized in that, the board structure includes：
Substrate body；
Line layer, it is formed in the substrate body；
Insulating protective layer, it is formed on the substrate body and the line layer, and makes the part surface of the line layer expose to this
Insulating protective layer；And
Strengthening layer, it is formed on the exposed parts surface of the line layer.
2. board structure as claimed in claim 1, it is characterized in that, the line layer includes electric contact mat and miscellaneous function portion,
And the electric contact mat and miscellaneous function portion is made to expose to the insulating protective layer.
3. board structure as claimed in claim 1, it is characterized in that, the insulating protective layer has multiple perforates, to make the circuit
The part surface of layer exposes to those perforates.
4. board structure as claimed in claim 1, it is characterized in that, the material of the strengthening layer is identical with the material of the line layer.
5. board structure as claimed in claim 1, it is characterized in that, the material for forming the strengthening layer is metal.
6. board structure as claimed in claim 1, it is characterized in that, the board structure also includes the table being formed on the strengthening layer
Face process layer.
7. board structure as claimed in claim 6, it is characterized in that, the upper surface flush of the surface-treated layer insulating protective layer
Upper surface.
8. board structure as claimed in claim 6, it is characterized in that, the board structure also include being formed at the insulating protective layer with
Diaphragm on the surface-treated layer.
9. board structure as claimed in claim 1, it is characterized in that, the height of the strengthening layer is more than or equal to the insulating protective layer
Height.
10. board structure as claimed in claim 1, it is characterized in that, the height of the strengthening layer is less than the height of the insulating protective layer
Degree.
11. board structure as claimed in claim 1, it is characterized in that, the board structure also includes being formed at the insulating protective layer
With the diaphragm on the strengthening layer.
12. a kind of preparation method of board structure, it is characterized in that, the preparation method includes：
There is provided one has the substrate body of line layer and insulating protective layer, wherein, for the line layer in the substrate body, this is exhausted
Edge protective layer makes the part surface of the line layer expose to the insulating protective layer in the substrate body and the line layer；
And
Strengthening layer is formed on the exposed parts surface of the line layer.
13. the preparation method of board structure as claimed in claim 12, it is characterized in that, the line layer includes electric contact mat and auxiliary
Function part, and make the electric contact mat and miscellaneous function portion expose to the insulating protective layer.
14. the preparation method of board structure as claimed in claim 12, it is characterized in that, the insulating protective layer has multiple perforates, with
The part surface of the line layer is made to expose to those perforates.
15. the preparation method of board structure as claimed in claim 12, it is characterized in that, the material of the strengthening layer and the material of the line layer
Matter is identical.
16. the preparation method of board structure as claimed in claim 12, it is characterized in that, the material for forming the strengthening layer is metal.
17. the preparation method of board structure as claimed in claim 12, it is characterized in that, the preparation method also include being formed surface-treated layer in
On the strengthening layer.
18. the preparation method of board structure as claimed in claim 17, it is characterized in that, this is exhausted for the upper surface flush of the surface-treated layer
On the surface of edge protective layer.
19. the preparation method of board structure as claimed in claim 17, it is characterized in that, the preparation method is also exhausted in this including forming diaphragm
On edge protective layer and the surface-treated layer.
20. the preparation method of board structure as claimed in claim 12, it is characterized in that, the height of the strengthening layer is exhausted more than or equal to this
The height of edge protective layer.
21. the preparation method of board structure as claimed in claim 12, it is characterized in that, the height of the strengthening layer is less than the insulation protection
The height of layer.
22. the preparation method of board structure as claimed in claim 12, it is characterized in that, the preparation method is also exhausted in this including forming diaphragm
On edge protective layer and the strengthening layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105130309 | 2016-09-20 | ||
| TW105130309A TWI615936B (en) | 2016-09-20 | 2016-09-20 | Substrate structure and the manufacture thereof |
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| CN107845620A true CN107845620A (en) | 2018-03-27 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112447608A (en) * | 2019-09-02 | 2021-03-05 | 矽品精密工业股份有限公司 | Electronic package, bearing structure thereof and manufacturing method thereof |
| US20210343574A1 (en) * | 2020-04-29 | 2021-11-04 | Semiconductor Components Industries, Llc | Curved semiconductor die systems and related methods |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI829396B (en) * | 2022-10-21 | 2024-01-11 | 欣興電子股份有限公司 | Circuit board structure and manufacturing method thereof |
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| CN202503808U (en) * | 2012-02-29 | 2012-10-24 | 博罗县精汇电子科技有限公司 | Circuit board with protection film for protecting binding area |
| CN104851865A (en) * | 2014-02-17 | 2015-08-19 | 矽品精密工业股份有限公司 | Flip-chip package substrate, flip-chip package and fabrication method thereof |
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| TW541652B (en) * | 2002-07-29 | 2003-07-11 | Megic Corp | Method for fabricating a circuit layer |
| TWI315658B (en) * | 2007-03-02 | 2009-10-01 | Phoenix Prec Technology Corp | Warp-proof circuit board structure |
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| TW461053B (en) * | 1999-11-09 | 2001-10-21 | Advanced Semiconductor Eng | Strength and electricity enhanced ball grid array package structure and manufacturing method of the same |
| CN102054710A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Nucleus-free layer encapsulation substrate and its manufacturing method |
| CN202503808U (en) * | 2012-02-29 | 2012-10-24 | 博罗县精汇电子科技有限公司 | Circuit board with protection film for protecting binding area |
| CN104851865A (en) * | 2014-02-17 | 2015-08-19 | 矽品精密工业股份有限公司 | Flip-chip package substrate, flip-chip package and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112447608A (en) * | 2019-09-02 | 2021-03-05 | 矽品精密工业股份有限公司 | Electronic package, bearing structure thereof and manufacturing method thereof |
| US20210343574A1 (en) * | 2020-04-29 | 2021-11-04 | Semiconductor Components Industries, Llc | Curved semiconductor die systems and related methods |
| US12020972B2 (en) * | 2020-04-29 | 2024-06-25 | Semiconductor Components Industries, Llc | Curved semiconductor die systems and related methods |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI615936B (en) | 2018-02-21 |
| TW201814866A (en) | 2018-04-16 |
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