[go: up one dir, main page]

CN107784142B - Thermal simulation method of semiconductor power component - Google Patents

Thermal simulation method of semiconductor power component Download PDF

Info

Publication number
CN107784142B
CN107784142B CN201610780319.XA CN201610780319A CN107784142B CN 107784142 B CN107784142 B CN 107784142B CN 201610780319 A CN201610780319 A CN 201610780319A CN 107784142 B CN107784142 B CN 107784142B
Authority
CN
China
Prior art keywords
finite element
element model
sub
component
semiconductor power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610780319.XA
Other languages
Chinese (zh)
Other versions
CN107784142A (en
Inventor
谢腾飞
颜骥
任亚东
张明
曾文彬
刘应
孙文伟
郭金童
唐豹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuzhou CRRC Times Semiconductor Co Ltd
Original Assignee
Zhuzhou CRRC Times Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuzhou CRRC Times Semiconductor Co Ltd filed Critical Zhuzhou CRRC Times Semiconductor Co Ltd
Priority to CN201610780319.XA priority Critical patent/CN107784142B/en
Publication of CN107784142A publication Critical patent/CN107784142A/en
Application granted granted Critical
Publication of CN107784142B publication Critical patent/CN107784142B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • G06F30/23Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention relates to a thermal simulation method of a semiconductor power assembly, wherein the semiconductor power assembly comprises at least two sub-components, and the thermal simulation method of the semiconductor power assembly comprises the following steps: establishing a finite element model library of a plurality of subcomponents; selecting a finite element model of the sub-component from the finite element model library, and assembling to form a finite element model of the semiconductor power assembly; and carrying out thermal simulation calculation on the finite element model of the semiconductor power component. Thermal simulation can be performed with high efficiency by this method.

Description

Thermal simulation method of semiconductor power component
Technical Field
The invention relates to the technical field of thermal simulation, in particular to a thermal simulation method of a semiconductor power assembly.
Background
A semiconductor power assembly includes a semiconductor power device and a corresponding heat sink assembled therewith. The semiconductor power device is widely applied to the fields of rail transit, power transmission and distribution, industrial power supply and the like due to the characteristics of high voltage and large current, and has wide prospect. Since the device generates a certain heat loss in application, the junction temperature of the device increases, and the increase of the junction temperature has a great influence on the electrical characteristics of the device, a corresponding heat sink is usually required for cooling. Therefore, it is very important to thermally design a semiconductor power module in the process of designing it. Thermal design directly affects the reliability and quality of the component design. Among them, thermal simulation is the main means of thermal design, and among them, finite element thermal simulation is one of the commonly used means.
In the prior art, a geometric model is generally established for the semiconductor power module as a whole, and then a finite element model is established on the basis of the geometric model. However, after the finite element model is built, if the semiconductor power device or the heat sink needs to be modified, the geometric model of the entire assembly must be re-built, and then the finite element model must be re-built. This results in very inefficient thermal simulation and great inconvenience to thermal design.
Therefore, a thermal simulation method for a semiconductor power device with high efficiency is needed.
Disclosure of Invention
In view of the above problems, the present invention provides a thermal simulation method for a semiconductor power module, by which thermal simulation can be performed with high efficiency.
According to the invention, the thermal simulation method of the semiconductor power assembly is provided, the semiconductor power assembly comprises at least two sub-components, and the thermal simulation method of the semiconductor power assembly comprises the following steps: establishing a finite element model library of a plurality of subcomponents; selecting a finite element model of the sub-component from the finite element model library, and assembling to form a finite element model of the semiconductor power assembly; and carrying out thermal simulation calculation on the finite element model of the semiconductor power component.
By the thermal simulation method of the semiconductor power assembly, provided by the invention, the finite element models of at least two sub-components can be assembled together to form the finite element model of the semiconductor power assembly. Thus, if some portion of the finite element model of the semiconductor power component needs to be modified, the finite element model of the entire semiconductor power component need not be re-established. Thus, the efficiency of modeling is improved, and further, the efficiency of performing thermal simulation is improved.
In one embodiment, creating a library of finite element models for a plurality of subcomponents may be accomplished by: respectively establishing geometric models of a plurality of subcomponents; respectively establishing a finite element model of each sub-component on the basis of the geometric model of each sub-component; and defining assembly interfaces on the finite element models of the sub-components, wherein the assembly interfaces on the finite element models of the sub-components which need to be connected with each other correspond to each other. In this way, a finite element model of a plurality of subcomponents can be built up in parallel.
In one embodiment, the assembly interface is defined by a Cartesian coordinate system. The assembly interface formed in this manner allows for easier and more extensive matching between the finite element models of the sub-components.
In one embodiment, finite element models of different subcomponents are built in parallel by different operating equipment. Thereby facilitating rapid assembly of a finite element model of a plurality of subcomponents.
In one embodiment, after assembling and forming a finite element model of a semiconductor power component, checking whether the finite element model of the semiconductor power component is correct, and if so, performing thermal simulation calculation on the finite element model of the semiconductor power component; if not, the finite element model of the sub-component is re-selected from the library of finite element models and assembled to form the finite element model of the semiconductor power assembly. By this procedure, it is possible to check in time and efficiently whether the finite element model of the assembled semiconductor power module is correct and, if not correct, to modify it in time.
In one embodiment, after assembling and forming a finite element model of a semiconductor power component, checking whether the finite element model of the semiconductor power component is correct, and if so, performing thermal simulation calculation on the finite element model of the semiconductor power component; if not, further judging whether the finite element model of the sub-component needs to be deleted, and if so, directly deleting the finite element model of the sub-component. In this way, no re-modeling is required, only the finite element model of the required sub-component is deleted.
In one embodiment, after assembling and forming a finite element model of a semiconductor power component, checking whether the finite element model of the semiconductor power component is correct, and if so, performing thermal simulation calculation on the finite element model of the semiconductor power component; if not, further judging whether the finite element model of the sub-component needs to be added or not, and if so, selecting the finite element model of the required sub-component from the finite element model library. In this way, the finite element model of the semiconductor power assembly does not need to be re-established, and only the finite element model of a new sub-component is selected from the finite element model library of the sub-component and added.
In one embodiment, after assembling and forming a finite element model of a semiconductor power component, checking whether the finite element model of the semiconductor power component is correct, and if so, performing thermal simulation calculation on the finite element model of the semiconductor power component; and if the component is not correct, further judging whether the finite element model of the sub-component needs to be replaced, and if the component needs to be replaced, selecting the finite element model of the required sub-component from the finite element model library to replace the finite element model of the sub-component needing to be replaced in the finite element models of the assembled semiconductor power components. In this way, the finite element model of the semiconductor power component does not need to be rebuilt, but rather the finite element model of the sub-component that needs to be replaced is replaced.
In one embodiment, after assembling and forming a finite element model of a semiconductor power component, checking whether the finite element model of the semiconductor power component is correct, and if so, performing thermal simulation calculation on the finite element model of the semiconductor power component; if not, further judging whether the assembly position is correct, if not, redefining an assembly interface of the finite element model of the sub-component, and then re-assembling the finite element model of the sub-component. In this way, if the assembly interfaces are found to not match or not match very properly, the assembly interfaces are redefined.
Compared with the prior art, the invention has the advantages that: the finite element models of the at least two sub-components can be assembled together to form a finite element model of the semiconductor power assembly. Thus, if some portion of the finite element model of the semiconductor power component needs to be modified, the finite element model of the entire semiconductor power component need not be re-established. Thus, the efficiency of modeling is improved, and further, the efficiency of performing thermal simulation is improved.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
fig. 1 shows a flow chart of a thermal simulation method of a semiconductor power module of the present invention.
In the drawings, like parts are provided with like reference numerals. The figures are not drawn to scale.
Detailed Description
The invention will be further explained with reference to the drawings.
The semiconductor power assembly includes at least two subcomponents. The at least two subcomponents include a semiconductor power device and a heat sink. Alternatively, the at least two sub-members can constitute a semiconductor power device and a heat sink.
As shown in fig. 1, the thermal simulation method of the semiconductor power module includes the following steps.
First, a library of finite element models is built for a plurality of subcomponents. In the finite element model library, finite element models of subcomponents required for forming the semiconductor power module are stored.
Finite element models of the subcomponents are then selected from the library of finite element models and assembled together to form a finite element model of the semiconductor power assembly.
After that, the thermal simulation calculation can be performed on the finite element model of the semiconductor power component. After the thermal simulation calculation turns over, the results may be read and saved.
In this way, a finite element model of a semiconductor power assembly can be obtained by fitting together the finite element models of at least two sub-components. And once a part needs to be modified, only the finite element model of the corresponding sub-component needs to be modified, and the finite element model of the whole semiconductor power assembly does not need to be reconstructed. Thus, the efficiency of modeling is improved, and further, the efficiency of performing thermal simulation is improved.
As shown in FIG. 1, a library of finite element models of subcomponents may be created by the following steps.
First, a geometric model of a plurality of subcomponents is established.
Then, a finite element model of the sub-component is established separately on the basis of several models of the respective sub-components.
After this, a corresponding assembly interface is provided on the finite element model of each subcomponent.
For a thermal simulation process, only the finite element models of the sub-components required by the thermal simulation process can be established, and the finite element models of the sub-components with various types, sizes and functions can be established for replacement or modification or for other thermal simulation processes in the future.
Preferably, the finite element models of the different subcomponents are built in parallel, independently of each other, by different operating devices (e.g., computers). In this way, finite element models of multiple sub-components can be created simultaneously, independent of each other, without interfering with each other. Therefore, the modeling efficiency is improved.
Preferably, the assembly interface is defined by a cartesian coordinate system. The assembly interface formed in this manner allows for easier and more extensive matching between the finite element models of the sub-components.
In addition, as shown in fig. 1, after the finite element model of the semiconductor power component is formed, it is preferably checked whether the finite element model of the semiconductor power component is correct. If the result is correct, performing thermal simulation calculation; if not, the finite element model of the sub-component may be reselected and reassembled to form the finite element model of the semiconductor power assembly. And circulating until the finite element model of the semiconductor power component is verified to be correct.
In one embodiment, after verifying that the finite element model of the semiconductor power component is incorrect, the already assembled finite element model of the semiconductor power component may be discarded and the finite element model of the sub-component may be reselected and assembled to obtain a new finite element model of the semiconductor power component.
In a preferred embodiment, a further determination is made after an incorrect finite element model of the semiconductor power component is detected.
For example, it may be further determined whether a finite element model of the sub-component needs to be pruned. If necessary, the finite element model of the respective sub-component is deleted directly from the finite element model of the already assembled semiconductor power component.
For example, it may be further determined whether a finite element model of the sub-component needs to be added. If desired, a finite element model of the desired sub-component is selected from a library of finite element models and added directly to the finite element model of the already formed semiconductor power assembly.
For example, it can be further determined whether the finite element model of the sub-component needs to be replaced. Selecting the finite element model of the required sub-component from the finite element model library replaces the finite element model of the sub-component needing to be replaced in the finite element model of the assembled semiconductor power component if required.
For example, it is possible to further judge whether or not the fitting position is correct. If not, the assembly interface is adjusted or redefined.
By the method, the finite element model of the semiconductor power component can be efficiently and quickly established.
It should be appreciated that one or more of the above determinations may be made simultaneously or sequentially after verifying that the finite element model of the semiconductor power component is incorrect. In the case where the determination is made in order, it is preferable that the determination be made in the order of whether the assembly position is correct, whether replacement is necessary, whether addition is necessary, and whether deletion is necessary, that is, a relatively simple determination be made first. However, the determination may be performed in other order as necessary. For example, it is also possible to make a judgment in the order of whether deletion is required, whether replacement is required, whether the assembly position is correct, and whether addition is required, and to make a corresponding modification of the advancement after one judgment, and then to make the next judgment. By such a sequence of determination, if the finite element model of the sub-component needs to be deleted or replaced, it is not necessary to determine whether the assembly position of the finite element model of the sub-component is correct, thereby improving the modeling efficiency.
The method can effectively improve the efficiency of building the semiconductor power component and thus improve the efficiency of performing thermal simulation.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (1)

1. A method of thermal simulation of a semiconductor power assembly, the semiconductor power assembly comprising at least two sub-components, the method of thermal simulation of a semiconductor power assembly comprising:
creating a library of finite element models of a plurality of sub-components, wherein the finite element models of different sub-components are created in parallel by different operating equipment, comprising:
respectively establishing geometric models of a plurality of subcomponents;
respectively establishing a finite element model of each sub-component on the basis of the geometric model of each sub-component, wherein the finite element model library of each sub-component is a finite element model of the sub-component containing different types, sizes and functional information; and
defining assembly interfaces on the finite element models of the sub-components, wherein the assembly interfaces on the finite element models of the sub-components which need to be connected with each other correspond to each other, and the assembly interfaces are defined by a Cartesian coordinate system;
selecting a finite element model of the sub-component from the finite element model library, and assembling to form a finite element model of the semiconductor power assembly;
checking whether a finite element model of the semiconductor power component is correct, wherein,
if the heat is correct, carrying out thermal simulation calculation on the finite element model of the semiconductor power component;
if not, directly reselecting the finite element model of the sub-component from the finite element model library, assembling to form the finite element model of the semiconductor power component, and after assembling and forming the finite element model of the semiconductor power component, checking whether the finite element model of the semiconductor power component is correct, wherein if the finite element model of the semiconductor power component is correct, performing thermal simulation calculation on the finite element model of the semiconductor power component;
if it is not, then further,
judging whether the finite element model of the sub-component needs to be deleted or not, and if so, directly deleting the finite element model of the sub-component;
judging whether a finite element model of the sub-component needs to be added or not, and if so, selecting the finite element model of the required sub-component from the finite element model library;
judging whether the finite element model of the sub-component needs to be replaced or not, if so, selecting the finite element model of the required sub-component from the finite element model library to replace the finite element model of the sub-component which needs to be replaced in the finite element models of the assembled semiconductor power assembly;
judging whether the assembly position is correct or not, if not, redefining an assembly interface of the finite element model of the sub-component, and then re-assembling the finite element model of the sub-component, wherein under the condition of sequentially judging, judging according to the sequence of whether the assembly position is correct or not, whether the assembly position needs to be replaced, whether the assembly position needs to be added and whether the assembly position needs to be deleted or not, or judging according to the sequence of whether the assembly position needs to be replaced, whether the assembly position is correct and whether the assembly position needs to be added, and if the finite element model of the sub-component needs to be deleted or replaced, judging whether the assembly position of the finite element model of the sub-component is correct or not is not needed, so that the modeling efficiency is improved.
CN201610780319.XA 2016-08-31 2016-08-31 Thermal simulation method of semiconductor power component Active CN107784142B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610780319.XA CN107784142B (en) 2016-08-31 2016-08-31 Thermal simulation method of semiconductor power component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610780319.XA CN107784142B (en) 2016-08-31 2016-08-31 Thermal simulation method of semiconductor power component

Publications (2)

Publication Number Publication Date
CN107784142A CN107784142A (en) 2018-03-09
CN107784142B true CN107784142B (en) 2021-10-19

Family

ID=61451025

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610780319.XA Active CN107784142B (en) 2016-08-31 2016-08-31 Thermal simulation method of semiconductor power component

Country Status (1)

Country Link
CN (1) CN107784142B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110263396A (en) * 2019-06-10 2019-09-20 哈尔滨工程大学 A kind of the virtual test platform and method of system in package SIP device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1979496A (en) * 2005-12-02 2007-06-13 中国科学院金属研究所 Copper-alloy pipe-material casting-milling technology parameter designing and optimizing method
WO2008126078A3 (en) * 2007-04-12 2009-06-11 Expert Dynamics Ltd System and method for generating a finite elements model of a pcb
CN102254061A (en) * 2011-06-09 2011-11-23 山东电力研究院 Finite element modeling and bearing method for line-tower coupling system of power transmission tower
CN103455686A (en) * 2013-09-17 2013-12-18 重庆大学 Modeling method of finite element model for overhead power transmission tower-line coupling system
CN104077428A (en) * 2014-02-26 2014-10-01 浙江工业大学 Remote finite element analysis method serving for industry alliance
CN105162324A (en) * 2015-10-26 2015-12-16 株洲南车时代电气股份有限公司 Direct-current high-voltage power supply and high-position energy taking device and power supplying method thereof
CN105631122A (en) * 2015-12-25 2016-06-01 鼎奇(天津)主轴科技有限公司 Thermal-deformation simulation analysis and modeling method of machine tool large piece

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030048269A1 (en) * 2001-09-12 2003-03-13 Powell Donald T. System and method for generating finite element models
CN103345561B (en) * 2013-07-16 2016-03-02 上海航天电源技术有限责任公司 A kind of hot simulating analysis of lithium ion battery with multilayer chip structure
US9607115B2 (en) * 2013-11-25 2017-03-28 Livermore Software Technology Corp. Methods and systems for reporting realistic kinetic energy of a multi-part finite element analysis model
US20160125108A1 (en) * 2014-11-03 2016-05-05 Tata Technologies Pte Limited Method and system for knowledge based interfacing between computer aided analysis and geometric model
CN104331566B (en) * 2014-11-12 2017-09-15 国家电网公司 500kV AC linear angle tower Electric Field Simulation Systems

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1979496A (en) * 2005-12-02 2007-06-13 中国科学院金属研究所 Copper-alloy pipe-material casting-milling technology parameter designing and optimizing method
WO2008126078A3 (en) * 2007-04-12 2009-06-11 Expert Dynamics Ltd System and method for generating a finite elements model of a pcb
CN102254061A (en) * 2011-06-09 2011-11-23 山东电力研究院 Finite element modeling and bearing method for line-tower coupling system of power transmission tower
CN103455686A (en) * 2013-09-17 2013-12-18 重庆大学 Modeling method of finite element model for overhead power transmission tower-line coupling system
CN104077428A (en) * 2014-02-26 2014-10-01 浙江工业大学 Remote finite element analysis method serving for industry alliance
CN105162324A (en) * 2015-10-26 2015-12-16 株洲南车时代电气股份有限公司 Direct-current high-voltage power supply and high-position energy taking device and power supplying method thereof
CN105631122A (en) * 2015-12-25 2016-06-01 鼎奇(天津)主轴科技有限公司 Thermal-deformation simulation analysis and modeling method of machine tool large piece

Also Published As

Publication number Publication date
CN107784142A (en) 2018-03-09

Similar Documents

Publication Publication Date Title
US9443044B2 (en) Determining a quality parameter for a verification environment
US8316332B1 (en) Constraint minimization method for formal verification
US10325036B2 (en) Method and system for determing welding process parameters
US8910099B1 (en) Method for debugging unreachable design targets detected by formal verification
EP3379436B1 (en) Method and apparatus for testing design of satellite wiring harness and signal processing units
US9864827B1 (en) System and method for modeling electronic circuit designs
US20140068533A1 (en) Information theoretic subgraph caching
WO2014048338A1 (en) Method for testing broadside path delay fault of digital combination integrated circuit
US20060123377A1 (en) Interconnect integrity verification
US8910105B1 (en) Routing process
US11409928B2 (en) Configurable digital twin
CN107784142B (en) Thermal simulation method of semiconductor power component
US8510693B2 (en) Changing abstraction level of portion of circuit design during verification
US10380301B1 (en) Method for waveform based debugging for cover failures from formal verification
US10289788B1 (en) System and method for suggesting components associated with an electronic design
US9098637B1 (en) Ranking process for simulation-based functional verification
US20080004826A1 (en) Mechanism for determining an accelerated test specification for device elements
Hauck et al. Electro-thermal simulation of multi-channel power devices on PCB with SPICE
US8885636B2 (en) Method and system for platform-independent VoIP dial plan design, validation, and deployment
US9202001B1 (en) System and method for electronic design routing between terminals
US10496767B1 (en) System and method for enhanced characterization for system identification of non-linear systems
US9886538B1 (en) System and method for using heterogeneous hierarchical configurations for electronic design reuse
US9990456B1 (en) Routing process including dynamically changing pad sizes
US8095338B2 (en) Data processing apparatus and method
JP5093508B2 (en) Loop optimization system, loop optimization method, and loop optimization program

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20200909

Address after: Room 309, semiconductor third line office building, Tianxin high tech park, Shifeng District, Zhuzhou City, Hunan Province

Applicant after: Zhuzhou CRRC times Semiconductor Co.,Ltd.

Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169

Applicant before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant