CN107680963A - Dynamic random access memory array and its domain structure, preparation method - Google Patents

Abstract

The invention provides a dynamic random access memory array and its layout structure and manufacturing method, so that the array region of the semiconductor substrate includes multiple rows of regions, each row of the multi-row regions includes a plurality of active regions, and the active region The rotational tilt directions in adjacent row regions are different, so that the pitch between the word lines across the active region is similar or even the same. Therefore, in the present invention, the direction of the active region in the dynamic random access memory array is changed from the original same-direction inclined configuration with the same extension direction to an interleaved row with different extension directions, so as to ensure the same operation function of the prototype layout configuration. Under the premise of improving the spacing between the effective word lines and improving the performance of the device.

Description

Dynamic random access memory array, its layout structure and manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a dynamic random access memory array and its layout structure and manufacturing method.

Background technique

Integrated circuits have evolved from integrating dozens of devices on a single chip to integrating millions of devices. The performance and complexity of traditional integrated circuits have far exceeded the original imagination. To achieve increases in complexity and circuit density (the number of devices that can fit on a given chip area), the feature size of a device, also called "geometry," has grown with each generation of integrated circuits Getting smaller and smaller. Increasing integrated circuit density not only increases the complexity and performance of integrated circuits, but also reduces costs for consumers. Making devices smaller is challenging because every process in integrated circuit manufacturing has a limit, that is, if a certain process is to be performed under the condition of being smaller than the feature size, the process or device arrangement needs to be replaced; in addition , due to the faster and faster device design requirements, there are process limitations in traditional processes and materials.

DRAM (Dynamic Random Access Memory), that is, dynamic random access memory is the most common system memory; the DRAM memory is a semiconductor device, and its performance has been greatly developed, but there is still a need for further development. Memory scaling is a challenging task because the inability to scale down memory cell size without reducing the storage capacity per memory cell area hinders the development of high-density memory. Scaling down devices is mainly applied to memory cells, and the memory cell array structure usually plays a key role in determining the chip size.

There are mainly two types of DRAM memories currently in use: one is a DRAM memory with an area of 8F ² memory cells; the other is a DRAM memory with an area of 6F ² memory cells. The memory with a 6F ² memory cell area provides some improvements in reducing the memory cell area, but there are still some problems in production using this technology, such as unreasonable word line design.

Contents of the invention

The object of the present invention is to provide a dynamic random access memory array and its layout structure and manufacturing method to improve the layout of the dynamic random access memory array and improve its performance.

In order to solve the above-mentioned technical problems, the present invention provides a dynamic random access memory array layout structure, which includes a plurality of isolation structures, active regions and word lines arranged in a semiconductor substrate, and the isolation structures are formed on the active Between districts;

The active region and the isolation structure are located in an array region of the semiconductor substrate, the array region includes multiple rows of regions, each row of the multi-row regions includes a plurality of the active regions, and The extension direction of the multiple rows of regions is perpendicular to the extension direction of the word lines, the rotation and inclination directions of the active regions in adjacent row regions are different, and each of the word lines spans the plurality of rows region one each of said active regions.

Optionally, for the layout structure of the DRAM array, the word lines have the same pitch.

Optionally, for the DRAM array layout structure, relative to the extension direction of the multi-row region, the absolute value of the included angle of the rotation tilt angle of the active region in the multi-row region is an acute angle .

Optionally, for the DRAM array layout structure, each of the active regions is strip-shaped, and the active regions between adjacent rows of regions are arranged in a staggered manner.

Optionally, for the DRAM array layout structure, the active regions in the same row region are arranged in parallel and have the same pitch.

Optionally, for the layout structure of the dynamic random access memory array, it is characterized in that it further includes bit lines formed above the semiconductor substrate, and the extension direction of the bit lines is the same as that of the multiple rows The direction in which the region extends.

The present invention also provides a dynamic random access memory array, comprising:

semiconductor substrate;

The active region and the isolation structure are located in the array region of the semiconductor substrate, the isolation structure isolates the adjacent active regions, the array region includes multiple rows of regions, and each row of the multi-row regions Each includes a plurality of active regions, and the rotation and tilt directions of the active regions in adjacent row regions are different; and

Word lines are formed in the semiconductor substrate, and each of the word lines crosses one of the active regions of the plurality of rows of regions.

Optionally, for the DRAM array, the word lines have the same pitch.

Optionally, for the DRAM array, relative to the extension direction of the multi-row regions, the absolute value of the included angle of the rotation tilt angles of the active regions in the multi-row regions is an acute angle.

Optionally, for the dynamic random access memory array, each of the active regions is strip-shaped, and the active regions between adjacent rows of regions are arranged in a staggered manner.

Optionally, for the DRAM array, the active regions in the same row are arranged in parallel and have the same pitch.

Optionally, the DRAM array further includes bit lines formed above the semiconductor substrate, and the extension direction of the bit lines is the same as the extension direction of the multi-row regions.

The present invention also provides a method for manufacturing a dynamic random access memory array, including:

Provide semiconductor substrates;

An active region is formed in the semiconductor substrate, the active region is located in an array region of the semiconductor substrate, the array region includes multiple rows of regions, and each row of the multi-row regions includes a plurality of In the active region, the rotation and tilt directions of the active region in adjacent row regions are different;

forming an isolation structure in the semiconductor substrate, the isolation structure is used to isolate adjacent active regions; and

Word lines are formed in the semiconductor substrate, and each of the word lines spans each of the active regions of the plurality of rows of regions.

Optionally, for the manufacturing method of the dynamic random access memory array, the word lines have the same pitch.

Optionally, the method for manufacturing the DRAM array further includes forming bit lines on the semiconductor substrate, the extension direction of the bit lines is the same as the extension direction of the multi-row regions.

In the dynamic random access memory array provided by the present invention and its layout structure and manufacturing method, the array region of the semiconductor substrate includes multiple rows of regions, each row of the multi-row regions includes a plurality of active regions, and the active regions The rotational tilt directions in adjacent row regions are different, so that the pitches between the word lines across the active region are similar or even the same. Therefore, in the present invention, the direction of the active region in the dynamic random access memory array is changed from the original same-direction inclined configuration with the same extension direction to an interleaved row with different extension directions, so as to ensure the same operation function of the prototype layout configuration. Under the premise, the spacing between the effective word lines is improved, which helps to improve the performance of the device.

Description of drawings

Fig. 1 is a schematic diagram of a dynamic random access memory array;

Fig. 2 is a schematic cross-sectional view along AA' in Fig. 1;

Fig. 3 is a schematic cross-sectional view along BB' in Fig. 1;

FIG. 4 is a schematic diagram of a layout structure of a DRAM array according to an embodiment of the present invention;

5 is a schematic cross-sectional view of a DRAM array along CC' in FIG. 4 according to an embodiment of the present invention;

6 is a schematic cross-sectional view of a DRAM array along DD' in FIG. 4 according to an embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of a DRAM array along EE' in FIG. 4 according to an embodiment of the present invention;

FIG. 8 is a schematic flowchart of a method for manufacturing a DRAM array according to an embodiment of the present invention;

Wherein, the reference signs are as follows:

1, 10-semiconductor substrate; 2, 20-active region;

3. 30-word line; 4. 40-bit line;

21-a row of regions; 22, 23-sub-regions;

410-first bit line layer; 420-second bit line layer;

5. 50-isolation structure; 6-dielectric layer;

60-bit line contact terminal; 70-dielectric layer.

detailed description

The dynamic random access memory array of the present invention and its layout structure and manufacturing method will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein , while still realizing the advantageous effects of the present invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the following description, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region, pad and/or pattern, it may directly on another layer or substrate, and/or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being 'under' another layer, it can be directly under, and/or one or more intervening layers may also be present. In addition, designations regarding 'on' and 'under' each layer may be made based on drawings.

FIG. 1 is a schematic diagram of a dynamic random access memory array, FIG. 2 is a schematic cross-sectional view along AA' in FIG. 1 , and FIG. 3 is a schematic cross-sectional view along BB' in FIG. 1 . As shown in FIGS. 1 to 3 , the DRAM array includes a semiconductor substrate 1 , an active region 2 , an isolation structure 5 , word lines 3 and bit lines 4 .

The active region 2 includes multiple rows of regions, each row of regions includes a plurality of sub-regions (or called active regions), and the sub-regions in each row of regions have the same extension direction, for example, all the sub-regions are along the third Direction (Z direction among Fig. 1, illustrate here, among Fig. 1, X, Y, Z are not three-dimensional three-dimensional coordinates, but indicate several directions on a plane) extend; strips. The word line 3 and the bit line 4 are formed on the semiconductor substrate 1, the word line 3 spans each sub-region of the multi-row region, and the bit line is formed above the word line , the bit line 4 spans a row of regions and corresponds to a sub-region of the row of regions. As can be seen from FIGS. 2 and 3 , the bit line 4 and the word line 3 are isolated by a dielectric layer (for example, silicon nitride) 6 (not shown in FIG. 1 ).

In order to show the structure of the dynamic random access memory array in more detail, please refer to Figure 2 and Figure 3, Figure 2 is a schematic cross-sectional view along A-A' in Figure 1; Figure 3 is a cross-sectional view along BB' in Figure 1 schematic diagram.

It can be seen from FIG. 2 that the bit lines 4 are formed on the semiconductor substrate 1 , specifically on a row of regions of the active region 2 . However, it can be seen from FIG. 3 that the word lines 3 are formed in the semiconductor substrate 1 , specifically across each sub-region of the plurality of rows of regions. As marked in Figure 3, from a sub-region on the left side in Figure 3, the spacing (such as the average pitch) of the word line 3 between the sub-region in the middle is W1, and the sub-region in the middle and the sub-region in the right The distance between the word lines 3 (such as the average distance) is W2, as can be seen from Figure 1, because the sub-regions of different rows are staggered, therefore, W2>W1, that is, the word line 3 is between each sub-region spanning The distance between the insulation and isolation trenches is not equal, which leads to the actual structure inhomogeneity, which is not conducive to the further optimization of the size of the DRAM, and easily affects the performance of the device.

Therefore, the present invention provides a dynamic random access memory array layout structure, thereby realizing the optimization of the word line of the dynamic random access memory array.

Referring to the schematic diagram of the layout structure of the DRAM array according to an embodiment of the present invention shown in FIG. 4, the layout structure of the DRAM array includes:

a semiconductor substrate 10;

a plurality of isolation structures 50, active regions 20 and word lines 30 arranged in the semiconductor substrate 10, the isolation structures 50 are formed between the active regions 20;

The active region 20 and the isolation structure 50 are located in an array region of the semiconductor substrate 10, the array region includes a plurality of rows of regions 21, and each row of regions 21 includes a plurality of the active regions 20, and The lateral extension direction of the multi-row regions 21 is perpendicular to the extension direction of the word lines 30, the rotation and inclination directions of the active regions 20 in adjacent row regions 21 are different, and each of the word lines 30 Each of the active regions 20 straddles the multi-row regions 21 .

For example, each row of regions 21 shown in FIG. 4 includes along the first direction (X direction in FIG. 4 , it is illustrated here that X, Y, and Z in FIG. 4 are not three-dimensional coordinates, but illustrate several directions on a plane. ) arranged multiple sub-regions 22, 23, the sub-regions 22, 23 in adjacent rows of regions 21 extend in different directions. Each of the sub-regions 22 and 23 corresponds to one active region 20 .

When the active region 20 in the first row of regions 21 (the first horizontal row from top to bottom in FIG. 4 ) transverse to the word line 30 is rotated and tilted counterclockwise, it is adjacent to the first The active region 20 in the second row region 21 of the row region 21 (the second horizontal row counted from top to bottom in FIG. 4 ) is rotated clockwise and tilted; relative to the horizontal row extension direction (X direction), The rotational tilt angle θ1 of the active region 20 in the first row of regions 21 ranges from -10 degrees to -45 degrees, and the rotational tilt angle θ2 of the active region in the second row of regions ranges from 10 degrees to 45 degrees. That is to say, relative to the extension direction of the multi-row region 21 , the absolute value of the included angle of the rotation tilt angle of the active region 20 in the multi-row region 21 is an acute angle.

The word line 30 is formed in the semiconductor substrate 1 , and the word line 30 crosses each sub-region 22 , 23 of the multi-row region 21 . The word lines 30 extend along a second direction (for example, the Y direction in FIG. 4 ), and the first direction and the second direction may intersect (for example, be perpendicular to each other).

It can be seen from FIG. 4 that the active area 20 is divided into multiple parts by the isolation structure 50. In the embodiment of the present invention, the active area 20 in the same row is set as a row area 21, so as to demonstrate the advantages of the present invention. . It can be seen that the active region 20 is divided into multiple rows of regions 21 , furthermore, in each row of regions 21 , there are multiple subregions 22 , 23 , and the active region 20 is specifically the structure in each subregion 22 , 23 . It can be understood that the active region 20 is a doped region formed by ion implantation, and may have different ion implantation types according to actual production needs.

In two adjacent rows of regions 21 , the sub-regions 22 and 23 extend in different directions (that is, they are not parallel). Specifically, each sub-region 22, 23 is in the shape of a strip, and in a row of regions 21, each sub-region 22 extends in the same direction (that is, parallel), for example, in the region 21 along the third direction (such as the Z direction in Figure 4) extend. It can be understood that, due to process problems, there may be a certain deviation between each sub-region 22, this deviation will not cause the product to deviate from the core idea of the present invention in the actual process of production, that is, each sub-region 22 is approximately Parallels are also allowed. For example as shown in Figure 4, in the two rows of areas 21 above, the sub-areas 22 in the upper row of areas 21 extend in the same direction, and the sub-areas 23 in the middle row of areas 21 extend in the same direction, but the sub-areas 22 and the sub-areas 23 extend in the same direction. The extending directions are different, so, through the different extending directions of the sub-regions 22 and 23 of the adjacent row of regions 21, the adjustment of the distance between the word lines in the active region 20 can be realized, so that the effective word lines (that is, across the adjacent The pitch difference between the word lines of the sub-regions) becomes smaller.

Further, in each row of regions 21, the spacing between the plurality of sub-regions 22, 23 is the same, that is, the active regions 20 in the same row of regions 21 are arranged in parallel and have the same spacing, thereby achieving uniform distributed.

Further, the angle between the extension directions of the sub-regions 22 and 23 in the adjacent row of regions 21 is θ1+θ2. That is, greater than or equal to 10 degrees and less than or equal to 90 degrees.

In addition, the sub-regions 22, 23 (i.e. active regions) in adjacent rows of regions 21 may be arranged in a staggered manner, that is, the central points of the active regions 20 between adjacent rows of regions 21 are not arranged on the same straight line , but the vector projected on the extending direction of the multi-row region 21 is staggered and shifted in a manner of shifting a word line pitch. On this basis, by adjusting the degree of interleaving, the same spacing between effective word lines can be realized (that is, the word lines 30 have the same spacing), and the word lines can effectively span multiple adjacent active regions 20. Each pitch W3 has no difference or narrows the difference (that is, the length of the word line 30 in the isolation structure 50 is the same or close. Assuming that the uppermost region 21 is the first row as shown in FIG. 4, the vertical direction in FIG. 4 The next row is the second row, the third row..., then the regions 21 of the odd rows can be overlapped after the translation in the vertical direction, and the regions 21 of the even rows can also be overlapped after the translation in the vertical direction, but the odd rows The area 21 of row and the area 21 of even number row can not overlap after passing through the translation of vertical direction, but intersects.In one embodiment, the area 21 of odd number row and the area 21 of even number row are horizontal (that is, vertically vertical) direction) after translation, can be mirror-image symmetry. It can be seen that the active region 20 in the present invention has certain regularity in structure, so the preparation process is simple, and the effect of optimizing the effective word line pitch can also be realized simultaneously.

For the DRAM array layout structure, it also includes a bit line 40, the bit line 40 is formed above the semiconductor substrate 10, and one bit line 40 corresponds to the sub-regions 22, 23 of a row of regions 21 . The bit line 40 extends along a first direction (X direction in FIG. 4 ), for example, the bit line 40 intersects with the word line 30. In one embodiment, the bit line 40 and the word line The word lines 30 are vertical, that is, the extension direction of the bit lines 40 is the same as the extension direction of the multi-row regions 21 .

It can be understood that there is a dielectric layer between the bit line 40 and the word line 30 to realize the isolation between the two, and the bit line 40 includes a bit line contact end, and the bit line contact end passes through Corresponding connections to subregions 22, 23 of a row of regions 21 are realized via the dielectric layer.

In addition, the layout structure of the DRAM array also includes a capacitor. In one embodiment, the capacitor is formed above the bit line 40 . In one embodiment, the capacitor is formed under the word line, more specifically, is formed under the isolation structure 50 . There are many types of capacitance in the prior art, and those skilled in the art can select a suitable capacitance process according to actual needs on the basis of the active region 20 provided in the present invention. Therefore, the capacitance is not shown in FIG. 4 .

In the DRAM array layout structure provided by the present invention, the array region of the semiconductor substrate includes multiple rows of regions, each row of the multi-row regions includes a plurality of active regions, and the active regions are located in adjacent rows of regions. The rotation tilt directions are different, so that the spacing between the word lines across the active area is similar or even the same. Therefore, in the present invention, the direction of the active region in the dynamic random access memory array is changed from the original same-direction inclined configuration with the same extension direction to an interleaved row with different extension directions, so as to ensure the same operation function of the prototype layout configuration. Under the premise, the spacing between the effective word lines is improved, which helps to improve the performance of the device.

Please combine Fig. 4, Fig. 5, Fig. 6 and Fig. 7, Fig. 5 is a schematic cross-sectional view of a dynamic random access memory array along CC' in Fig. 4 according to an embodiment of the present invention; Fig. 6 is a schematic diagram of an embodiment of the present invention A schematic cross-sectional view of the DRAM array along DD' in FIG. 4; FIG. 7 is a schematic cross-sectional view of the DRAM array along EE' in FIG. 4 according to an embodiment of the present invention. With the help of a schematic cross-sectional view of the DRAM array, it is more helpful to understand the layout structure of the DRAM array of the present invention.

It can be seen that the DRAM array in one embodiment of the present invention includes:

a semiconductor substrate 10;

The active region 20 and the isolation structure 50 are located in the array region of the semiconductor substrate 10, the isolation structure 50 isolates adjacent active regions 20, the array region includes multiple rows of regions 21, each row of regions Each row of 21 includes a plurality of active regions 20, and the rotation and tilt directions of the active regions 20 in adjacent row regions 21 are different; and

The word lines 30 are formed in the semiconductor substrate 10 , and each of the word lines 30 crosses each of the active regions 20 of the multi-row regions 21 .

The material of the semiconductor substrate 10 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound or silicon-on-insulator (SOI), etc., or other materials known to those skilled in the art. In the semiconductor substrate 10 Doped regions or other semiconductor structures may also be formed in the doped region, which is not limited in the present invention. The active region 20 and the isolation structure 50 are formed in the semiconductor substrate 10 , and the isolation structure 50 is located at the periphery of the active region 20 for isolating adjacent active regions 20 . It can also be understood that the active region 20 is defined by forming the isolation structure 50 . Wherein, the isolation structure 50 may be a trench isolation structure. The active region 20 is used to form memory cells, such as memory transistors. In the subsequent process, the ion doping process can be performed on the active regions 20 on both sides of the word line formation region to form ion doped regions respectively. For example, the ion doped region corresponding to the left side of the word line formation region can form The source region of the storage transistor and the ion-doped region corresponding to the right side of the word line forming region may constitute the drain region of the storage transistor. Wherein, the ion doping process may be performed before forming the word lines, or may be performed after forming the word lines.

As shown in FIG. 4 , a bit line 40 is further included, and the bit line 40 extends, for example, along a first direction (direction X in FIG. 4 ). The word lines 30 extend, for example, along the second direction (the Y direction in FIG. 4 ). That is, the bit lines 40 and the word lines 30 are intersected. In one embodiment, the bit lines 40 are perpendicular to the word lines 30, that is, the extension direction of the bit lines 40 is in the same direction as the multiple row The direction of extension of the region 21.

Wherein, the first direction (X direction as shown in Figure 4), the second direction (Y direction as shown in Figure 4) and the third direction (Z direction as shown in Figure 4) are all in the same plane and intersect each other, for example, the first direction The first direction and the second direction are perpendicular to each other, and the absolute value of the included angle between the first direction and the third direction may be 10°-45°, for example, 30°.

When the active region 20 in the first row of regions 21 transverse to the word line 30 is rotated and tilted clockwise, the active region 20 in the second row of regions 21 adjacent to the first row of regions 21 The region 20 is rotated and tilted counterclockwise, the rotation tilt angle θ1 of the active region 20 in the first row of regions 21 ranges from 10 degrees to 45 degrees, and the rotation tilt angle θ2 of the active region in the second row of regions ranges from 10 degrees to 45 degrees. -10 degrees to -45 degrees. That is to say, relative to the extension direction of the multi-row region 21 , the absolute value of the included angle of the rotation tilt angle of the active region 20 in the multi-row region 21 is an acute angle.

As can be seen from FIG. 4 , in this CC' section, there is no word line, and the bit line 40 is formed above the semiconductor substrate 10, specifically, formed on the dielectric layer 70, and the dielectric layer 70 It is used to realize the isolation of the bit line 40 and the word line. The material of the dielectric layer 70 can be, for example, common materials such as silicon nitride, silicon oxide, and silicon oxynitride. The bit line 40 is connected to the active region 20 through a bit line contact end 60, for example, the bit line contact end 60 is made of polysilicon or other materials. In one embodiment, the bit line 40 includes a first bit line layer 410 and a second bit line layer 420, as shown in FIG. 420. In another embodiment, the first bit line layer 410 may not have sidewalls, that is, the first bit line layer 410 is formed under the second bit line layer 420 . For example, the material of the first bit line layer 410 can be titanium nitride, the material of the second bit line layer 420 can be tungsten metal, and the first bit line layer 410 can reduce the contact resistance and effectively prevent peeling. Effect.

As shown in FIG. 6 , in the cross-section of DD′, the word line 30 crosses the active region 20 , that is, crosses each of the sub-regions 22 and 23 of the multi-row region 21 . And in one embodiment, the pitch of the word lines 30 between each sub-region is the same, which is denoted as W3. Comparing the situation of W2>W1 shown in FIG. 3 , it can be seen that the pitch of the word lines is significantly improved.

It can also be seen from FIG. 6 that a bit line 40 is formed on the word line 30, and the bit line 40 is isolated from the word line 30 by a dielectric layer 70. This part is consistent with that in FIG. 5 and will not be described again.

As shown in FIG. 7 , in the cross-section of EE′, the word line 30 crosses the active region 20 , that is, crosses each of the sub-regions 22 and 23 of the multi-row region 21 . And in one embodiment, the pitch of the word lines 30 between each sub-region is the same, which is denoted as W3. Comparing the situation of W2>W1 shown in FIG. 3 , it can be seen that the pitch of the word lines is significantly improved.

It can also be seen from FIG. 7 that a bit line 40 is formed on the word line 30, and the bit line 40 is isolated from the word line 30 by a dielectric layer 70. This part is consistent with that in FIG. 5 and will not be described again.

In the DRAM array that the present invention obtains, the pitch of the word line 30 between each subregion can be obtained to be the same, and the principle is: in two adjacent rows of regions 21, the subregions 22, 23 ( That is, the active regions 20) extend in different directions. Specifically, each sub-region 22, 23 is in the shape of a strip, and in a row of regions 21, each sub-region 22 extends in the same direction. It can be understood that due to process problems, there may be a certain deviation between each sub-region 22, This deviation will not cause the product to deviate from the core idea of the present invention in the actual production process. For example as shown in Figure 4, in the two rows of areas 21 above, the sub-areas 22 in the upper row of areas 21 extend in the same direction, and the sub-areas 23 in the middle row of areas 21 extend in the same direction, but the sub-areas 22 and the sub-areas 23 extend in the same direction. The extending directions are different, so, through the different extending directions of the sub-regions 22 and 23 of the adjacent row of regions 21, the adjustment of the distance between the word lines in the active region 20 can be realized, so that the effective word lines (that is, across the adjacent The pitch difference between the word lines of the sub-regions) becomes smaller.

Further, in each row of regions 21, the spacing between the plurality of sub-regions 22, 23 is the same, that is, the active regions 20 in the same row of regions 21 are arranged in parallel and have the same spacing, thereby achieving uniform distributed.

Further, the angle between the extension directions of the sub-regions 22 and 23 in the adjacent row of regions 21 is θ1+θ2. That is, greater than or equal to 10 degrees and less than or equal to 90 degrees.

In addition, the sub-regions 22, 23 (i.e. active regions) in adjacent rows of regions 21 may be arranged in a staggered manner, that is, the central points of the active regions 20 between adjacent rows of regions 21 are not arranged on the same straight line , but the vector projected on the extending direction of the multi-row region 21 is staggered and shifted in a manner of shifting a word line pitch. On this basis, by adjusting the degree of interleaving, the spacing between effective word lines can be the same (that is, the word lines have the same spacing). Assuming that the uppermost area 21 in Figure 4 is the first row, and the vertical direction in Figure 4 is the second row, the third row..., then the areas 21 with odd rows can be translated in the vertical direction After overlapping, the regions 21 of the even rows can also be overlapped after the translation in the vertical direction, but the regions 21 of the odd rows and the regions 21 of the even rows cannot overlap after the translation in the vertical direction, but intersect. In one embodiment, the regions 21 in odd rows and the regions 21 in even rows may be symmetrical in mirror image after translating laterally (ie, vertically). It can be seen that the active region 20 in the present invention has a certain regularity in structure, so the preparation process is simple, and the effect of optimizing the effective word line pitch can also be achieved.

In addition, the DRAM array also includes a capacitor. In one embodiment, the capacitor is formed above the bit line 40 . In one embodiment, the capacitor is formed under the word line, more specifically, is formed under the isolation structure 50 . There are many types of capacitance in the prior art, and those skilled in the art can select a suitable capacitance process according to actual needs on the basis of the active region 20 provided in the present invention. Therefore, the capacitance is not shown in the figure.

In the DRAM array provided by the present invention, the array area of the semiconductor substrate includes multiple rows of regions, each row of the multi-row regions includes a plurality of active regions, and the active regions in adjacent rows of regions The rotation tilt directions are not the same, so that the pitch between the word lines across the active area is similar or even the same. Therefore, in the present invention, the direction of the active region in the dynamic random access memory array is changed from the original same-direction inclined configuration with the same extension direction to an interleaved row with different extension directions, so as to ensure the same operation function of the prototype layout configuration. Under the premise, the spacing between the effective word lines is improved, which helps to improve the performance of the device.

The present invention also provides a method for manufacturing a dynamic random access memory array, including:

Step S11, providing a semiconductor substrate; the material of the semiconductor substrate can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound or silicon-on-insulator (SOI), etc., or other materials known to those skilled in the art, Doping regions or other semiconductor structures may also be formed in the semiconductor substrate, which is not limited in the present invention.

Step S12, forming an active region in the semiconductor substrate, the active region is located in an array region of the semiconductor substrate, the array region includes multiple rows of regions, each row of the multi-row regions is It includes a plurality of active regions, and the rotation and tilt directions of the active regions in adjacent row regions are different. The active region is used to form memory cells, such as memory transistors. In the subsequent process, the ion doping process can be performed on the active regions on both sides of the word line formation region to form ion doped regions respectively. For example, the ion doping region corresponding to the left side of the word line formation region can form the The source region of the storage transistor, the ion-doped region corresponding to the right side of the word line forming region can constitute the drain region of the storage transistor. Wherein, the ion doping process may be performed before forming the word lines, or may be performed after forming the word lines.

Step S13, forming an isolation structure in the semiconductor substrate, the isolation structure is used to isolate adjacent active regions; specifically, the formation of the isolation structure can be formed by common digging and filling, and can be formed through the layout of the present invention , design a special mask plate, after photolithography and other operations, obtain a trench with multiple rows of regions as shown in Figure 4, fill the groove with an insulating material, preferably silicon oxide or silicon nitride, and perform planarization, and then form the required isolation structure, which can isolate adjacent active regions from each other. Preferably, after the insulating layer is filled in the groove, it also includes performing high temperature annealing treatment on the substrate to reduce the pressure of the substrate, and the temperature of the high temperature annealing is preferably 900°C-1100°C.

Step S14 , forming word lines in the semiconductor substrate, and each of the word lines spans one of the active regions in the plurality of rows of regions; for example, the word lines have the same pitch.

Step S15 , forming a bit line on the word line, the extension direction of the bit line is the same as the extension direction of the multi-row regions.

It can be understood that the above-mentioned method for making the DRAM array is only an optional solution, and those skilled in the art can also use any other method to perform dynamic The preparation of the random access memory array, as long as the special design of the active area is achieved, the spacing between the effective word lines is improved under the premise of ensuring the same operation function of the prototype layout configuration, which helps to improve the performance of the device. All are covered by the thought of the present invention.

In summary, in the DRAM array and its layout structure and manufacturing method provided by the present invention, the array region of the semiconductor substrate includes multiple rows of regions, and each row of the multi-row regions includes a plurality of active region, the rotation and inclination directions of the active region in adjacent row regions are different, so that the spacing between the word lines across the active region is similar or even the same. Therefore, in the present invention, the direction of the active region in the dynamic random access memory array is changed from the original same-direction inclined configuration with the same extension direction to an interleaved row with different extension directions, so as to ensure the same operation function of the prototype layout configuration. Under the premise, the spacing between the effective word lines is improved, which helps to improve the performance of the device.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (15)

1. a kind of dynamic random access memory array domain structure, including multiple isolation junctions configured in the semiconductor substrate Structure, active area and wordline, the isolation structure are formed between the active area；

The active area and the isolation structure are located in the array region of the Semiconductor substrate, and the array region includes more Region is arranged, each row in multiple rows of region all includes multiple active areas, and the bearing of trend in multiple rows of region is vertical In the bearing of trend of the wordline, rotation incline direction of the active area in adjacent row region is differs, and each institute State each active area of the wordline across multiple rows of region.

2. dynamic random access memory array domain structure as claimed in claim 1, it is characterised in that the wordline has Identical spacing.

3. dynamic random access memory array domain structure as claimed in claim 1, it is characterised in that relative to described more The bearing of trend in region is arranged, the angle absolute value at the rotation angle of inclination of the active area is acute angle in multiple rows of region.

4. dynamic random access memory array domain structure as claimed in claim 1, it is characterised in that described each active Area is in strip, and the active area between adjacent row region is to be staggered.

5. dynamic random access memory array domain structure as claimed in claim 4, it is characterised in that in identical row region In the active area be arranged in parallel and there is identical spacing.

6. the dynamic random access memory array domain structure as any one of claim 1 to 5, it is characterised in that Also include bit line, be formed at the semiconductor substrate, and the bearing of trend of the bit line is in the same direction in multiple rows of region Bearing of trend.

A kind of 7. dynamic random access memory array, it is characterised in that including：

Semiconductor substrate；

Active area and isolation structure, in the array region of the Semiconductor substrate, the isolation structure isolates adjacent institute Active area is stated, the array region includes multiple rows of region, and each row in multiple rows of region all includes multiple active areas, institute Rotation incline direction of the active area in adjacent row region is stated to differ；And

Wordline, it is formed in the Semiconductor substrate, and each wordline has across described in each one of multiple rows of region Source region.

8. dynamic random access memory array as claimed in claim 7, it is characterised in that the wordline has identical Away from.

9. dynamic random access memory array as claimed in claim 7, it is characterised in that relative to multiple rows of region Bearing of trend, the angle absolute value at the rotation angle of inclination of the active area is acute angle in multiple rows of region.

10. dynamic random access memory array as claimed in claim 7, it is characterised in that each active area is in length Strip, the active area between adjacent row region are to be staggered.

11. dynamic random access memory array as claimed in claim 10, it is characterised in that the institute in identical row region Active area is stated to be arranged in parallel and there is identical spacing.

12. the dynamic random access memory array as any one of claim 7 to 11, it is characterised in that also include Bit line, the semiconductor substrate is formed at, and the bearing of trend of the bit line is in the same direction in the extension side in multiple rows of region To.

A kind of 13. preparation method of dynamic random access memory array, it is characterised in that including：

Semiconductor substrate is provided；

Active area is formed in the Semiconductor substrate, the active area is located in the array region of the Semiconductor substrate, institute Stating array region includes multiple rows of region, and each row in multiple rows of region all includes multiple active areas, and the active area exists Rotation incline direction in adjacent row region is to differ；

Isolation structure is formed in the Semiconductor substrate, the isolation structure is used to isolate adjacent active area；And

Form wordline in the Semiconductor substrate, and each wordline is described active across each one of multiple rows of region Area.

14. the preparation method of dynamic random access memory array as claimed in claim 13, it is characterised in that the wordline With identical spacing.

15. the preparation method of the dynamic random access memory array as described in claim 13 or 14, it is characterised in that also wrap Include and form bit line on the semiconductor substrate, the bearing of trend of the bit line is in the same direction in the bearing of trend in multiple rows of region.