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CN107680951A - A kind of encapsulating structure and its method for packing of multi-chip lamination - Google Patents

A kind of encapsulating structure and its method for packing of multi-chip lamination Download PDF

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Publication number
CN107680951A
CN107680951A CN201710852287.4A CN201710852287A CN107680951A CN 107680951 A CN107680951 A CN 107680951A CN 201710852287 A CN201710852287 A CN 201710852287A CN 107680951 A CN107680951 A CN 107680951A
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CN
China
Prior art keywords
chip
connection sheet
top surface
slide holder
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710852287.4A
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Chinese (zh)
Other versions
CN107680951B (en
Inventor
张晓天
潘华
鲁明朕
鲁军
哈姆扎·依玛兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Inc
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Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Priority to CN201710852287.4A priority Critical patent/CN107680951B/en
Publication of CN107680951A publication Critical patent/CN107680951A/en
Application granted granted Critical
Publication of CN107680951B publication Critical patent/CN107680951B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

本发明涉及一种多芯片叠层的封装结构及其封装方法，仅使用一个联结片设置于HS芯片的源极和LS芯片的漏极上实现其电性连接，导电损耗和开关损耗减小，且热耗散效率则得到增强。IC芯片绝缘地连接在联结片上，从而可以叠放到HS芯片及LS芯片所在平面的上方，以有效减少封装后的器件尺寸。本发明中可以将第一、第二载片台的底面暴露在塑封体外；还有多种方法，进一步将联结片上不连接IC芯片的一部分表面暴露在塑封体外；或者在联结片上进一步连接散热板，并使该散热板的一部分表面暴露在塑封体外；或者将散热板插入到塑封体预留的缺口中以接触联结片帮助散热。

The invention relates to a multi-chip stacked packaging structure and a packaging method thereof. Only one connecting sheet is used to arrange the source of the HS chip and the drain of the LS chip to realize their electrical connection, and the conduction loss and switching loss are reduced. And the heat dissipation efficiency is enhanced. The IC chip is insulated and connected to the bonding sheet, so that it can be stacked above the plane where the HS chip and the LS chip are located, so as to effectively reduce the size of the packaged device. In the present invention, the bottom surfaces of the first and second slide stages can be exposed outside the plastic package; there are also multiple methods to further expose a part of the surface of the connecting sheet that is not connected to the IC chip outside the plastic package; or further connect the cooling plate on the connecting sheet , and expose part of the surface of the cooling plate to the plastic package; or insert the cooling plate into the gap reserved in the plastic package to contact the connecting sheet to help heat dissipation.

Description

一种多芯片叠层的封装结构及其封装方法A multi-chip stacked packaging structure and packaging method thereof

本案是分案申请This case is a divisional application

原案发明名称：一种多芯片叠层的封装结构及其封装方法Title of the original invention: A multi-chip stacked packaging structure and its packaging method

原案申请号：201310617032.1Original application number: 201310617032.1

原案申请日：2013年11月27日Date of original filing: November 27, 2013

技术领域technical field

本发明涉及半导体领域，特别涉及一种多芯片叠层的封装结构及其封装方法。The invention relates to the field of semiconductors, in particular to a multi-chip stacked package structure and a package method thereof.

背景技术Background technique

在DC-DC(直流-直流)转换器中，通常设有两个MOSFET(金属氧化物半导体场效应管)作为切换开关，一个是高端MOSFET(简称HS)，另一个是低端MOSFET(简称LS)。其中，HS的栅极G1及LS的栅极G2均与一控制器(简称IC)连接；HS的漏极D1连接Vin端，源极S1连接LS的漏极D2，而LS的源极S2连接Gnd端，以形成所述的DC-DC转换器。In a DC-DC (direct current-direct current) converter, there are usually two MOSFETs (metal oxide semiconductor field effect transistors) as switching switches, one is a high-side MOSFET (HS for short), and the other is a low-side MOSFET (LS for short). ). Among them, the gate G1 of HS and the gate G2 of LS are connected to a controller (abbreviated as IC); the drain D1 of HS is connected to the Vin terminal, the source S1 is connected to the drain D2 of LS, and the source S2 of LS is connected to Gnd terminal to form the DC-DC converter.

对于DC-DC转换器中的芯片封装结构，是希望将高端MOSFET芯片和低端MOSFET芯片以及控制器芯片封装在同一个塑封体中，以减少外围器件数量，同时提高电源等的利用效率。然而，对于具体的封装结构来说，上述高端MOSFET芯片和低端MOSFET芯片以及控制器芯片只能在引线框架的同一个平面上平行布置，因此封装后的体积大；而且，仅仅通过引线来连接芯片的相应引脚(例如是HS的源极S1与LS的漏极D2之间)，将使得电阻和热阻增加，影响器件成品的性能。For the chip packaging structure in the DC-DC converter, it is hoped that the high-end MOSFET chip, the low-end MOSFET chip and the controller chip will be packaged in the same plastic package, so as to reduce the number of peripheral devices and improve the utilization efficiency of the power supply. However, for a specific packaging structure, the above-mentioned high-end MOSFET chip, low-end MOSFET chip and controller chip can only be arranged in parallel on the same plane of the lead frame, so the volume after packaging is large; moreover, they are only connected by wires The corresponding pins of the chip (for example, between the source S1 of the HS and the drain D2 of the LS) will increase the resistance and thermal resistance, which will affect the performance of the finished device.

发明内容Contents of the invention

本发明的目的是提供一种多芯片叠层的封装结构及其封装方法的多种实施方案，能够通过设置联接片将控制器芯片叠放在高端和低端的MOSFET 芯片所在的平面之上，并通过该联接片实现相应芯片引脚的电路连接，以实现将多个半导体芯片封装在同一个半导体封装中，从而减少直流-直流转换器组装时元件的数量，减小整个半导体封装的尺寸，并有效改善器件的电学性能及散热效果。The purpose of the present invention is to provide a multi-chip stacked packaging structure and various implementations of the packaging method thereof, which can stack the controller chip on the plane where the high-end and low-end MOSFET chips are located by setting the connecting sheet, And the circuit connection of the corresponding chip pins is realized through the connecting piece, so as to realize the packaging of multiple semiconductor chips in the same semiconductor package, thereby reducing the number of components when the DC-DC converter is assembled, and reducing the size of the entire semiconductor package. And effectively improve the electrical performance and heat dissipation effect of the device.

为了达到上述目的，本发明一个技术方案是提供一种多芯片叠层的封装结构，其包含：In order to achieve the above object, a technical solution of the present invention is to provide a multi-chip stacked packaging structure, which includes:

引线框架，其设有相互隔开的第一载片台，第二载片台和若干引脚，所述第二载片台进一步设有相互隔开的第一部分和第二部分；A lead frame, which is provided with a first loading table spaced apart from each other, a second loading table and several pins, and the second loading table is further provided with a first part and a second part spaced apart from each other;

第一芯片，其背面电极向下布置并导电连接在第一载片台上；The first chip, the back electrode of which is arranged downwards and conductively connected to the first chip stage;

第二芯片，通过翻转使其正面电极向下布置并导电连接在第二载片台的第一部分及第二部分上，该第二芯片的其中一些正面电极连接至所述第一部分，其中另一些正面电极连接至所述第二部分；The second chip is flipped so that its front electrodes are arranged downward and conductively connected to the first part and the second part of the second stage, some of the front electrodes of the second chip are connected to the first part, and some of them are connected to the first part. a front electrode connected to the second part;

联结片，其底面同时导电连接至第一芯片向上布置的其中一些正面电极，及第二芯片向上布置的背面电极上；The connecting piece, the bottom surface of which is electrically connected to some of the front electrodes arranged upwards of the first chip and the rear electrodes of the second chip arranged upward;

第三芯片，其背面向下布置并绝缘地连接在所述联结片的顶面上；a third chip, the back side of which is arranged downward and is insulatedly connected to the top surface of the bonding sheet;

塑封体，其封装了依次叠放为多层结构的第三芯片、联结片、第一芯片及第二芯片、引线框架，以及对应连接在芯片电极与芯片电极之间或芯片电极与引脚之间的引线，并且，使引脚与外部器件连接的部分以及第一载片台和第二载片台背面的至少一部分暴露在该塑封体以外。A plastic package, which encapsulates the third chip, the connecting sheet, the first chip and the second chip, the lead frame, and the corresponding connection between the chip electrode and the chip electrode or between the chip electrode and the pin. lead wires, and at least a part of the part where the pin is connected to the external device and the backside of the first and second chip stages is exposed outside the plastic package.

一个具体的应用实例中，所述第一芯片是一个作为高端MOSFET芯片的 HS芯片，其背面设置的漏极导电连接在第一载片台上；In a specific application example, the first chip is an HS chip as a high-end MOSFET chip, and the drain provided on the back thereof is conductively connected to the first loading stage;

所述第二芯片是一个作为低端MOSFET芯片且经过芯片级封装的LS芯片，其正面设置的源极导电连接在第二载片台的第一部分上，正面设置的栅极导电连接在第二载片台的第二部分上；The second chip is an LS chip which is a low-end MOSFET chip and has been packaged in chip scale. on the second part of the slide table;

所述联结片的背面导电连接在所述HS芯片正面的源极及所述LS芯片背面的漏极上，用以实现这两个电极之间的电性连接；The back side of the connecting sheet is conductively connected to the source on the front side of the HS chip and the drain on the back side of the LS chip, so as to realize the electrical connection between these two electrodes;

所述第三芯片是一个作为控制器的IC芯片，其底面绝缘地连接在联结片的顶面上，而其顶面的若干电极分别通过引线对应连接至其他芯片上的相应电极或引线框架上的相应引脚；The third chip is an IC chip as a controller, its bottom surface is insulatedly connected to the top surface of the connecting sheet, and some electrodes on its top surface are respectively connected to corresponding electrodes on other chips or lead frames through lead wires the corresponding pins;

所述HS芯片正面或LS芯片背面上未被联结片遮蔽的若干电极，也分别通过引线对应连接至其他芯片上的相应电极或引线框架上的相应引脚。The electrodes on the front of the HS chip or the back of the LS chip that are not covered by the bonding sheet are also connected to corresponding electrodes on other chips or corresponding pins on the lead frame through leads.

一个实施例中，所述封装结构还在形成塑封体前设置有散热板，所述散热板与所述第三芯片分别连接在联结片的顶面之上，以使该散热板与联结片形成导热接触，进而通过该散热板暴露在塑封体顶面之外的表面实现散热。In one embodiment, the packaging structure is also provided with a heat dissipation plate before forming the plastic package, and the heat dissipation plate and the third chip are respectively connected on the top surface of the coupling sheet, so that the heat dissipation plate and the coupling sheet form a Heat conduction contact, and then realize heat dissipation through the surface of the heat dissipation plate exposed outside the top surface of the plastic package.

另一个实施例中，所述封装结构还在形成塑封体后设置有散热板；所述塑封体的顶面上进一步形成有缺口，所述散热板的底部插入至该缺口以连接至联结片的顶面，并形成该散热板与联结片的导热接触，进而通过所述散热板留在塑封体顶面之外的顶部实现散热。In another embodiment, the packaging structure is also provided with a heat dissipation plate after the plastic package is formed; a gap is further formed on the top surface of the plastic package, and the bottom of the heat dissipation plate is inserted into the gap to connect to the connecting sheet. The top surface of the heat dissipation plate and the heat conduction contact between the heat dissipation plate and the connecting sheet are formed, and the heat dissipation is realized through the top of the heat dissipation plate remaining outside the top surface of the plastic package.

所述联结片设有连接在第一芯片上的高端连接部分，和连接在第二芯片上的低端连接部分；所述联结片的高端连接部分及低端连接部分具有相同或不同的厚度；The coupling sheet is provided with a high-end connection portion connected to the first chip, and a low-end connection portion connected to the second chip; the high-end connection portion and the low-end connection portion of the coupling sheet have the same or different thicknesses;

一个实施例中，所述高端连接部分、第一芯片、第一载片台厚度的和值，与所述低端连接部分、第二芯片、第二载片台厚度的和值相等，从而使连接后联结片的顶面水平以稳固放置第三芯片。In one embodiment, the sum of the thicknesses of the high-end connection portion, the first chip, and the first slide table is equal to the sum of the thicknesses of the low-end connection portion, the second chip, and the second slide table, so that After connecting, the top surface of the bonding sheet is horizontal to place the third chip firmly.

又一个实施例中，所述第三芯片连接于联结片的高端连接部分或低端连接部分中厚度较小的一个部分之上，高端连接部分或低端连接部分中厚度较大的一个部分的顶面暴露在所述塑封体之外实现散热。In yet another embodiment, the third chip is connected to the thinner part of the high-end connection part or the low-end connection part of the bonding sheet, and the thicker part of the high-end connection part or the low-end connection part The top surface is exposed outside the plastic package to realize heat dissipation.

优选的，在所述联结片上形成有若干个局部调整联结片厚度的触点，所述触点是使该联结片顶面向下凹陷形成不穿透的盲孔且同时使该联结片底面向下突出的结构。Preferably, several contact points for locally adjusting the thickness of the connecting sheet are formed on the connecting sheet, and the contact points make the top surface of the connecting sheet concave downward to form an impenetrable blind hole and at the same time make the bottom surface of the connecting sheet downward prominent structure.

所述联结片进一步设有引线连接部分，其导电连接至引线框架所设置的互联引脚上；所述引线连接部分、高端连接部分及低端连接部分，是通过一体成型或通过组装连接来形成所述联结片的；The connecting piece is further provided with a lead connection part, which is conductively connected to the interconnection pin provided on the lead frame; the lead connection part, the high-end connection part and the low-end connection part are formed by integral molding or assembly connection of the connecting piece;

优选的，所述引线连接部分与所述互联引脚上对应设置有防止组装及封装过程中联结片位置改变的锁定机构。Preferably, the connecting part of the lead wire and the interconnecting pin are correspondingly provided with a locking mechanism that prevents the position of the connecting piece from changing during the process of assembling and packaging.

优选的，所述第一芯片与第一载片台之间，所述第二芯片与第二载片台之间，所述联结片与所述第一芯片及第二芯片之间的导电连接，是通过在相互连接的表面之间设置的焊锡或导电的环氧树脂胶实现；Preferably, the conductive connection between the first chip and the first chip stage, between the second chip and the second chip stage, and between the connecting sheet and the first chip and the second chip , is achieved by solder or conductive epoxy glue placed between the interconnected surfaces;

所述第三芯片与所述联结片之间绝缘地连接，是通过在第三芯片背面设置的不导电粘结胶实现。The insulating connection between the third chip and the connecting piece is realized through a non-conductive adhesive disposed on the back of the third chip.

优选的所述联结片是铜片。Preferably, the connecting sheet is a copper sheet.

本发明的另一个技术方案是提供一种多芯片叠层的封装方法，包含：Another technical solution of the present invention is to provide a packaging method for multi-chip stacking, including:

设置引线框架，其设有相互隔开的第一载片台，第二载片台和若干引脚，所述第二载片台进一步设有相互隔开的第一部分和第二部分；A lead frame is provided, which is provided with a first loading table spaced apart from each other, a second loading table and several pins, and the second loading table is further provided with a first part and a second part spaced apart from each other;

将第一芯片的背面电极向下布置并导电连接在第一载片台上；arranging the back electrode of the first chip downward and conductively connecting it to the first loading stage;

将第二芯片翻转以使其正面电极向下布置并导电连接在第二载片台的第一部分及第二部分上，该第二芯片的其中一些正面电极连接至所述第一部分，其中另一些正面电极连接至所述第二部分；Flipping the second chip so that its front electrodes are arranged downward and conductively connected to the first part and the second part of the second stage, some of the front electrodes of the second chip are connected to the first part, and some of the front electrodes are connected to the first part. a front electrode connected to the second part;

将联结片底面同时导电连接至第一芯片向上布置的其中一些正面电极，及第二芯片向上布置的背面电极上；Conductively connecting the bottom surface of the bonding sheet to some of the front electrodes arranged upwards of the first chip and the back electrodes of the second chip arranged upwards at the same time;

将第三芯片的背面向下布置并绝缘地连接在所述联结片的顶面上；arranging the back side of the third chip downward and insulatingly connecting it to the top surface of the bonding sheet;

形成塑封体将依次叠放为多层结构的第三芯片、联结片、第一芯片及第二芯片、引线框架，以及对应连接在芯片电极与芯片电极之间或芯片电极与引脚之间的引线进行封装后，切割所述塑封体形成一个独立的器件；并且，使引脚与外部器件连接的部分以及第一载片台和第二载片台背面的至少一部分暴露在该塑封体以外。Forming the plastic package will be stacked in sequence into the third chip, the bonding sheet, the first chip and the second chip, the lead frame, and the lead wires correspondingly connected between the chip electrodes and the chip electrodes or between the chip electrodes and the pins in a multi-layer structure After encapsulation, the plastic package is cut to form an independent device; and the part where the pins are connected to the external device and at least a part of the back of the first and second chip stages are exposed outside the plastic package.

一个实施例中，所述封装方法还在塑封之前将设置的一散热板也连接至所述联结片的顶面之上，以使该散热板与联结片形成导热接触，进而通过该散热板暴露在塑封体顶面之外的表面实现散热。In one embodiment, the packaging method also connects a heat dissipation plate provided before plastic sealing to the top surface of the coupling sheet, so that the heat dissipation plate forms a thermal contact with the coupling sheet, and then exposes through the heat dissipation plate. Heat dissipation is realized on surfaces other than the top surface of the plastic package.

另一个实施例中，所述封装方法在封装形成的塑封体的顶面上形成有缺口，并将设置的一散热板的底部插入至该缺口以连接至联结片的顶面，并形成该散热板与联结片的导热接触，进而通过所述散热板留在塑封体顶面之外的顶部实现散热。In another embodiment, the packaging method forms a gap on the top surface of the plastic package formed by packaging, and inserts the bottom of a heat dissipation plate into the gap to connect to the top surface of the connecting sheet, and forms the heat dissipation plate. The plate is in thermal contact with the connecting sheet, and then the heat dissipation is realized through the top of the heat dissipation plate remaining outside the top surface of the plastic package.

所述联结片设有连接在第一芯片上的高端连接部分，和连接在第二芯片上的低端连接部分；所述联结片的高端连接部分及低端连接部分具有相同或不同的厚度；The coupling sheet is provided with a high-end connection portion connected to the first chip, and a low-end connection portion connected to the second chip; the high-end connection portion and the low-end connection portion of the coupling sheet have the same or different thicknesses;

两者厚度不同时，所述第三芯片连接于联结片的高端连接部分或低端连接部分中厚度较小的一个部分之上，高端连接部分或低端连接部分中厚度较大的一个部分的顶面暴露在所述塑封体之外实现散热。When the thicknesses of the two are different, the third chip is connected to the thinner part of the high-end connection part or the low-end connection part of the connecting sheet, and the thicker part of the high-end connection part or the low-end connection part The top surface is exposed outside the plastic package to realize heat dissipation.

优选的，所述第一芯片与第一载片台之间，所述第二芯片与第二载片台之间，所述联结片与所述第一芯片及第二芯片之间的导电连接，是通过在相互连接的表面之间设置的焊锡或导电的环氧树脂胶实现；Preferably, the conductive connection between the first chip and the first chip stage, between the second chip and the second chip stage, and between the connecting sheet and the first chip and the second chip , is achieved by solder or conductive epoxy glue placed between the interconnected surfaces;

所述第三芯片与所述联结片之间绝缘地连接，是通过在第三芯片背面设置的不导电粘结胶实现。The insulating connection between the third chip and the connecting piece is realized through a non-conductive adhesive disposed on the back of the third chip.

优选的实施例中，在所述联结片上形成有若干个局部调整联结片厚度的触点，所述触点是通过打孔方式使该联结片顶面向下凹陷形成不穿透的盲孔且同时使该联结片底面向下突出的结构。In a preferred embodiment, several contact points for locally adjusting the thickness of the connecting sheet are formed on the connecting sheet, and the contact points are made by punching holes to make the top surface of the connecting sheet concave downward to form an impenetrable blind hole and at the same time A structure that makes the bottom of the coupling piece protrude downward.

上述任意一个实施例中，所述第一芯片是通过以下过程形成的：在硅片上用以连接其他器件的表面分别形成镀层；进行芯片测试；芯片背面研磨及背面金属化以控制第一芯片的厚度并形成相应的背面电极；切割形成各个独立的第一芯片；之后，再将所述第一芯片背面向下连接至第一载片台。In any one of the above embodiments, the first chip is formed through the following processes: respectively forming a plating layer on the surface of the silicon wafer for connecting other devices; performing chip testing; chip backside grinding and backside metallization to control the first chip and forming corresponding backside electrodes; cutting to form individual first chips; and then connecting the first chips backside down to the first loading stage.

所述第二芯片是通过以下过程形成的：在硅片上用以连接其他器件的表面形成镀层；进行芯片测试及电路图形映射；在硅片正面对应位置植球以形成相应的正面电极；芯片级封装形成封装体；在芯片正面研磨，以使植球的顶部暴露在封装体的顶面外；芯片正面预切割，形成划片槽；芯片背面研磨及背面金属化以控制第二芯片的厚度并形成相应的背面电极；切割形成各个独立的第二芯片；之后，将所述第二芯片翻转后使其正面向下连接至第二载片台。The second chip is formed through the following processes: forming a coating on the surface of the silicon wafer for connecting other devices; performing chip testing and circuit pattern mapping; planting balls at corresponding positions on the front of the silicon wafer to form corresponding front electrodes; Level packaging to form a package; grinding on the front side of the chip so that the top of the ball is exposed outside the top surface of the package; pre-cutting on the front side of the chip to form a scribe groove; grinding and metallization on the back side of the chip to control the thickness of the second chip and forming corresponding backside electrodes; dicing to form individual second chips; afterward, flipping the second chips so that their front faces are down and connected to the second carrier stage.

所述第三芯片是通过以下过程形成的：芯片背面研磨；IC芯片的背面涂覆不导电的粘结胶；切割形成各个独立的第三芯片；之后，将所述第三芯片粘结于已经连接至第一芯片、第二芯片上的联结片的顶面；The third chip is formed through the following processes: grinding the back of the chip; coating the back of the IC chip with a non-conductive adhesive; cutting to form each independent third chip; after that, bonding the third chip to the already existing connected to the top surfaces of the bonding pads on the first chip and the second chip;

在第三芯片、联结片、第一芯片及第二芯片叠放形成多层结构后，还具有以下过程：黏贴胶带，进行固化；在相应的芯片电极与芯片电极之间，及芯片电极与引脚之间分别键接形成引线；形成塑封体；在暴露于塑封体外的位置形成镀层；最终切割形成各个独立的封装器件。After the third chip, the connecting sheet, the first chip and the second chip are stacked to form a multi-layer structure, the following processes are also included: sticking the tape and curing; between the corresponding chip electrodes and the chip electrodes, and between the chip electrodes and the chip electrodes. The leads are respectively bonded to form leads; a plastic package is formed; a plating layer is formed at a position exposed to the outside of the plastic package; finally, individual packaged devices are formed by cutting.

与现有技术相比，本发明所述多芯片叠层的封装结构及其封装方法，其优点在于：Compared with the prior art, the packaging structure and packaging method of the multi-chip stack in the present invention have the following advantages:

相比原先使用多个贴片或键接的引线来连接HS芯片的源极与LS芯片的漏极的结构，本发明中仅使用一个联结片同时焊接或导电黏贴至HS芯片的源极和LS芯片的漏极上，就可以电性连接这两个电极，工艺简单易于实现，导电损耗和开关损耗减小，且热耗散效率则得到增强，器件成品的性能更好。Compared with the original structure of using multiple patches or bonded wires to connect the source of the HS chip and the drain of the LS chip, only one bonding piece is used in the present invention to be soldered or conductively bonded to the source and drain of the HS chip at the same time. On the drain of the LS chip, these two electrodes can be electrically connected, the process is simple and easy to implement, the conduction loss and switching loss are reduced, and the heat dissipation efficiency is enhanced, and the performance of the finished device is better.

相比原先将三个芯片并排放在同一个平面的结构，本发明中的IC芯片绝缘地连接在联结片上，从而可以叠放到HS芯片及LS芯片所在平面的上方，以有效减少封装后的器件尺寸，节约封装材料。Compared with the original structure in which three chips are arranged side by side on the same plane, the IC chip in the present invention is insulatedly connected to the connecting sheet, so that it can be stacked on the plane where the HS chip and the LS chip are located, so as to effectively reduce packaging. Device size, save packaging material.

本发明中可以将第一、第二载片台的底面暴露在塑封体外，便于连接电路板及实现散热。本发明中还有三种方法，进一步在塑封体顶面也形成散热用的表面，即，将联结片上不连接IC芯片的一部分表面暴露在塑封体外；或者在联结片上进一步连接散热板，并使该散热板有一部分表面暴露在塑封体外；或者将散热板插入到塑封体预留的缺口中以接触联结片进行散热。In the present invention, the bottom surfaces of the first and second slide stages can be exposed outside the plastic package, which is convenient for connecting circuit boards and realizing heat dissipation. There are also three methods in the present invention, further forming a surface for heat dissipation on the top surface of the plastic package, that is, exposing a part of the surface of the connecting sheet that is not connected to the IC chip outside the plastic package; or further connecting the cooling plate on the connecting sheet, and making this Part of the surface of the cooling plate is exposed outside the plastic package; or the cooling plate is inserted into the gap reserved in the plastic package to contact the connecting sheet for heat dissipation.

本发明的叠层结构并不会影响在IC芯片与其他芯片之间，HS芯片或LS 芯片与引脚之间键接形成连接用的引线。可以通过设置各部分厚度不同的联结片或通过在联结片上连接的散热板来调整封装结构内不同位置的厚度，以使封装结构一侧的IC芯片、其下方的联结片部分、HS芯片、第一载片台及相应的引线的总体厚度，与封装结构另一侧的联结片的较厚部分或散热板与联结片的组合、LS芯片、第二载片台的总体厚度相匹配。The laminated structure of the present invention does not affect the lead wires used for bonding between the IC chip and other chips, or between the HS chip or the LS chip and pins. The thickness of different positions in the package structure can be adjusted by setting connecting sheets with different thicknesses for each part or by connecting a heat dissipation plate on the connecting sheet, so that the IC chip on one side of the package structure, the connecting sheet part below it, the HS chip, the second The overall thickness of a carrier table and corresponding lead wires matches the overall thickness of the thicker part of the bonding sheet on the other side of the packaging structure or the combination of the heat dissipation plate and the bonding sheet, the LS chip, and the second chip carrier.

本发明中还可以通过在联结片上打孔形成在底面向下突出的多个触点，这在例如键接引线之后的情况下，可以方便快速地实现对联结片局部的厚度调整。In the present invention, a plurality of contacts protruding downward from the bottom surface can also be formed by punching holes on the connecting sheet, which can conveniently and quickly realize local thickness adjustment of the connecting sheet after bonding wires, for example.

本发明中在联结片和与之连接的引线框架引脚上对应设置有锁定机构，以确保组装及封装过程中，联结片的位置不会发生改变。另外，散热片也可以通过设置锁定机构来固定其位置。In the present invention, a locking mechanism is correspondingly provided on the connecting piece and the lead frame pin connected thereto, so as to ensure that the position of the connecting piece will not change during the process of assembling and packaging. In addition, the heat sink can also be fixed in its position by providing a locking mechanism.

附图说明Description of drawings

图1A是本发明在第一实施例中所述芯片封装结构的立体图；FIG. 1A is a perspective view of the chip packaging structure described in the first embodiment of the present invention;

图1B是本发明在第一实施例中所述芯片封装结构的正面透视图；FIG. 1B is a front perspective view of the chip packaging structure in the first embodiment of the present invention;

图1C是本发明在第一实施例中所述芯片封装结构的侧剖面示意图；FIG. 1C is a schematic side sectional view of the chip packaging structure in the first embodiment of the present invention;

图1D和图1E是本发明所述芯片封装结构中一种优选联接片正反面的结构示意图；FIG. 1D and FIG. 1E are structural schematic diagrams of the front and back sides of a preferred connecting sheet in the chip packaging structure of the present invention;

图2A～图2G是本发明在第一实施例中与所述芯片封装方法各步骤相对应的结构示意图；2A to 2G are structural schematic diagrams corresponding to each step of the chip packaging method in the first embodiment of the present invention;

图3是本发明在第一实施例中所述芯片封装方法的流程图；Fig. 3 is a flowchart of the chip packaging method described in the first embodiment of the present invention;

图4A～图4G是本发明在第二实施例中与所述芯片封装方法各步骤相对应的结构示意图；4A to 4G are structural schematic diagrams corresponding to each step of the chip packaging method in the second embodiment of the present invention;

图5是本发明在第二实施例中所述芯片封装方法的流程图；Fig. 5 is a flow chart of the chip packaging method described in the second embodiment of the present invention;

图6A～图6H是本发明在第三实施例中与所述芯片封装方法各步骤相对应的结构示意图；6A to 6H are structural schematic diagrams corresponding to each step of the chip packaging method in the third embodiment of the present invention;

图7是本发明在第三实施例中所述芯片封装方法的流程图；Fig. 7 is a flow chart of the chip packaging method described in the third embodiment of the present invention;

图8A～图8F是本发明在第四实施例中与所述芯片封装方法各步骤相对应的结构示意图；8A to 8F are structural schematic diagrams corresponding to each step of the chip packaging method in the fourth embodiment of the present invention;

图9是本发明在第三实施例中所述芯片封装方法的流程图。FIG. 9 is a flow chart of the chip packaging method in the third embodiment of the present invention.

具体实施方式Detailed ways

以下将结合附图，说明本发明的多个优选的实施例。Several preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

实施例1Example 1

配合参见图1A～图1C所示，本发明中由2个相同类型的MOSFET芯片 (2个N型或2个P型)，分别作为高端MOSFET(简称为HS芯片20)和低端MOSFET芯片(简称为LS芯片30)。通过一个联结片40将一个控制器芯片(简称为IC芯片50)叠放在这两个MOSFET芯片所在的同一个平面上，并且，将IC芯片50与LS芯片30和HS芯片20的相应电极及引脚14连接后封装在同一个塑封体100内，以形成一个直流-直流转换器。1A to 1C for cooperation, in the present invention, 2 MOSFET chips of the same type (2 N-type or 2 P-type) are respectively used as a high-end MOSFET (abbreviated as HS chip 20) and a low-end MOSFET chip ( It is referred to as LS chip 30 for short). A controller chip (abbreviated as IC chip 50) is stacked on the same plane where the two MOSFET chips are located by a bonding sheet 40, and the IC chip 50 is connected to the corresponding electrodes and electrodes of the LS chip 30 and the HS chip 20. After the pins 14 are connected, they are packaged in the same plastic package 100 to form a DC-DC converter.

所述的HS芯片20和LS芯片30，各自在芯片正面设有源极和栅极，而在芯片背面设有漏极；其中，HS芯片20的栅极G1及LS芯片30的栅极G2 均与IC芯片50上的控制极连接；HS芯片20的漏极D1连接Vin端，源极 S1连接LS芯片30的漏极D2，而LS芯片30的源极S2连接Gnd端，形成所述直流-直流转换器。在直流-直流转换器的Vin-Gnd两端之间还可以设置电容、电感等其他的元器件。The HS chip 20 and the LS chip 30 are respectively provided with a source and a gate on the front of the chip, and a drain is provided on the back of the chip; wherein, the gate G1 of the HS chip 20 and the gate G2 of the LS chip 30 are both It is connected with the control pole on the IC chip 50; the drain D1 of the HS chip 20 is connected to the Vin end, the source S1 is connected to the drain D2 of the LS chip 30, and the source S2 of the LS chip 30 is connected to the Gnd end to form the DC- DC converter. Other components such as capacitors and inductors can also be arranged between the two ends of Vin-Gnd of the DC-DC converter.

本实施例提供的封装结构中，设有引线框架10(参见图2A所示)，该引线框架10在同一平面上设置有相互分离的第一载片台11和第二载片台，其中，第二载片台还设置有相互分离的第一部分12和第二部分13。所述引线框架10还设置有多个相互分离的引脚14，其中包含：低端源极引脚、低端栅极引脚、高端源极引脚、高端栅极引脚，以及互联引脚15等。In the packaging structure provided in this embodiment, a lead frame 10 (see FIG. 2A ) is provided, and the lead frame 10 is provided with a first wafer stage 11 and a second wafer stage separated from each other on the same plane, wherein, The second stage is also provided with a first part 12 and a second part 13 which are separated from each other. The lead frame 10 is also provided with a plurality of mutually separated pins 14, which include: low-end source pins, low-end gate pins, high-end source pins, high-end gate pins, and interconnection pins 15 etc.

本实施例中的这些引脚14分布在第一载片台11和第二载片台的周边，其中，高端漏极引脚是从第一载片台11上延伸设置的，低端源极引脚是从第二载片台的第一部分12上延伸设置的，低端栅极引脚是从第二载片台的第二部分13上延伸设置的；其他若干引脚14则都是与第一载片台11或第二载片台相互隔开的。These pins 14 in this embodiment are distributed on the periphery of the first loading stage 11 and the second loading stage, wherein, the high-end drain pin is extended from the first loading stage 11, and the low-end source The pins are extended from the first part 12 of the second stage, and the low-end gate pins are extended from the second part 13 of the second stage; other pins 14 are all connected with The first loading platform 11 or the second loading platform are separated from each other.

所述HS芯片20放置在第一载片台11上，在该HS芯片20的背面与第一载片台11的顶面之间设有焊锡或导电的环氧树脂粘结胶91或其他的导电连接材料，以使HS芯片20背面的漏极S1与第一载片台11形成电性连接，并可以通过高端漏极引脚与外部器件连通。The HS chip 20 is placed on the first loading stage 11, and solder or conductive epoxy resin adhesive 91 or other adhesives are provided between the back surface of the HS chip 20 and the top surface of the first loading stage 11. Conductive connection material, so that the drain S1 on the back of the HS chip 20 is electrically connected to the first loading stage 11, and can communicate with external devices through the high-side drain pin.

芯片级封装的LS芯片30，在翻转后放置于第二载片台上，在该LS芯片30向下的正面与第二载片台的第一部分12及第二部分13之间设有焊锡或导电的环氧树脂粘结胶91等，以使LS芯片30正面的源极与第二载片台的第一部分12电性连接，并可以通过低端源极引脚与外部器件连通；同时， LS芯片30正面的栅极G2与第二载片台的第二部分13电性连接，并可以通过低端栅极引脚与外部器件连通。The chip-scale packaged LS chip 30 is placed on the second carrier stage after being turned over, and solder or solder is provided between the downward surface of the LS chip 30 and the first part 12 and the second part 13 of the second carrier stage. Conductive epoxy resin bonding glue 91 etc., so that the source on the front side of the LS chip 30 is electrically connected to the first part 12 of the second carrier, and can be communicated with external devices through the low-end source pin; at the same time, The gate G2 on the front side of the LS chip 30 is electrically connected to the second part 13 of the second stage, and can communicate with external devices through the low-end gate pin.

本实施例提供的封装结构中特别设置的联结片40是由导电材料制成，例如是一种铜片。该联结片40设有高端连接部分41和低端连接部分42，分别通过焊锡或导电的环氧树脂粘结胶91等，粘接设置在HS芯片20及LS芯片 30向上的表面之上，从而使HS芯片20正面的源极S1及LS芯片30背面的漏极D2(两者均为向上布置)分别与联结片40底面的相应位置电性连接，并实现HS芯片20的源极S1与LS芯片30的漏极D2之间的电性连接。The bonding sheet 40 specially provided in the package structure provided by this embodiment is made of conductive material, such as a copper sheet. The connecting sheet 40 is provided with a high-end connecting portion 41 and a low-end connecting portion 42, which are respectively bonded on the upward surfaces of the HS chip 20 and the LS chip 30 through solder or conductive epoxy resin adhesive 91, so that The source S1 on the front side of the HS chip 20 and the drain D2 on the back side of the LS chip 30 (both are arranged upwards) are electrically connected to the corresponding positions on the bottom surface of the connecting sheet 40 respectively, and the source S1 and LS of the HS chip 20 are realized. The electrical connection between the drain D2 of the chip 30 .

所述联结片40的厚度设计，应当满足使联结片40的高端连接部分41 与其下方HS芯片20等相加的厚度，等于联结片40的低端连接部分42与其下方LS芯片30等相加的厚度，来保证粘接后整个联结片40的顶面是与HS 芯片20及LS芯片30所在的平面相平行的，以便于后续稳固放置IC芯片50。例如，优选的实施例中是使第一载片台11和第二载片台的厚度一致；HS芯片20和LS芯片30厚度一致，连接在引线框架10后两个芯片的顶面水平；并且，使联结片40上对应连接HS芯片20及LS芯片30的位置的厚度一致，从而保证其叠放在两个芯片上后的顶面也是水平的。The thickness design of the connecting piece 40 should meet the thickness of the high-end connecting portion 41 of the connecting piece 40 and the HS chip 20 below it, which is equal to the thickness of the low-end connecting portion 42 of the connecting piece 40 and the LS chip 30 below it. Thickness, to ensure that the top surface of the entire bonding sheet 40 is parallel to the plane where the HS chip 20 and the LS chip 30 are located after bonding, so as to facilitate the subsequent stable placement of the IC chip 50. For example, in a preferred embodiment, the thicknesses of the first loading table 11 and the second loading table are consistent; the thickness of the HS chip 20 and the LS chip 30 are consistent, and they are connected to the top surface level of the two chips after the lead frame 10; and , make the thickness of the connecting sheet 40 corresponding to the position connecting the HS chip 20 and the LS chip 30 consistent, so as to ensure that the top surface after it is stacked on the two chips is also horizontal.

配合参见图1D～图1E所示，例如，可以在联结片40的底部分别形成能够调整其高端连接部分41及低端连接部分42的厚度的凸起块411、421。并且，在一个优选的实施例中，在凸起块411、421的位置还可以形成有多个向下突出的触点45，来进一步调整联结片40各部分的厚度。这些触点45的形成，是通过在联结片40上打孔，从而在联结片40的顶面形成不穿透的凹坑，并在联结片40的底部形成所述的触点45。一个联结片40上，不同位置触点45的打孔深度可以相同或不相同，根据具体的厚度调节情况决定。Referring to FIG. 1D to FIG. 1E , for example, protruding blocks 411 and 421 capable of adjusting the thicknesses of the high-end connecting portion 41 and the low-end connecting portion 42 can be formed on the bottom of the connecting piece 40 . Moreover, in a preferred embodiment, a plurality of downwardly protruding contacts 45 may be formed at the positions of the protruding blocks 411 , 421 to further adjust the thickness of each part of the connecting piece 40 . These contacts 45 are formed by punching holes in the connecting sheet 40 so as to form impermeable recesses on the top surface of the connecting sheet 40 and form said contacts 45 at the bottom of the connecting sheet 40 . On one coupling sheet 40, the perforation depths of the contacts 45 at different positions may be the same or different, depending on the specific thickness adjustment conditions.

同时，该联结片40还设置有引脚连接部分43，用来与位于引线框架10 周边的互联引脚15进行电性连接，以使HS芯片20的源极S1及LS芯片30 的漏极D2及联结片40能够进一步通过该互联引脚15与外部器件连通。所述联结片40的引脚连接部分43，其向下突出部分431的厚度加上与该突出部分431连接的互联引脚15的厚度，也应当满足上述使粘接后联结片40的顶面与两个MOSFET芯片相平行的设计目的。Simultaneously, this connecting piece 40 is also provided with pin connection part 43, is used for being in electrical connection with the interconnection pin 15 that is positioned at lead frame 10 periphery, makes the source S1 of HS chip 20 and the drain D2 of LS chip 30 And the connection piece 40 can further communicate with external devices through the interconnection pin 15 . The pin connection portion 43 of the connecting sheet 40, the thickness of its downward protruding portion 431 plus the thickness of the interconnection pin 15 connected to the protruding portion 431, should also meet the above-mentioned requirement that the top surface of the connecting sheet 40 after bonding Parallel design purpose with two MOSFET chips.

在一个优选的实施例中，在引线框架10的互联引脚15上及所述联结片 40的引脚连接部分43还对应设置有锁定机构。在图1A的示例结构中，互联引脚15上的锁定机构是开设的若干个定位孔81，而联结片40的锁定机构则是在其底部的对应位置的定位件82，图示的定位件82相当于一种从联结片 40底面向下延伸或弯折的结构，能够对应插入到这些定位孔81中以实现联结片40位置的固定，以确保在组装及封装过程联结片40不会发生移动。并且，在设置有上述锁定机构时，联结片40上定位件82的厚度，是大于引脚连接部分43的厚度，以确保该定位件82能够对应插入到互联引脚15的定位孔81中。本发明并不限制在其他的实施结构中互换定位孔81及定位件82 的位置或使用其他结构的锁定机构。In a preferred embodiment, a locking mechanism is correspondingly provided on the interconnection pins 15 of the lead frame 10 and the pin connection portion 43 of the connecting sheet 40. In the example structure of Fig. 1A, the locking mechanism on the interconnection pin 15 is a plurality of positioning holes 81 opened, and the locking mechanism of the connecting piece 40 is a positioning piece 82 at the corresponding position at its bottom, the positioning piece shown in the figure 82 is equivalent to a structure extending or bending downwards from the bottom surface of the connecting piece 40, which can be inserted into these positioning holes 81 to realize the fixing of the position of the connecting piece 40, so as to ensure that the connecting piece 40 will not be damaged during the assembly and packaging process. move. Moreover, when the above-mentioned locking mechanism is provided, the thickness of the positioning piece 82 on the connecting piece 40 is greater than the thickness of the pin connection portion 43 to ensure that the positioning piece 82 can be inserted into the positioning hole 81 of the interconnection pin 15 correspondingly. The present invention is not limited to exchanging the positions of the positioning hole 81 and the positioning member 82 or using other locking mechanisms in other implementation structures.

在图1A的示例结构中，联结片40的表面形状及其尺寸设计，使得该联结片40的高端连接部分41基本覆盖了其下方LS芯片30顶部的绝大部分面积，但低端连接部分42则没有将HS芯片20的顶部完全覆盖。因而，所述 HS芯片20正面未被联结片40遮蔽的源极S1和栅极G1，可以分别通过若干个键接的引线60，直接连接至引线框架10的引脚14或其他芯片(例如是 IC芯片50)的电极上；或者，将引线框架10的引脚14作为中转，设置多段分别键接的引线60，以间接连接至其他芯片(例如是IC芯片50)上的相应电极。本发明也不限制在其他的实施例中，使用其他结构的联结片40，例如，是不完全覆盖LS芯片30的结构；或者，联结片40不是一体成型的，而是由多个小的联结部件相互连接或组装形成的等等。In the exemplary structure of Fig. 1A, the surface shape and size design of the connecting sheet 40 make the high-end connecting portion 41 of the connecting sheet 40 basically cover most of the area at the top of the LS chip 30 below it, but the low-end connecting portion 42 Then the top of the HS chip 20 is not completely covered. Thus, the source S1 and grid G1 on the front side of the HS chip 20 that are not shielded by the bonding sheet 40 can be directly connected to the pins 14 of the lead frame 10 or other chips (such as Or, using the pin 14 of the lead frame 10 as a relay, a plurality of sections of lead wires 60 bonded respectively are provided to indirectly connect to corresponding electrodes on other chips (such as the IC chip 50). The present invention is not limited to other embodiments, using other structures of the connecting piece 40, for example, a structure that does not completely cover the LS chip 30; Parts are connected or assembled to form, etc.

本发明所述的IC芯片50，通过不导电的粘结胶92或其他绝缘的固定连接方式，粘接设置在该联结片40的顶面之上，以使IC芯片50、联结片40、 HS芯片20与LS芯片30形成为一个自上而下叠放的多层结构，同时该IC 芯片50与HS芯片20和LS芯片30的电极之间不会通过联结片40实现电性连接。The IC chip 50 of the present invention is bonded and arranged on the top surface of the connecting sheet 40 through non-conductive adhesive glue 92 or other insulating fixed connection methods, so that the IC chip 50, the connecting sheet 40, the HS The chip 20 and the LS chip 30 are formed into a multilayer structure stacked from top to bottom, and the electrodes of the IC chip 50 and the HS chip 20 and the LS chip 30 are not electrically connected through the bonding sheet 40 .

在图1A的示例结构中，所述IC芯片50是位于联结片40的高端连接部分41之上，即对应HS芯片20上方的位置；而在其他未显示出的示例中， IC芯片50可以是位于联结片40顶面的其他位置。所述IC芯片50上的若干电极，能够分别通过键接的引线60，电性连接至引线框架10周边的相应引脚14上或其他芯片(例如是HS芯片20)的相应电极上。In the exemplary structure of FIG. 1A, the IC chip 50 is located above the high-end connection portion 41 of the connecting sheet 40, which corresponds to the position above the HS chip 20; and in other not shown examples, the IC chip 50 may be Other positions on the top surface of the coupling sheet 40. Several electrodes on the IC chip 50 can be electrically connected to corresponding pins 14 around the lead frame 10 or corresponding electrodes of other chips (such as the HS chip 20 ) through bonded leads 60 .

本实施例的封装结构中，还包含塑封体100，将上述叠设的IC芯片50、联结片40、HS芯片20与LS芯片30及对应电极上连接的引线60都封装起来形成一个器件，而将各个引脚14与外部器件连接的部分暴露出来，并且使引线框架10上第一载片台11和第二载片台(例如是其第一部分12)的底面暴露在塑封体100之外，用以连接电路板或帮助散热。In the packaging structure of the present embodiment, a plastic package body 100 is also included, and the IC chip 50, the bonding sheet 40, the HS chip 20, the LS chip 30 and the lead wires 60 connected to the corresponding electrodes are all packaged to form a device, and Exposing the part where each pin 14 is connected to the external device, and exposing the bottom surface of the first carrier stage 11 and the second carrier stage (for example, the first part 12 thereof) on the lead frame 10 outside the plastic package 100, Used to connect to the circuit board or to help dissipate heat.

以下请配合参见图2A～图2G所示的结构，及图3所示的流程，介绍本实施例所述芯片的封装方法：Please refer to the structures shown in FIGS. 2A to 2G and the process shown in FIG. 3 below to introduce the packaging method of the chip described in this embodiment:

即，见图2A，设置一个引线框架10，包含相互隔开的第一载片台11，设有第一部分12和第二部分13的第二载片台，以及多个引脚14。That is, as shown in FIG. 2A , a lead frame 10 is provided, including a first stage 11 spaced apart from each other, a second stage with a first part 12 and a second part 13 , and a plurality of pins 14 .

见图2B，设置一个MOSFET芯片为HS芯片20，将其固定连接在第一载片台11上并使HS芯片20背面的漏极D1与第一载片台11形成电性连接。Referring to FIG. 2B , a MOSFET chip is set as the HS chip 20 , which is fixedly connected to the first stage 11 and the drain D1 on the back of the HS chip 20 is electrically connected to the first stage 11 .

见图2C，设置另一个芯片级封装的MOSFET芯片为LS芯片30，将其翻转后固定连接在第二载片台上并使LS芯片30正面的源极S1与第二载片台的第一部分12形成电性连接，且LS芯片30正面的栅极G2与第二载片台的第二部分13形成电性连接。See Fig. 2C, another MOSFET chip of chip-scale packaging is set as LS chip 30, it is turned over and fixedly connected on the second carrier and the source S1 on the front side of LS chip 30 is connected to the first part of the second carrier. 12 to form an electrical connection, and the gate G2 on the front side of the LS chip 30 is electrically connected to the second portion 13 of the second stage.

见图2D，设置一个联结片40，在其背面分别通过设置焊锡或导电的环氧树脂粘结胶91等类似方式，将该联结片40的高端连接部分41连接至HS 芯片20顶面，低端连接部分42连接至LS芯片30顶面，引脚连接部分43 连接至引线框架10的互联引脚15上，使得HS芯片20正面的源极S1、LS 芯片30向上的背面漏极D2与互联引脚15之间相互形成电性连接。As shown in FIG. 2D , a connecting piece 40 is set, and the high-end connection part 41 of the connecting piece 40 is connected to the top surface of the HS chip 20 by setting solder or conductive epoxy resin adhesive 91 and the like on the back of the connecting piece 40. The terminal connection part 42 is connected to the top surface of the LS chip 30, and the pin connection part 43 is connected to the interconnection pin 15 of the lead frame 10, so that the source S1 on the front side of the HS chip 20 and the upward back drain D2 of the LS chip 30 are connected to the interconnection pin 15. The pins 15 are electrically connected to each other.

见图2E，将IC芯片50通过不导电的粘结胶92，固定设置在联结片40 的顶面上，形成IC芯片50、联结片40、HS芯片20与LS芯片30叠放的多层结构。并且，在HS芯片20正面未被联结片40遮蔽的栅极G1和源极S1，IC芯片50的若干电极，及引线框架10的若干引脚14之间相互通过键接的引线60对应连接。2E, the IC chip 50 is fixedly arranged on the top surface of the connecting sheet 40 through a non-conductive adhesive 92 to form a multilayer structure in which the IC chip 50, the connecting sheet 40, the HS chip 20 and the LS chip 30 are stacked. . Moreover, the gate G1 and the source S1 not covered by the bonding sheet 40 on the front of the HS chip 20, the electrodes of the IC chip 50, and the pins 14 of the lead frame 10 are connected to each other through corresponding bonding wires 60 .

见图2F及图2G正反两面所示，设置塑封体100将IC芯片50、联结片 40、HS芯片20与LS芯片30叠放的多层结构及引线60等都封装起来，而使各个引脚14用以连接外部器件的位置及第一载片台11和第二载片台的背面暴露出来。2F and 2G, the front and back sides of FIG. 2G show that the plastic package 100 is set to package the multi-layer structure of the IC chip 50, the connecting sheet 40, the HS chip 20 and the LS chip 30, and the leads 60, so that each lead The positions of the pins 14 for connecting external devices and the backs of the first slide stage 11 and the second slide stage are exposed.

再参见图3所示，当设置一个LS芯片30时，通过以下步骤实现：在 LS芯片30上用于后续连贴固定的表面形成有镀层，例如是Ni/Au的镀层；芯片测试及电路图形映射；在芯片正面对应位置进行植球以形成相应的电极。芯片级封装；在芯片正面研磨，以使植球的顶部暴露在封装体的顶面外；例如，可以在研磨后使植球暴露的顶面与封装体的顶面齐平，等等。芯片正面预切割，形成划片槽。芯片背面研磨及背面金属化形成相应电极；例如一个具体实例中经过背面研磨及背面金属化后的厚度为6mil，其中硅片的厚度为 3mil，硅片上方的封装体厚度为3mil。之后，切割形成各个独立的LS芯片 30，再翻转使其以正面朝下且背面朝上的方式导电连接至第二载片台上。Referring again to shown in Figure 3, when an LS chip 30 is set, it is realized by the following steps: on the LS chip 30, a coating is formed on the surface of the LS chip 30 for subsequent bonding and fixing, such as a coating of Ni/Au; chip testing and circuit pattern Mapping; plant balls at the corresponding positions on the front of the chip to form corresponding electrodes. Chip-scale packaging; grinding on the front side of the chip so that the top of the balls is exposed outside the top surface of the package; eg, the exposed top surface of the balls can be ground flush with the top surface of the package, etc. The front side of the chip is pre-cut to form a scribe groove. Chip backside grinding and backside metallization form corresponding electrodes; for example, in a specific example, the thickness after backside grinding and backside metallization is 6mil, in which the thickness of the silicon chip is 3mil, and the thickness of the package above the silicon chip is 3mil. Afterwards, each independent LS chip 30 is formed by dicing, and then flipped over so that it is conductively connected to the second loading stage with the front side facing down and the back side facing up.

而在设置一个HS芯片20时，通过以下步骤实现：在HS芯片20上用于后续连贴固定的表面形成有镀层，例如是Ni/Pd/Au的镀层；芯片测试；芯片背面研磨及背面金属化，例如以上述的具体实例说明，使背面研磨及背面金属化后HS芯片20和LS芯片30的厚度一致，为6mil。切割形成各个独立的HS芯片20，使其正面朝上，背面朝下连接至第一载片台11。When an HS chip 20 is set, it is realized through the following steps: on the HS chip 20, a coating is formed on the surface of the HS chip 20 for subsequent attachment and fixation, such as a coating of Ni/Pd/Au; chip testing; chip back grinding and back metal For example, using the above-mentioned specific example to illustrate, the thickness of the HS chip 20 and the LS chip 30 after back grinding and back metallization are consistent, which is 6 mil. Cutting forms each independent HS chip 20 , making the front face up and the back face down connected to the first loading stage 11 .

而在设置一个IC芯片50时，通过以下步骤实现：IC芯片50背面研磨，例如为6mil。在IC芯片50的背面涂覆不导电的粘结胶92。切割形成各个独立的IC芯片50，并置于清洗后的联结片40顶面上。When setting an IC chip 50, it is realized through the following steps: the backside of the IC chip 50 is ground, for example, to 6mil. A non-conductive adhesive 92 is coated on the back of the IC chip 50 . Separate IC chips 50 are formed by cutting and placed on the top surface of the cleaned bonding sheet 40 .

则IC芯片50、联结片40、HS芯片20与LS芯片30叠放连接之后，具体设有黏贴胶带，进行固化；在相应芯片的电极及引脚14之间键接形成连接的引线60；形成塑封体100；在暴露的位置形成镀层；通过锯切或冲压等类似方式，切割形成各个独立的封装器件的若干步骤。Then after the IC chip 50, the connecting piece 40, the HS chip 20 and the LS chip 30 are stacked and connected, an adhesive tape is specifically provided for curing; the lead wire 60 is bonded between the electrodes and the pins 14 of the corresponding chips to form a connection; Forming the plastic package 100 ; forming a plating layer at the exposed position; cutting and forming individual packaged devices by sawing or punching or similar methods.

实施例2Example 2

图4A～图4G示出了本实施例中芯片封装各个步骤中的结构示意，图5 示出了本实施例中封装方法的流程。其中，本实施例的结构简述如下，即，设置一个引线框架10(图4A)，包含第一载片台11，用于固定连接HS芯片 20并与其背面漏极D1形成电性连接(图4B)；还包含第二载片台，设有第一部分12和第二部分13，用于固定连接翻转的封装LS芯片30并分别与其正面的源极S2和栅极G2形成电性连接(图4C)。将一个联结片40导电连接在HS芯片20及LS芯片30上，以使该联结片40的高端连接部分41电性连接至HS芯片20正面的源极S1，而该联结片40的低端连接部分42电性连接至LS芯片30LS芯片30向上的背面漏极D2，并进而通过该联结片40 的引脚连接部分43电性连接至引线框架10的互联引脚15(图4D)；4A to 4G show the structural diagrams of each step of chip packaging in this embodiment, and FIG. 5 shows the flow of the packaging method in this embodiment. Wherein, the structure of the present embodiment is briefly described as follows, that is, a lead frame 10 (FIG. 4A) is set, including a first loading stage 11, which is used to fixedly connect the HS chip 20 and form an electrical connection with the drain D1 on its back side (FIG. 4B); It also includes a second chip stage, which is provided with a first part 12 and a second part 13, which are used to fix and connect the flipped package LS chip 30 and form an electrical connection with the source S2 and the grid G2 on the front side respectively (Fig. 4C). A connecting piece 40 is conductively connected on the HS chip 20 and the LS chip 30, so that the high-side connection portion 41 of the connecting piece 40 is electrically connected to the source S1 on the front side of the HS chip 20, and the low-end of the connecting piece 40 is connected to The portion 42 is electrically connected to the upper backside drain D2 of the LS chip 30, and then electrically connected to the interconnection pin 15 of the lead frame 10 through the pin connection portion 43 of the bonding sheet 40 (FIG. 4D);

与实施例1中的不同之处在于，本实施例中是在联结片40上同时设置了 IC芯片50和一个散热板71，例如是导热性能良好的铜板或类似材料制成所述散热板71。例如，是将该散热板71设置在联结片40的低端连接部分42 的顶面上形成良好的导热接触(图4E)，而将IC芯片50绝缘地粘接在联结片40的高端连接部分41(图4F)。则，形成IC芯片50与散热板71，联结片40，HS芯片20及LS芯片30叠放的多层结构，并且，散热板71的厚度设计，应当与IC芯片50与HS芯片20或引脚14之间连接若干引线60后的厚度大致相当。将上述多层结构封装在塑封体100中，而使各个引脚14外连的部分，第一载片台11和第二载片台的大部分底面分别暴露在塑封体100 的底面之外；同时使散热板71的顶面暴露在塑封体100的顶面之外进一步帮助散热。The difference from Embodiment 1 is that in this embodiment, the IC chip 50 and a heat dissipation plate 71 are arranged on the connecting sheet 40 at the same time, for example, the heat dissipation plate 71 is made of a copper plate with good thermal conductivity or similar materials. . For example, the cooling plate 71 is arranged on the top surface of the low-end connecting portion 42 of the bonding sheet 40 to form a good thermal contact ( FIG. 4E ), and the IC chip 50 is bonded on the high-end connecting portion of the bonding sheet 40 in an insulating manner. 41 (Fig. 4F). Then, form IC chip 50 and radiator plate 71, the multi-layer structure that connecting plate 40, HS chip 20 and LS chip 30 are stacked, and, the thickness design of radiator plate 71 should be consistent with IC chip 50 and HS chip 20 or pin 14 are roughly equal in thickness after connecting several lead wires 60 . Encapsulate the above-mentioned multi-layer structure in the plastic package 100, so that the parts connected to the pins 14, most of the bottom surfaces of the first slide table 11 and the second slide table are respectively exposed outside the bottom surface of the plastic package 100; At the same time, the top surface of the heat dissipation plate 71 is exposed outside the top surface of the plastic package 100 to further help heat dissipation.

配合参见图5所示，本实施例中设置引线框架10、HS芯片20、LS芯片 30及IC芯片50的过程与实施例1中基本一致，不同点主要是需要设置散热板71，并在联结片40粘接在HS芯片20和LS芯片30上以后，到清洗联结片40以设置IC芯片50之前，需要增加将散热板71连接至联结片40顶面的步骤。Referring to Fig. 5, the process of setting lead frame 10, HS chip 20, LS chip 30 and IC chip 50 in this embodiment is basically the same as that in Embodiment 1. After the sheet 40 is bonded on the HS chip 20 and the LS chip 30 , until the bonding sheet 40 is cleaned to install the IC chip 50 , it is necessary to add a step of attaching the heat sink 71 to the top surface of the bonding sheet 40 .

实施例3Example 3

图6A～图6G示出了本实施例中芯片封装各个步骤中的结构示意，图7 示出了本实施例中封装方法的流程。其中，本实施例的结构简述如下，即，设置一个引线框架10(图6A)，包含第一载片台11，用于固定连接HS芯片 20并与其背面漏极D1形成电性连接(图6B)；还包含第二载片台，设有第一部分12和第二部分13，用于固定连接翻转的封装LS芯片30并分别与其正面的源极S2和栅极G2形成电性连接(图6C)。将一个联结片40导电连接在HS芯片20及LS芯片30上，以使该联结片40的高端连接部分41电性连接至HS芯片20正面的源极S1，而该联结片40的低端连接部分42电性连接至LS芯片30LS芯片30向上的背面漏极D2，并进而通过该联结片40 的引脚连接部分43电性连接至引线框架10的互联引脚15(图6D)。将一个 IC芯片50绝缘地粘接在联结片40的高端连接部分41，并形成IC芯片50、 HS芯片20及引脚14之间相互的引线60连接(图6E)；6A to 6G show the structural diagrams of each step of chip packaging in this embodiment, and FIG. 7 shows the flow of the packaging method in this embodiment. Wherein, the structure of the present embodiment is briefly described as follows, that is, a lead frame 10 (FIG. 6A) is set, including a first wafer stage 11, which is used to fixedly connect the HS chip 20 and form an electrical connection with the backside drain D1 (FIG. 6B); also includes a second chip stage, provided with a first part 12 and a second part 13, used for fixing and connecting the flipped package LS chip 30 and forming an electrical connection with the source electrode S2 and the gate G2 of the front surface thereof respectively (Fig. 6C). A connecting piece 40 is conductively connected on the HS chip 20 and the LS chip 30, so that the high-side connection portion 41 of the connecting piece 40 is electrically connected to the source S1 on the front side of the HS chip 20, and the low-end of the connecting piece 40 is connected to The portion 42 is electrically connected to the upper backside drain D2 of the LS chip 30 , and further electrically connected to the interconnection pin 15 of the lead frame 10 through the pin connection portion 43 of the bonding sheet 40 ( FIG. 6D ). An IC chip 50 is insulatedly bonded to the high-end connection portion 41 of the bonding sheet 40, and forms a mutual lead wire 60 connection between the IC chip 50, the HS chip 20 and the pin 14 (Fig. 6E);

与实施例1中的不同之处在于，本实施例中是在使用塑封体100将IC 芯片50，联结片40，HS芯片20及LS芯片30叠放的多层结构一起封装时，塑封体100底面暴露的结构不变，而是在该塑封体100的顶面上形成一个缺口101，使得联结片40上的低端连接部分42有一部分面积从该缺口101中暴露出来(图6F)。设置一个散热板72，例如是导热性能良好的铜板或类似材料制成，该散热板72的底部向下设置有一个突起件(图6G)，该突起件能够插入塑封体100的缺口101，且具有足够的厚度从而连接至联结片40形成导热接触。该散热板72的顶部留在塑封体100的顶面上(图6H)，因此可以在不超过塑封体100面积的情况下设置尽量大的散热面积，以提升散热效果。The difference from Embodiment 1 is that in this embodiment, when the plastic package 100 is used to package the IC chip 50, the joint sheet 40, the stacked multilayer structure of the HS chip 20 and the LS chip 30, the plastic package 100 The exposed structure of the bottom surface remains unchanged, but a gap 101 is formed on the top surface of the plastic package 100, so that a part of the low-end connecting portion 42 on the coupling piece 40 is exposed from the gap 101 (FIG. 6F). A heat dissipation plate 72 is provided, for example, it is made of a copper plate or similar material with good thermal conductivity, and a protrusion ( FIG. 6G ) is provided downward on the bottom of the heat dissipation plate 72 , and the protrusion can be inserted into the gap 101 of the plastic package 100 , and It is thick enough to be connected to the bonding tab 40 to form a thermally conductive contact. The top of the heat dissipation plate 72 remains on the top surface of the plastic package 100 ( FIG. 6H ), so a heat dissipation area as large as possible can be provided without exceeding the area of the plastic package 100 to improve the heat dissipation effect.

配合参见图7所示，本实施例中设置引线框架10、HS芯片20、LS芯片 30及IC芯片50的过程与实施例1中基本一致，不同点主要是需要设置散热板72，并在封装多层结构形成带缺口101的塑封体100之后，需要增加将散热板72的突起件插入到缺口101与其中的联结片40顶面实现连接及导热接触的步骤。Referring to Fig. 7, the process of setting lead frame 10, HS chip 20, LS chip 30 and IC chip 50 in this embodiment is basically the same as that in Embodiment 1. After the multi-layer structure forms the plastic package 100 with the notch 101 , it is necessary to add a step of inserting the protruding part of the heat dissipation plate 72 into the notch 101 to realize connection and thermal contact with the top surface of the connecting sheet 40 therein.

实施例4Example 4

图8A～图8F示出了本实施例中芯片封装各个步骤中的结构示意，图9 示出了本实施例中封装方法的流程。其中，本实施例的结构简述如下，即，设置一个引线框架10(图8A)，包含第一载片台11，用于固定连接HS芯片 20并与其背面漏极D1形成电性连接(图8B)；还包含第二载片台，设有第一部分12和第二部分13，用于固定连接翻转的封装LS芯片30并分别与其正面的源极S2和栅极G2形成电性连接(图8C)。将一个联结片40导电连接在HS芯片20及LS芯片30上，以使该联结片40的高端连接部分41电性连接至HS芯片20正面的源极S1，而该联结片40的低端连接部分42电性连接至LS芯片30LS芯片30向上的背面漏极D2，并进而通过该联结片40 的引脚连接部分43电性连接至引线框架10的互联引脚15(图8D)；FIG. 8A to FIG. 8F show schematic structural diagrams of each step of chip packaging in this embodiment, and FIG. 9 shows the flow of the packaging method in this embodiment. Wherein, the structure of the present embodiment is briefly described as follows, that is, a lead frame 10 (FIG. 8A) is set, including a first wafer stage 11, which is used to fixedly connect the HS chip 20 and form an electrical connection with its backside drain D1 (FIG. 8B); It also includes a second chip stage, which is provided with a first part 12 and a second part 13, which are used to fix and connect the flipped package LS chip 30 and form an electrical connection with the source S2 and the grid G2 on the front side respectively (Fig. 8C). A connecting piece 40 is conductively connected on the HS chip 20 and the LS chip 30, so that the high-side connection portion 41 of the connecting piece 40 is electrically connected to the source S1 on the front side of the HS chip 20, and the low-end of the connecting piece 40 is connected to The portion 42 is electrically connected to the upper back drain D2 of the LS chip 30, and then electrically connected to the interconnection pin 15 of the lead frame 10 through the pin connection portion 43 of the bonding sheet 40 (FIG. 8D);

与实施例1中的不同之处在于，本实施例中的联结片40结构不同，其中，高端连接部分41(及引脚连接部分43)的厚度小于低端连接部分42的厚度 (图8D)。而该低端连接部分42的厚度设计，应当满足将IC芯片50绝缘地粘接在联结片40的高端连接部分41上，且在IC芯片50与HS芯片20或引脚14之间连接若干引线60后的厚度大致相当(图8E)。则，塑封体100将上述IC芯片50，联结片40，HS芯片20及LS芯片30叠放的多层结构封装后，除塑封体100底面暴露的部分不变之外，同时还使该联结片40的低端连接部分42的顶面暴露在塑封体100的顶面之外以进一步帮助散热。本实施例中联结片40的三个部分可以是一体成型的，也可以是通过组装或连接后形成的。The difference from Embodiment 1 is that the structure of the connecting piece 40 in this embodiment is different, wherein the thickness of the high-end connection portion 41 (and the pin connection portion 43) is smaller than the thickness of the low-end connection portion 42 ( FIG. 8D ) . And the thickness design of this low-end connecting portion 42 should meet the requirement that the IC chip 50 be bonded insulatively on the high-end connecting portion 41 of the bonding sheet 40, and connect some lead wires between the IC chip 50 and the HS chip 20 or the pin 14. The thickness after 60 is roughly the same (Fig. 8E). Then, after the plastic package 100 encapsulates the above-mentioned IC chip 50, the joint sheet 40, the HS chip 20 and the LS chip 30 with a stacked multi-layer structure, except that the exposed part of the bottom surface of the plastic package 100 remains unchanged, the connection sheet is also made The top surface of the bottom connecting portion 42 of 40 is exposed outside the top surface of the plastic package 100 to further help heat dissipation. In this embodiment, the three parts of the coupling piece 40 can be integrally formed, or formed by assembling or connecting.

配合参见图9所示，本实施例中设置引线框架10、HS芯片20、LS芯片 30及IC芯片50及将其封装的过程与实施例1中基本一致，不同点主要是需要在封装前以胶带等覆盖联结片40的高端连接部分41的顶面，以便于封装后能够使其暴露设置。As shown in FIG. 9, the process of setting up lead frame 10, HS chip 20, LS chip 30 and IC chip 50 and packaging them in this embodiment is basically the same as that in Embodiment 1. An adhesive tape or the like covers the top surface of the high-end connection portion 41 of the coupling sheet 40 so that it can be exposed after packaging.

本发明中各个芯片本身的制作流程可以根据本领域的常规手段实现。而本发明中将多芯片通过联结片40叠放并连接的封装结构及封装方法，除了上文描述的使用两个MOSFET芯片及一个IC芯片50以外，还可以运用到其他器件的封装中，例如是封装高压IGBT芯片(绝缘栅双极型晶体管)、高压控制器，或者用于封装更多数量的芯片或更多的芯片叠层，等等。The manufacturing process of each chip in the present invention can be realized according to conventional means in the field. In the present invention, the packaging structure and packaging method in which multiple chips are stacked and connected through the connecting sheet 40 can also be applied to the packaging of other devices, except for the use of two MOSFET chips and an IC chip 50 described above, such as It is used to package high-voltage IGBT chips (insulated gate bipolar transistors), high-voltage controllers, or to package more chips or more chip stacks, etc.

尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。Although the content of the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be considered as limiting the present invention. Various modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the above disclosure. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (17)

1. a kind of encapsulating structure of multi-chip lamination, it is characterised in that include：
Lead frame, it is provided with the first slide holder spaced apart from each other, the second slide holder and some pins, and second slide holder enters One step is provided with Part I spaced apart from each other and Part II；
First chip, its backplate are arranged downwards and are conductively connected on the first slide holder；
Second chip, its front electrode is arranged downwards by upset and be conductively connected in the Part I of the second slide holder and the On two parts, some of front electrodes of second chip are connected to the Part I, and wherein other front electrodes connect It is connected to the Part II；
Connection sheet, its bottom surface are conductively connected to some of front electrodes that the first chip is arranged upwards, and the second chip simultaneously In the backplate arranged upwards；
3rd chip, its back side arrangement and insulated are connected on the top surface of the connection sheet downwards；
Plastic-sealed body, it is encapsulated stacks the 3rd chip, connection sheet, the first chip and the second chip for sandwich construction, draws successively Wire frame, and the lead between chip electrode and chip electrode or between chip electrode and pin is correspondingly connected to, also, make The part and at least a portion at the first slide holder and the second slide holder back side that pin is connected with external devices are exposed to the modeling Seal beyond body；
Contact formed with several local directed complete set connection sheet thickness on the connection sheet, the contact are to make the connection sheet top Depression forms the blind hole not penetrated and makes the downward projection of structure in connection sheet bottom surface simultaneously downwards.
2. the encapsulating structure of multi-chip lamination as claimed in claim 1, it is characterised in that
First chip is a HS chip as high-end MOSFET chips, and the Drain Electrodes Conductive that its back side is set is connected to the On one slide holder；
Second chip is a LS chip as low side MOSFET chips and Jing Guo wafer-level package, what its front was set Source conductive is connected on the Part I of the second slide holder, and the Gate Electrode Conductive that front is set is connected to the second of the second slide holder On part；
The back side of the connection sheet is conductively connected in the drain electrode of the source electrode and the LS chip backs of the HS chip front sides, is used To realize the electric connection between the two electrodes；
3rd chip is an IC chip as controller, and its bottom surface is insulated to be connected on the top surface of connection sheet, and It is corresponding in the respective electrode or lead frame that some electrodes of its top surface are correspondingly connected on other chips by lead respectively Pin；
Some electrodes of piece masking are not coupled in the HS chip front sides or LS chip backs, are correspondingly connected by lead respectively yet The respective pins in respective electrode or lead frame being connected on other chips.
3. the encapsulating structure of multi-chip lamination as claimed in claim 1, it is characterised in that
The encapsulating structure is also provided with heat sink before plastic-sealed body is formed, and the heat sink is connected respectively with the 3rd chip On the top surface of connection sheet, so that the heat sink forms thermal conductive contact with connection sheet, and then by the heat sink exposed to modeling Realize radiating in the surface sealed outside body top surface.
4. the encapsulating structure of multi-chip lamination as claimed in claim 1, it is characterised in that
The encapsulating structure is also provided with heat sink after plastic-sealed body is formed；It is formed further with lacking on the top surface of the plastic-sealed body Mouthful, the bottom of the heat sink is inserted into the breach to be connected to the top surface of connection sheet, and forms the heat sink and connection sheet Thermal conductive contact, and then radiating is realized at the top stayed in by the heat sink outside plastic-sealed body top surface.
5. the encapsulating structure of multi-chip lamination as described in any one in Claims 1 to 4, it is characterised in that
The connection sheet is provided with the high-end coupling part being connected on the first chip, is connected with the low side being connected on the second chip Part；The high-end coupling part and low side coupling part of the connection sheet have identical or different thickness；
The high-end coupling part, the first chip, the first slide holder thickness and value, with the low side coupling part, the second core Piece, the second slide holder thickness and value it is equal so that the top surface level of connection sheet places the 3rd chip with firm after connection.
6. the encapsulating structure of multi-chip lamination as claimed in claim 5, it is characterised in that
3rd chip is connected to the less part of thickness in the high-end coupling part or low side coupling part of connection sheet On, the top surface of a larger part of thickness is exposed to outside the plastic-sealed body in high-end coupling part or low side coupling part Realize radiating.
7. the encapsulating structure of multi-chip lamination as claimed in claim 5, it is characterised in that
The connection sheet is further provided with wire connections point, and it is conductively connected on the interconnection pin set by lead frame； The wire connections point, high-end coupling part and low side coupling part, are by being integrally formed or by assembly and connection come shape Into the connection sheet；
The wire connections point prevent connection sheet position in assembling and encapsulation process with being correspondingly arranged on the interconnection pin The locking mechanism of change.
8. the encapsulating structure of multi-chip lamination as claimed in claim 1, it is characterised in that
Between first chip and the first slide holder, between second chip and the second slide holder, the connection sheet and institute Being conductively connected between the first chip and the second chip is stated, is scolding tin or conduction by being set between the surface of interconnection Epoxide-resin glue realize；
Insulated connection between 3rd chip and the connection sheet, it is non-conductive viscous by being set in the 3rd chip back Gum deposit is realized.
9. the encapsulating structure of multi-chip lamination as claimed in claim 1, it is characterised in that
The connection sheet is copper sheet.
A kind of 10. method for packing of multi-chip lamination, it is characterised in that
Lead frame is set, and it is provided with the first slide holder spaced apart from each other, the second slide holder and some pins, second slide glass Platform is further provided with Part I and Part II spaced apart from each other；
The backplate of first chip is arranged downwards and is conductively connected on the first slide holder；
Second chip is overturn so that its front electrode is arranged downwards and is conductively connected in the Part I of the second slide holder and the On two parts, some of front electrodes of second chip are connected to the Part I, and wherein other front electrodes connect It is connected to the Part II；
Connection sheet bottom surface is conductively connected to some of front electrodes that the first chip arranges upwards simultaneously, and the second chip to In the backplate of upper arrangement；
The back side of 3rd chip arrangement and insulated is connected on the top surface of the connection sheet downwards；
The 3rd chip for sandwich construction, connection sheet, the first chip and the second chip, lead frame will be stacked successively by forming plastic-sealed body Frame, and be correspondingly connected to after the lead between chip electrode and chip electrode or between chip electrode and pin is packaged, Cut the plastic-sealed body and form an independent device；Also, make the part and the first slide glass that pin is connected with external devices At least a portion at platform and the second slide holder back side is exposed to beyond the plastic-sealed body；
Contact formed with several local directed complete set connection sheet thickness on the connection sheet, the contact is to pass through hole knockout The connection sheet top surface is set to be recessed downwards to form the blind hole not penetrated and make the downward projection of structure in connection sheet bottom surface simultaneously.
11. the method for packing of multi-chip lamination as claimed in claim 10, it is characterised in that
One heat sink of setting is also connected on the top surface of the connection sheet by the method for packing also before plastic packaging, so that The heat sink forms thermal conductive contact with connection sheet, and then the surface being exposed to by the heat sink outside plastic-sealed body top surface is realized and dissipated Heat.
12. the method for packing of multi-chip lamination as claimed in claim 10, it is characterised in that
Formed on the top surface for the plastic-sealed body that the method for packing is formed in encapsulation it is jagged, and by the bottom of a heat sink of setting The breach is inserted into be connected to the top surface of connection sheet, and forms the thermal conductive contact of the heat sink and connection sheet, and then passes through institute State the top that heat sink is stayed in outside plastic-sealed body top surface and realize radiating.
13. the method for packing of multi-chip lamination as claimed in claim 10, it is characterised in that
The connection sheet is provided with the high-end coupling part being connected on the first chip, is connected with the low side being connected on the second chip Part；The high-end coupling part and low side coupling part of the connection sheet have identical or different thickness；
During both thickness differences, the 3rd chip is connected to thickness in the high-end coupling part or low side coupling part of connection sheet On a less part, the top surface of a larger part of thickness is exposed in high-end coupling part or low side coupling part Radiating is realized outside the plastic-sealed body.
14. the method for packing of multi-chip lamination as claimed in claim 10, it is characterised in that
Between first chip and the first slide holder, between second chip and the second slide holder, the connection sheet and institute Being conductively connected between the first chip and the second chip is stated, is scolding tin or conduction by being set between the surface of interconnection Epoxide-resin glue realize；
Insulated connection between 3rd chip and the connection sheet, it is non-conductive viscous by being set in the 3rd chip back Gum deposit is realized.
15. the method for packing of multi-chip lamination as described in any one in claim 11~14, it is characterised in that
First chip is formed by procedure below：Plating is formed respectively to connect the surface of other devices on silicon chip Layer；Carry out chip testing；Chip back is ground and back face metalization is to control the thickness of the first chip and form the corresponding back side Electrode；Cutting forms each the first independent chip；And then first chip back is connected to downwards the first slide glass Platform.
16. the method for packing of multi-chip lamination as claimed in claim 15, it is characterised in that
Second chip is formed by procedure below：On silicon chip coating is formed to connect the surface of other devices； Carry out chip testing and circuitous pattern mapping；Ball is planted in front side of silicon wafer correspondence position to form corresponding front electrode；Chip-scale Encapsulation forms packaging body；Ground in chip front side, so as to plant the top of ball outside the top surface of packaging body；Chip front side pre-cut Cut, form scribe line；Chip back is ground and back face metalization is to control the thickness of the second chip and form corresponding back side electricity Pole；Cutting forms each the second independent chip；Afterwards, it is faced down after second chip is overturn and be connected to second Slide holder.
17. the method for packing of multi-chip lamination as claimed in claim 16, it is characterised in that
3rd chip is formed by procedure below：Chip back is ground；The backside coating of IC chip is nonconducting viscous Gum deposit；Cutting forms each the 3rd independent chip；Afterwards, the 3rd chip is bonded in be already attached to the first chip, The top surface of connection sheet on second chip；
Stacked in the 3rd chip, connection sheet, the first chip and the second chip after forming sandwich construction, also with procedure below：It is glutinous Tape, solidified；Between corresponding chip electrode and chip electrode, and bonded shape is distinguished between chip electrode and pin Into lead；Form plastic-sealed body；Coating is formed in the position outside plastic-sealed body；It is finally cut to create each independent wrapper Part.
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