CN107623992A - The optimization method and PCB of PCB inner figures, jigsaw structure and laminar structure - Google Patents
The optimization method and PCB of PCB inner figures, jigsaw structure and laminar structure Download PDFInfo
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- CN107623992A CN107623992A CN201710867665.6A CN201710867665A CN107623992A CN 107623992 A CN107623992 A CN 107623992A CN 201710867665 A CN201710867665 A CN 201710867665A CN 107623992 A CN107623992 A CN 107623992A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000005457 optimization Methods 0.000 title claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 161
- 229910052802 copper Inorganic materials 0.000 claims abstract description 122
- 239000010949 copper Substances 0.000 claims abstract description 122
- 239000011889 copper foil Substances 0.000 claims abstract description 39
- 239000003292 glue Substances 0.000 claims abstract description 37
- 238000003475 lamination Methods 0.000 claims abstract description 33
- 238000003801 milling Methods 0.000 claims description 20
- 210000002615 epidermis Anatomy 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 15
- 238000005553 drilling Methods 0.000 abstract description 14
- 239000000945 filler Substances 0.000 abstract description 10
- 238000009826 distribution Methods 0.000 abstract description 6
- 230000006872 improvement Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 46
- 229910000831 Steel Inorganic materials 0.000 description 10
- 239000010959 steel Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000006837 decompression Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000037303 wrinkles Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 241000446313 Lamella Species 0.000 description 1
- 241000784732 Lycaena phlaeas Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 241001074085 Scophthalmus aquosus Species 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a kind of optimization method of PCB inner figures and PCB, jigsaw structure and laminar structure, PCB inner figures include Tong Qu and Wu Tongqu, the no copper area includes the via area provided with least one via, when the residual copper rate in You Tong areas is less than special value, copper point is laid in the hole location of crossing of the via, and the diameter of copper point is less than the diameter of the via.The small size copper point of such laying can improve the uniformity of figure distribution, reduce the glue amount needed for no copper area filler, so as to reduce the corrugation of the copper foil after lamination process, empty equivalent risk, meanwhile, because the size of copper point is smaller than via, it can bore and remove in drilling；In addition, the laying of copper point can also lift PCB drilling qualities to a certain extent, and it is especially larger to the improvement for the haloing that drills, so as to lift PCB CAF performances.
Description
Technical field
The present invention relates to electronic applications, more particularly, to a kind of optimization method of PCB inner figures, PCB, jigsaw knot
Structure and laminar structure.
Background technology
It is traditional with the rapid development of electronic industry, as electronic product electric property transmit essential part-
Printed wiring board constantly tends to high speed, the development of high multiple stratification.High multilayer circuit board is that have the figures such as circuit by multiple making
Core plate and prepreg by pressing, drilling, electroplating, the technique such as etching and be made, wherein, lamination process is that PCB makes
One of critical process, PCB lamination quality is related to being processed further making and applying, such as drilling, figure for subsequent product
Making, consent nog plate, the reliability of product, PCB attachment etc..For the making of high multi-layer PCB, often occur that copper foil rises
Wrinkle, be laminated the application of the problems such as empty, especially High-Speed PCB material so that these problems are more prominent.Compared with FR4 materials,
The lamination process window of high-speed material is narrower, and mobility, the filler ability of prepreg are worse, it is easier to occur copper foil corrugation,
The problems such as empty is laminated, particularly when the inner figure design of graphic element has when being designed without copper area of large-size, no copper
Extremely easily there is the defects of starved, copper foil corrugation in area, and starved short circuit problem occurs after then easily causing to drill, electroplating, and
Starved can also influence PCB reliability；Copper foil corrugation can then cause rear process pad pasting not tight, so as to cause plating, open circuit etc. to lack
Fall into.
The content of the invention
Based on this, extremely easily occur that starved, copper foil are corrugated to be lacked the invention reside in the Wu Tongqu for overcoming prior art PCB
Fall into, there is provided a kind of optimization method of PCB inner figures, PCB, jigsaw structure and laminar structure.
Its technical scheme is as follows：
A kind of optimization method of PCB inner figures, PCB inner figures include Tong Qu and Wu Tongqu, the no copper area bag
The via area provided with least one via is included, when the residual copper rate in You Tong areas is less than special value, in the mistake hole position of the via
Put place and lay copper point, and the diameter of copper point is less than the diameter of the via.
Because via area has active graphical, i.e. via, prior art can not lay choked flow in such no copper via area
Block, so as to have copper foil corrugation, starved equivalent risk during lamination process, in order to improve this phenomenon, and PCB electricity is not influenceed
Gas transmission performance, when engineering CAM carries out PCB design optimization, when the residual copper rate in You Tong areas is less than special value, in the mistake
Porose area lays the copper point smaller than via diameter, and copper point installation position is consistent with the drilling to drill, i.e., crosses hole site difference each
Lay copper point.The small size copper point of such laying can improve the uniformity of figure distribution, reduce the glue amount needed for no copper area filler,
So as to reduce the corrugation of the copper foil after lamination process, empty equivalent risk, meanwhile, because the size of copper point is smaller than via, drilling
When can bore and remove, do not influence PCB electric property；In addition, the laying of copper point can also lift PCB drilling qualities to a certain extent,
It is especially larger to the improvement for the haloing that drills, so as to lift PCB CAF performances.
In one of the embodiments, the scope of the difference of the diameter dimension of the diameter of the copper point and the via is
2mil-6mil。
In one of the embodiments, when the residual copper rate in the You Tong areas is more than the special value, in the via
Area lays copper sheet, and the copper sheet is provided with shading ring in the hole location of crossing of the via, and the diameter of the shading ring is more than described
The diameter of via.
In one of the embodiments, the scope of the difference of the diameter dimension of the diameter of the shading ring and the via is
10mil-30mil。
The technical program also provides a kind of PCB, and the PCB is the optimization method according to any of the above-described PCB inner figures
The PCB that embodiment makes.
In one of the embodiments, including the milling band as cutter path, the milling are taken provided with least one resistance glue
Point.
In one of the embodiments, it is described resistance glue point be shaped as it is square or circular, and it is described resistance glue point the length of side
Or the size range of diameter is 5mil-20mil, the distance of resistance glue point to the milling belt edge is 5mil-10mil.
The technical program also provides a kind of jigsaw structure, including PCB, the PCB are described in any of the above-described embodiment
PCB, the PCB include at least two graphic elements for being provided with the no copper area, and the Wu Tongqu of adjacent pattern unit is staggered.
Avoid no copper area accumulation excessive, more easily cause copper foil corrugation, be laminated phenomena such as empty.
The technical program also provides a kind of laminar structure, including pre- lamination, and the pre- lamination is set including at least two-layer laminate
The PCB put, the PCB are the PCB described in any of the above-described embodiment；Above the upper epidermis of the pre- lamination and layer lower section is
Provided with one layer of cushion.During PCB layer pressure, pre- lamination need to be pressed using steel plate, due to steel plate to cover type effect poor, work as height
Multi-layer PCB exist large-size without copper area when, the pressure that no copper area is subject to is smaller, or even decompression, so as to easily causing filler
Defect and copper foil wrinkling.And the technical program can effectively be changed by increasing by one layer of cushion in the levels of pre- lamination
It is apt to decompression situation of the high multi-layer PCB without copper area, improves gummosis uniformity.
In one of the embodiments, the cushion includes layer of prepreg and copper foil layer, and the layer of prepreg is set
Between two layers of copper foil layer.
The beneficial effects of the present invention are：
When the residual copper rate in You Tong areas is less than special value, the copper point smaller than via diameter, copper are laid in the via area
Point laying is consistent with the drilling to drill, i.e., lays copper point respectively in each hole site of crossing.The small size copper point of such laying can change
The uniformity of kind figure distribution, reduces the glue amount needed for no copper area filler, so as to reduce the corrugation of the copper foil after lamination process, sky
Hole equivalent risk, meanwhile, because the size of copper point is smaller than via, it can bore and remove in drilling；In addition, the laying of copper point can also be certain
PCB drilling qualities are lifted in degree, it is especially larger to the improvement for the haloing that drills, so as to lift PCB CAF performances.
When the residual copper rate in You Tong areas is more than the special value, in via area laying copper sheet, the copper sheet is described
The hole location of crossing of via is provided with shading ring, and the diameter of the shading ring is more than the diameter of the via.Such optimization method pin
The larger situation of residual copper rate to the You Tong areas without Tong Qu peripheries, it can equally improve the uniformity of figure distribution, reduce no copper area
Glue amount needed for filler, so as to reduce the corrugation of the copper foil after lamination process, empty equivalent risk.In order to prevent via from being led with copper sheet
Lead to and cause short circuit, shading ring need to be set between via and copper sheet, i.e., the need of described copper sheet get around the via and were laid in
The other positions of porose area, copper sheet make ring-type hollow processing at via along the periphery in hole, form shading ring.
The jigsaw structure of the present invention avoids no copper area accumulation excessive, more easily causes copper foil corrugation, is laminated phenomena such as empty.
The present invention can be effectively improved high multi-layer PCB without copper area by increasing by one layer of cushion in the levels of pre- lamination
Decompression situation, improve gummosis uniformity.
Brief description of the drawings
Fig. 1 is the PCB of present invention optimization structural representation one；
Fig. 2 is the PCB of present invention optimization structural representation two；
Fig. 3 is the PCB construction schematic diagram of the present invention；
The milling band partial structural diagram that Fig. 4 is Fig. 3；
Fig. 5 is the structural representation that the milling of the present invention takes the resistance glue point of adjacent inner layer；
Fig. 6 is the PCB of present invention jigsaw structural representation one；
Fig. 7 is the PCB of present invention jigsaw structural representation two；
Fig. 8 is the PCB of present invention jigsaw structural representation three；
Fig. 9 is the schematic diagram of the laminate structure of the present invention.
Description of reference numerals：
100th, Wu Tongqu；10th, via area；11st, via；12nd, copper point；13rd, copper sheet；131st, shading ring；200th, milling band；20、
Hinder glue point；21st, the first resistance glue point；22nd, the second resistance glue point；300th, graphic element；400th, pre- lamination；500th, cushion；51st, half is solid
Change lamella；52nd, copper foil layer；600th, You Tong areas.
Embodiment
For the objects, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with accompanying drawing and specific embodiment party
Formula, the present invention is described in further detail.It should be appreciated that embodiment described herein is only solving
The present invention is released, does not limit protection scope of the present invention.
A kind of optimization method of PCB inner figures as shown in Figure 1, PCB inner figures include copper area 600 and Wu Tongqu
100, the no copper area 100 includes the via area 10 provided with least one via 11, when the residual copper rate in You Tong areas is less than certain number
During value, copper point 12 is laid in the hole location of crossing of the via 11, and the diameter of copper point 12 is less than the diameter of the via.
Because via area 10 has active graphical, i.e. via 11, prior art can not be laid in such no copper via area 10
Choker bar, so as to have copper foil corrugation, starved equivalent risk during lamination process, in order to improve this phenomenon, and do not influence PCB
Electric transmission performance, engineering CAM carry out PCB optimizations when, when the residual copper rate in You Tong areas is less than special value, in the mistake
The hole location of crossing of porose area 10 lays the copper point 12 smaller than the diameter of via 11；In present embodiment, the special value is 30%,
That is, when the residual copper rate in You Tong areas is less than 30%, copper point can be laid, specifically, the residual copper rate in the You Tong areas is selected without copper area
The residual copper rate in the You Tong areas on 100 peripheries, the residual copper rate without 2 centimetres of Nei Youtong areas of unilateral distance of copper area 100 can be selected as ginseng
Examine value.The laying of copper point 12 is consistent with the drilling to drill, i.e., lays copper point 12 respectively in the hole site of crossing of each via 11.Such cloth
If small size copper point 12 can improve figure distribution uniformity, the glue amount needed for no filler of copper area 100 is reduced, so as to reduce
Copper foil corrugation after lamination process, empty equivalent risk, meanwhile, because the size of copper point is smaller than via, it can bore and remove in drilling, no
Influence PCB electric property；In addition, the laying of copper point 12 can also lift PCB drilling qualities to a certain extent, especially to boring
The improvement of hole haloing is larger, so as to lift PCB CAF performances.
The scope of the difference of the diameter of the copper point 12 and the diameter dimension of the via 11 is 2mil-6mil.This size model
The copper point 12 enclosed can be removed in drilling by smooth brill, and the difference of specific size can also be according to the You Tong areas without the periphery of copper area 100
Residual copper rate size determines.
As shown in Fig. 2 when the residual copper rate in the You Tong areas on the no periphery of copper area 100 is more than the special value, that is, it is more than
When 30%, copper sheet 13 is laid in the via area 10, the copper sheet 13 is provided with shading ring in the hole location of crossing of the via 11
131, the diameter of the shading ring 131 is more than the diameter of the via 11.Such optimization method is directed to having without the periphery of copper area 100
The larger situation of the residual copper rate in copper area, can equally improve the uniformity of figure distribution, reduce the glue amount needed for no copper area filler, from
And the corrugation of the copper foil after lamination process, empty equivalent risk can be reduced.In order to prevent that via 11 and copper sheet 13 from turning on and causes short circuit,
Shading ring 131 need to be set between via 11 and copper sheet 13, i.e., the need of described copper sheet 13 get around the via 11 and are laid in via
The other positions in area 10, copper sheet 13 make ring-type hollow processing at via 11 along the periphery in hole, form shading ring 131.It is described every
Diameter from ring 131 can be according to the process capability of PCB factories and depending on the residual copper rate in the You Tong areas without the periphery of copper area 100, this
In embodiment, the scope of the difference of the diameter dimension of the diameter of shading ring 131 and the via 11 is 10mil-30mil, you can
The diameter of shading ring 131 is set to bigger 10mil-30mil than the diameter of via 11.
Present embodiment also provides a kind of PCB, and the PCB is the optimization method according to any of the above-described PCB inner figures
The PCB that embodiment makes.The PCB makes according to the optimization method of above-mentioned PCB inner figures, after reducing PCB layer pressure processing
Copper foil corrugation, empty equivalent risk.
As shown in Figure 3 and Figure 4, the PCB of present embodiment includes milling band 200 as cutter path, on the milling band 200
Provided with least one resistance glue point 20.When making high multi-layer PCB, being accumulated without copper area 100 for each floor milling bands of PCB, milling often occurs
Depression, copper foil corrugation etc. at band 200, and because the side of milling band 200 is graphic element 300, therefore the position filler of milling band 200 is not
Foot can often influence the quality of graphic element, and to improve this phenomenon, the resistance glue of certain size can be laid on the feed path of milling band 200
Point 20, resistance glue point 20 can be copper point.Being shaped as the resistance glue point 20 is square or circular, and present embodiment is then using circular resistance
Glue point, resistance glue point 20 use copper point.Because the size of milling band 200 is generally smaller, width is about 0.1 inch, hinders glue point
20 laying also needs the round dot or square using small size, and the length of side of the resistance glue point 20 or the size range of diameter are
5mil-20mil, the center spacing of adjacent resistance glue point 20 may be configured as 5-20mil.In addition, the resistance glue point 20 arrives the side of milling band 200
The distance of edge is 5mil-10mil.The specific size and spacing for hindering glue point 20 can be according to the figures in milling band 200 nearby two inches
Residual copper rate is determined, and when the residual copper rate of figure is relatively low, for example, during residual copper rate ＜ 30%, can will hinder the length of side or straight of glue point 20
Footpath is dimensioned to 5mil, and the center spacing of adjacent resistance glue point 20 is arranged to 15mil；When the residual copper rate of figure is general, such as
During 30%≤residual copper rate ＜ 50%, the length of side for hindering glue point 20 or diameter can be arranged to 10mil, it is adjacent to hinder in glue point 20
In the heart away from being arranged to 20mil；When the residual copper rate of figure is larger, during such as residual copper rate >=50%, can by hinder glue point 20 the length of side or
Diameter is arranged to 10mil, and the center spacing of adjacent resistance glue point 20 is arranged to 5mil.Make as far as possible the residual copper rate of milling band 200 with
The residual copper rate of figure is consistent, and lifts thickness of slab uniformity.In addition, as shown in figure 5, when PCB has two layers or multilayer, milling band
The resistance glue point 20 of adjacent inner layer is staggered on 200, so as to further lift thickness of slab uniformity；L in figurenFirst resistance glue point of layer
21 and and LnThe adjacent L of layern+1Second resistance glue point 22 of layer is staggered.
Present embodiment also provides a kind of jigsaw structure as shown in Figure 6 to 8, including PCB, the PCB are any of the above-described
PCB described in embodiment, the PCB include at least two graphic elements 300 for being provided with the no copper area 200, adjacent pattern list
Being staggered without copper area 200 for member 300, avoids no copper area 200 from accumulating excessive, and it is existing more to easily cause copper foil corrugation, lamination cavity etc.
As.As shown in Figure 6 and Figure 7, it is a jigsaw structure for spelling six, i.e., six graphic elements 300, each graphic element in jigsaw is present
All include copper area 600 in 300 and be staggered without copper area 200, each graphic element 300 without copper area 200；It is illustrated in figure 8
One spells three jigsaw structure, i.e., three graphic elements 300 in jigsaw be present；The jigsaw structure of present embodiment is also applied for other
One spells more jigsaw.
Present embodiment also provides a kind of laminar structure, including pre- lamination 400, and the pre- lamination 400 includes at least two layers
The PCB being stacked, and prepreg is provided between the PCB of adjacent layer, the PCB is the PCB described in any of the above-described embodiment；
One layer of cushion 500 is equipped with above the upper epidermis of the pre- lamination 400 and below layer, forms new laminate structure.
During PCB layer pressure, two blocks of steel plates need to be used to press pre- laminations 400, due to steel plate to cover type effect poor, when high multi-layer PCB is deposited
When large-size is without copper area 100, the pressure that no copper area 100 is subject to is smaller, or even decompression, so as to easily cause filler defect
And copper foil wrinkling.It is and present embodiment in the levels of pre- lamination 400 by increasing by one layer of cushion 500, i.e., described
Cushion 500 is located between steel plate and pre- lamination 400, can be effectively improved decompression situation of the high multi-layer PCB without copper area 100, is improved
Gummosis uniformity.
In present embodiment, the cushion 500 includes layer of prepreg 51 and copper foil layer 52, the layer of prepreg 51
Between two layers of copper foil layer 52.Due to the coefficient of expansion difference of different materials, in PCB layer presses process, it is used for
The steel plate swell increment of pressing is less than the swell increment of the copper foil on pre- lamination 400, and steel plate will limit the expansion of copper foil in the plane, be
Swelling stress is discharged, copper foil can be recessed toward prepreg side in PCB, so as to produce copper foil corrugation；And the copper foil of cushion 500
Layer 52 is in contact with pre- lamination 400 to be laminated, and the thermal coefficient of expansion of steel plate and the copper foil on PCB can be avoided inconsistent and caused
Copper foil corrugation the problem of.Further, the thickness of the copper foil layer 52 can be 12 μm or 18 μm of common copper foil, prepreg
Layer 51 can use conventional FR4 materials, and specification can use the common specifications such as 1080,3313,2116, so as to reduce cushion 500
Cost, meanwhile, after the copper foil layer 52 of cushion 500 is laminated, is torn off being reclaimed, is recycled, avoided after can processing
Waste of material.In addition, using copper foil layer 52 plus the laminate structure of layer of prepreg 51, except can effectively improve high multi-layer PCB layer
The problems such as copper foil in pressure processing wrinkles, be empty, can also reduce contraction situation of the material in bonding processes, it is more to be advantageous to height
Layer PCB interlayer alignment control.Because steel plate in X-direction and Y-direction has its intrinsic coefficient of expansion, traditional pre- lamination 400
Due to not setting cushion 500, steel plate can produce larger tensile force in X-direction and Y-direction, and use the lamination of present embodiment
Structure can provide static pressure rather than stretching pressure, contribute to balance plate surface pressure, so as to improve harmomegathus situation, and this embodiment party
The harmomegathus value of sheet material is smaller than traditional laminate structure by 3/10000ths or so obtained by the laminate structure of formula, can reduce lamination harmomegathus and become
Change value, it is more beneficial for controlling interlayer alignment quality.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of optimization method of PCB inner figures, it is characterised in that PCB inner figures include Tong Qu and Wu Tongqu, described
Include the via area provided with least one via without copper area, when the residual copper rate in You Tong areas is less than special value, in the via
Cross hole location lay copper point, and the diameter of copper point be less than the via diameter.
2. the optimization method of PCB inner figures according to claim 1, it is characterised in that the diameter of the copper point and institute
The scope for stating the difference of the diameter dimension of via is 2mi l-6mi l.
3. the optimization method of PCB inner figures according to claim 1 or 2, it is characterised in that residual when the You Tong areas
When copper rate is more than the special value, copper sheet is laid in the via area, the copper sheet is set in the hole location of crossing of the via
There is shading ring, the diameter of the shading ring is more than the diameter of the via.
4. the optimization method of PCB inner figures according to claim 3, it is characterised in that the diameter of the shading ring with
The scope of the difference of the diameter dimension of the via is 10mi l-30mi l.
5. a kind of PCB, it is characterised in that the PCB is the optimization method according to any one of claim 1-4 PCB inner figures
The PCB of making.
6. PCB according to claim 5, it is characterised in that including the milling band as cutter path, the milling, which takes, to be provided with
At least one resistance glue point.
7. PCB according to claim 6, it is characterised in that being shaped as the resistance glue point is square or circular and described
It is 5mi l-20mi l to hinder the length of side of glue point or the size range of diameter.
A kind of 8. jigsaw structure, it is characterised in that including PCB, the PCB be claim any one of 5-7 described in PCB, institute
Stating PCB includes at least two graphic elements for being provided with the no copper area, and the Wu Tongqu of adjacent pattern unit is staggered.
A kind of 9. laminar structure, it is characterised in that including pre- lamination, the pre- lamination includes the PCB that at least two-layer laminate is set,
The PCB is the PCB described in claim any one of 5-7；It is equipped with above the upper epidermis of the pre- lamination and below layer
One layer of cushion.
10. laminar structure according to claim 9, it is characterised in that the cushion includes layer of prepreg and copper foil
Layer, the layer of prepreg is between two layers of copper foil layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710867665.6A CN107623992A (en) | 2017-09-22 | 2017-09-22 | The optimization method and PCB of PCB inner figures, jigsaw structure and laminar structure |
| PCT/CN2017/120099 WO2019056650A1 (en) | 2017-09-22 | 2017-12-29 | Method for optimizing pcb inner layer pattern, pcb, board spliced structure and laminated structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710867665.6A CN107623992A (en) | 2017-09-22 | 2017-09-22 | The optimization method and PCB of PCB inner figures, jigsaw structure and laminar structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107623992A true CN107623992A (en) | 2018-01-23 |
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ID=61090230
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710867665.6A Pending CN107623992A (en) | 2017-09-22 | 2017-09-22 | The optimization method and PCB of PCB inner figures, jigsaw structure and laminar structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107623992A (en) |
| WO (1) | WO2019056650A1 (en) |
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| CN108811376A (en) * | 2018-06-28 | 2018-11-13 | 广州兴森快捷电路科技有限公司 | The production method of the thick copper coin of high density interconnection and thick copper core plate |
| CN109095434A (en) * | 2018-07-09 | 2018-12-28 | 武汉耐普登科技有限公司 | Structural member of sensor and its manufacturing method |
| CN109815556A (en) * | 2018-12-30 | 2019-05-28 | 广州兴森快捷电路科技有限公司 | A kind of recognition methods, device, equipment and the storage medium of line layer isolated area |
| CN110636717A (en) * | 2019-09-24 | 2019-12-31 | 北大方正集团有限公司 | Method and device for reducing the scrapping rate of printed circuit boards |
| CN112858875A (en) * | 2021-01-04 | 2021-05-28 | 广州广合科技股份有限公司 | PCB CAF test module design method |
| CN114205991A (en) * | 2020-09-18 | 2022-03-18 | 重庆方正高密电子有限公司 | PCB board |
| CN114980514A (en) * | 2022-05-19 | 2022-08-30 | 深圳崇达多层线路板有限公司 | A method, circuit board and electronic device for improving the cavity of the edge of a circuit board |
| CN118829086A (en) * | 2024-08-15 | 2024-10-22 | 中山芯承半导体有限公司 | A method for improving substrate warping |
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| CN109095434A (en) * | 2018-07-09 | 2018-12-28 | 武汉耐普登科技有限公司 | Structural member of sensor and its manufacturing method |
| CN109815556A (en) * | 2018-12-30 | 2019-05-28 | 广州兴森快捷电路科技有限公司 | A kind of recognition methods, device, equipment and the storage medium of line layer isolated area |
| CN110636717A (en) * | 2019-09-24 | 2019-12-31 | 北大方正集团有限公司 | Method and device for reducing the scrapping rate of printed circuit boards |
| CN114205991A (en) * | 2020-09-18 | 2022-03-18 | 重庆方正高密电子有限公司 | PCB board |
| CN114205991B (en) * | 2020-09-18 | 2024-05-03 | 重庆方正高密电子有限公司 | PCB board |
| CN112858875A (en) * | 2021-01-04 | 2021-05-28 | 广州广合科技股份有限公司 | PCB CAF test module design method |
| CN114980514A (en) * | 2022-05-19 | 2022-08-30 | 深圳崇达多层线路板有限公司 | A method, circuit board and electronic device for improving the cavity of the edge of a circuit board |
| CN118829086A (en) * | 2024-08-15 | 2024-10-22 | 中山芯承半导体有限公司 | A method for improving substrate warping |
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