[go: up one dir, main page]

CN107622957B - 双面SiP的三维封装结构的制造方法 - Google Patents

双面SiP的三维封装结构的制造方法 Download PDF

Info

Publication number
CN107622957B
CN107622957B CN201710875279.1A CN201710875279A CN107622957B CN 107622957 B CN107622957 B CN 107622957B CN 201710875279 A CN201710875279 A CN 201710875279A CN 107622957 B CN107622957 B CN 107622957B
Authority
CN
China
Prior art keywords
manufacturing
packaging structure
double
board
temporary carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710875279.1A
Other languages
English (en)
Other versions
CN107622957A (zh
Inventor
林耀剑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201710875279.1A priority Critical patent/CN107622957B/zh
Publication of CN107622957A publication Critical patent/CN107622957A/zh
Application granted granted Critical
Publication of CN107622957B publication Critical patent/CN107622957B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明涉及一种双面SiP的三维封装结构的制造方法，所述方法包括以下步骤：步骤一、取一临时载板；步骤二、在临时载板上贴装核心转接板；步骤三、在核心转接板正面贴装扇出型晶圆级封装结构、第一被动元件和第一3D导电部件；步骤四、塑封作业；步骤五、机械研磨露出第一3D导电部件并移除临时载板；步骤六、核心转接板背面贴装芯片、第二被动元件和第二3D导电部件；步骤七、塑封，植球作业；步骤八、下一步封装制程或者切割成单颗产品，完成测试。本发明能够使用预制的窄中心距3D导电部件成为堆叠封装的支撑结构，可以降低封装模组的尺寸高度，提高封装模组的高频性能以及高度设计和翘曲控制的灵活性。

Description

双面SiP的三维封装结构的制造方法
技术领域
本发明涉及一种双面SiP的三维封装结构的制造方法，属于半导体封装技术领域。
背景技术
根据半导体技术的发展，电子器件变得微型化并且越来越轻以满足用户的需求，因此，用于实现与单个封装相同或不同的半导体芯片的多芯片封装技术得到增强。与半导体芯片所实现的封装相比，多芯片封装就封装大小或重量以及安装过程而言是有利的，具体地讲，多芯片封装主要应用于要求微型化和减重的便携式通信终端。
在这些多芯片封装中，封装基板堆叠在另一个封装基板上的层叠型封装被称为堆叠封装（package on package，以下称为“PoP” ）。由于随着半导体封装技术的发展，半导体封装的容量已变得更高，厚度变得更薄并且尺寸变得更小，堆叠的芯片数量最近已经增大。
常规的层叠封装采用焊料球印刷工艺和回流工艺，问题在于，当增大焊料球的尺寸或高度以便增大封装之间的距离时，焊料球会产生开裂或破碎。
另外随着封装制程中的高密度线路、多种封装材料的使用、以及各种芯片以及功能器件的使用，使得整个封装体很复杂，各种材质的搭配不易平衡，容易导致整体的翘曲变形。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种双面SiP的三维封装结构的制造方法，它能够使用预制的窄中心距3D导电部件成为堆叠封装的支撑结构，模组中使用薄型晶圆级封装和其他器件的组合，可以降低封装模组的尺寸高度，提高封装模组的高频性能以及高度设计和翘曲控制的灵活性。
本发明解决上述问题所采用的技术方案为：一种双面SiP的三维封装结构的制造方法，所述方法包括如下步骤：
步骤一、取一临时载板；
步骤二、在临时载板上贴装核心转接板；
步骤三、在核心转接板正面贴装扇出型晶圆级封装结构、第一被动元件和第一3D导电部件，第一3D导电部件布置于扇出型晶圆级封装结构和第一被动元件的外围；
步骤四、核心转接板正面进行塑封作业；
步骤五、机械研磨露出第一3D导电部件并移除临时载板；
步骤六、核心转接板背面贴装芯片、第二被动元件和第二3D导电部件，第二3D导电部件布置于芯片和第二被动元件的外围；
步骤七、核心转接板正面进行塑封，植球作业；
步骤八、下一步封装制程或者整体进行切割成单颗产品，完成测试。
步骤一中的临时载板使用硅或者玻璃晶圆/板材。
步骤一中的脱膜层使用树脂类薄膜或者惰性材料层或者多层惰性金属层。
树脂类薄膜采用HD3000系列；惰性材料层采用SiO2或SiN；多层惰性金属层采用Cu/Ti 或Cu/NiV/Ti。
步骤二中的核心转接板是由晶圆级或板级制作而成的多层线路板，厚度＜100um，细间距≤15um。
步骤三中的第一3D导电部件和步骤六中的第二3D导电部件均可连接在一起贴装或单独贴装。
贴装方式采用焊锡膏、点助焊剂或导电/不导电胶的方式。
步骤五中移除临时载板使用激光扫描、机械研磨或者化学蚀刻的方式。
步骤五中的机械研磨在移除临时载板前进行或在移除临时载板后进行。
与现有技术相比，本发明的优点在于：
1、封装模组中使用晶圆级或者面板级制作的重布线核心转接板以及内部使用的晶圆级封装结构可以降低整体封装模组的高度和尺寸；
2、主芯片、其他芯片（如MEMS、控制芯片、集成无源器件）采用晶圆级封装结构，使用低损耗的绝缘材料，可以提高高频性能；另外晶圆级封装结构可以单独另外制作，可以在测试合格之后应用于本模组封装中，可防止多芯片单独植入SiP模组却在最终测试不合格，可以减少芯片损失，且保证最终产品的高良率；
3、可以提高整体封装模组的高度设计的灵活性和翘曲控制的稳定性：上下部分的3D导电部件是预制单独设计的，可以有全金属柱和金属柱中填充树脂的组合，或金属平行侧壁中填充复合材料的组合；具有灵活的CTE设计可以来控制整体结构的翘曲，其高度设计也可以进行灵活的设计；扇出型晶圆级封装也可以通过调整塑封的厚度和凸块设计的高度来调整翘曲度。同时金属平行侧壁中填充复合材料的组合可以提供高深度/间距比的3D低成本导电部件。
附图说明
图1~图8为本发明一种双面SiP的三维封装结构的制造方法的各工序流程图。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
本实施例中的一种双面SiP的三维封装结构的制造方法，所述方法包括如下步骤：
步骤一、参见图1，取一临时载板，并在临时载板正面贴上一层脱膜层；
临时载板使用硅或者玻璃晶圆/板材，脱膜层使用树脂类薄膜如HD3000系列，或者惰性材料层如SiO2、SiN，或者多层惰性金属层Cu/Ti 或Cu/NiV/Ti 等；
步骤二、参见图2，在临时载板上的脱膜层上贴装核心转接板，或逐层沉积/涂胶/贴膜与薄膜电路成型连接从而形成多层堆叠薄膜电路；
核心转接板是由晶圆级或板级制作而成的多层线路板，厚度＜100um，细间距≤15um，至少两层的线路层，介电层材料相同或者外层使用低CTE（热膨胀系数）、高杨氏模量（E）的材料，内层用高CTE（热膨胀系数）、低杨氏模量（E）的材料，以便控制翘曲度和界面分层，所有的介电层有低的介电常数和介质损耗；
步骤三、参见图3，在核心转接板正面贴装扇出型晶圆级封装结构、第一被动元件和第一3D导电部件，第一3D导电部件布置于扇出型晶圆级封装结构和第一被动元件的外围；
第一3D导电部件可连接在一起或单独贴装；
贴装方式可采用焊锡膏、点助焊剂、导电/不导电胶等方式；
高价值的扇出型晶圆级封装结构可经过检测合格后进行贴装，保证产品良率；
第一3D导电部件可以连接相邻的两个相同或者不同线路设计的单元；第一3D导电部件可采用两层或多层线路的PCB板、两层线路的MIS板或其他相似的技术；
步骤四、参见图4，核心转接板正面进行塑封作业；
步骤五、参见图5，机械研磨露出第一3D导电部件并移除临时载板；
机械研磨可在移除临时载板前进行，也可在移除临时载板后进行；
移除临时载板可使用激光扫描、机械研磨或者化学蚀刻的方式；
步骤六、参见图6，核心转接板背面贴装芯片、第二被动元件和第二3D导电部件，第二3D导电部件布置于芯片和第二被动元件的外围；
价值高的芯片可在最后贴装，贴装芯片期间可以进行OS（开短路）检测，以避免高价值芯片的损失；
第二3D导电部件可连接在一起或单独贴装；
步骤七、参见图7，核心转接板正面进行塑封，植球作业；
步骤八、参见图8，下一步封装制程或者整体进行切割成单颗产品，完成测试。

Claims (9)

1.一种双面SiP的三维封装结构的制造方法，其特征在于所述方法包括如下步骤：
步骤一、取一临时载板；
步骤二、在临时载板上贴装核心转接板；
步骤三、在核心转接板正面贴装扇出型晶圆级封装结构、第一被动元件和第一3D导电部件，第一3D导电部件布置于扇出型晶圆级封装结构和第一被动元件的外围；
步骤四、核心转接板正面进行塑封作业；
步骤五、机械研磨露出第一3D导电部件并移除临时载板；
步骤六、核心转接板背面贴装芯片、第二被动元件和第二3D导电部件，第二3D导电部件布置于芯片和第二被动元件的外围；
步骤七、核心转接板背面进行塑封，植球作业；
步骤八、下一步封装制程或者整体进行切割成单颗产品，完成测试。
2.根据权利要求1所述的一种双面SiP的三维封装结构的制造方法，其特征在于：步骤一中的临时载板使用硅或者玻璃晶圆/板材。
3.根据权利要求1所述的一种双面SiP的三维封装结构的制造方法，其特征在于：步骤一临时载板正面贴上一层脱膜层，脱膜层使用树脂类薄膜或者惰性材料层或者多层惰性金属层。
4. 根据权利要求3所述的一种双面SiP的三维封装结构的制造方法，其特征在于：树脂类薄膜采用HD3000系列；惰性材料层采用SiO2或SiN；多层惰性金属层采用Cu/Ti 或Cu/NiV/Ti。
5.根据权利要求1所述的一种双面SiP的三维封装结构的制造方法，其特征在于：步骤二中的核心转接板是由晶圆级或板级制作而成的多层线路板，厚度＜100um，细间距≤15um。
6.根据权利要求1所述的一种双面SiP的三维封装结构的制造方法，其特征在于：步骤三中的第一3D导电部件和步骤六中的第二3D导电部件均可连接在一起贴装或单独贴装。
7.根据权利要求1所述的一种双面SiP的三维封装结构的制造方法，其特征在于：贴装方式采用焊锡膏、点助焊剂或导电/不导电胶的方式。
8.根据权利要求1所述的一种双面SiP的三维封装结构的制造方法，其特征在于：步骤五中移除临时载板使用激光扫描、机械研磨或者化学蚀刻的方式。
9.根据权利要求1所述的一种双面SiP的三维封装结构的制造方法，其特征在于：步骤五中的机械研磨在移除临时载板前进行或在移除临时载板后进行。
CN201710875279.1A 2017-09-25 2017-09-25 双面SiP的三维封装结构的制造方法 Active CN107622957B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710875279.1A CN107622957B (zh) 2017-09-25 2017-09-25 双面SiP的三维封装结构的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710875279.1A CN107622957B (zh) 2017-09-25 2017-09-25 双面SiP的三维封装结构的制造方法

Publications (2)

Publication Number Publication Date
CN107622957A CN107622957A (zh) 2018-01-23
CN107622957B true CN107622957B (zh) 2019-11-01

Family

ID=61090730

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710875279.1A Active CN107622957B (zh) 2017-09-25 2017-09-25 双面SiP的三维封装结构的制造方法

Country Status (1)

Country Link
CN (1) CN107622957B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109473363B (zh) * 2018-11-12 2024-09-06 深圳市江波龙电子股份有限公司 系统级封装结构及生产方法
CN109559996A (zh) * 2018-11-13 2019-04-02 无锡中微高科电子有限公司 一种3D高密度互联的PoP塑封器件制备方法
CN111816645A (zh) * 2019-04-10 2020-10-23 力成科技股份有限公司 天线整合式封装结构及其制造方法
US11462461B2 (en) 2020-06-03 2022-10-04 Apple Inc. System in package for lower z height and reworkable component assembly
CN113921473B (zh) * 2020-07-10 2024-11-08 江苏长电科技股份有限公司 封装结构和封装结构制造方法
CN115148710B (zh) * 2021-03-29 2024-12-24 矽磐微电子(重庆)有限公司 Mcm封装结构及其制作方法
CN114141726B (zh) * 2021-12-01 2024-12-24 甬矽电子(宁波)股份有限公司 扇出型封装方法和扇出型封装结构
CN117525061A (zh) * 2022-07-25 2024-02-06 矽磐微电子(重庆)有限公司 扇出型系统级封装结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517930A (zh) * 2013-10-04 2015-04-15 联发科技股份有限公司 半导体封装
CN105514087A (zh) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 双面扇出型晶圆级封装方法及封装结构
CN106409780A (zh) * 2015-08-03 2017-02-15 矽品精密工业股份有限公司 电子封装件及其制法
CN106601716A (zh) * 2015-10-20 2017-04-26 台湾积体电路制造股份有限公司 多堆叠的多输出封装件中的晶圆级屏蔽罩及其形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157295A1 (en) * 2006-12-20 2008-07-03 Custom One Design, Inc. Methods and apparatus for multichip module packaging
CN102709260B (zh) * 2012-05-08 2015-05-20 日月光半导体制造股份有限公司 半导体封装构造
KR101477392B1 (ko) * 2013-05-21 2014-12-29 삼성전기주식회사 전자 소자 모듈
KR20150092876A (ko) * 2014-02-06 2015-08-17 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517930A (zh) * 2013-10-04 2015-04-15 联发科技股份有限公司 半导体封装
CN106409780A (zh) * 2015-08-03 2017-02-15 矽品精密工业股份有限公司 电子封装件及其制法
CN106601716A (zh) * 2015-10-20 2017-04-26 台湾积体电路制造股份有限公司 多堆叠的多输出封装件中的晶圆级屏蔽罩及其形成方法
CN105514087A (zh) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 双面扇出型晶圆级封装方法及封装结构

Also Published As

Publication number Publication date
CN107622957A (zh) 2018-01-23

Similar Documents

Publication Publication Date Title
CN107622957B (zh) 双面SiP的三维封装结构的制造方法
TWI533412B (zh) 半導體元件封裝結構及其形成方法
CN107749411B (zh) 双面SiP的三维封装结构
TWI417995B (zh) 具有晶粒埋入式以及雙面覆蓋重增層之基板結構及其方法
US8350377B2 (en) Semiconductor device package structure and method for the same
US6627998B1 (en) Wafer scale thin film package
KR101690549B1 (ko) 내장 칩 패키지
TWI413231B (zh) 射頻模組封裝
CN101252125A (zh) 具减缩结构的复数晶粒封装结构与其形成方法
US20080157327A1 (en) Package on package structure for semiconductor devices and method of the same
TWI409923B (zh) 具有晶粒埋入式以及雙面覆蓋重增層之基板結構及其方法
US7038316B2 (en) Bumpless die and heat spreader lid module bonded to bumped die carrier
TW200931628A (en) Stacking die package structure for semiconductor devices and method of the same
CN101211903A (zh) 射频模块封装结构及其形成方法
JP2008252087A (ja) 半導体装置パッケージ構造及びその方法
JP5588620B2 (ja) ウェーハ・レベル・パッケージ及びその形成方法
CN101325188A (zh) 具双面增层之晶圆级半导体封装及其方法
KR20080089311A (ko) Ｗｌｐ용 다이 수용 스루홀 및 양 표면 위에 이중 사이드빌드업층들을 갖는 반도체 디바이스 패키지 및 그 방법
KR102506101B1 (ko) 반도체 디바이스 및 제조 방법
CN115132593A (zh) 一种三维封装结构及其制备方法
JP2020191323A (ja) 半導体パッケージ用配線基板及び半導体パッケージ、並びにそれらの製造方法
CN101335265A (zh) 具有晶粒功能之半导体封装结构
WO2024016525A1 (zh) 底部封装体及其制作方法以及堆叠封装结构及其制作方法
KR101341619B1 (ko) 반도체 패키지 및 그의 제조 방법
JP2005005632A (ja) チップ状電子部品及びその製造方法、並びにその実装構造

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant