CN107622957B - The manufacturing method of the three-dimension packaging structure of two-sided SiP - Google Patents
The manufacturing method of the three-dimension packaging structure of two-sided SiP Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/30—Technical effects
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Abstract
本发明涉及一种双面SiP的三维封装结构的制造方法，所述方法包括以下步骤：步骤一、取一临时载板；步骤二、在临时载板上贴装核心转接板；步骤三、在核心转接板正面贴装扇出型晶圆级封装结构、第一被动元件和第一3D导电部件；步骤四、塑封作业；步骤五、机械研磨露出第一3D导电部件并移除临时载板；步骤六、核心转接板背面贴装芯片、第二被动元件和第二3D导电部件；步骤七、塑封，植球作业；步骤八、下一步封装制程或者切割成单颗产品，完成测试。本发明能够使用预制的窄中心距3D导电部件成为堆叠封装的支撑结构，可以降低封装模组的尺寸高度，提高封装模组的高频性能以及高度设计和翘曲控制的灵活性。
The invention relates to a method for manufacturing a three-dimensional packaging structure of double-sided SiP. The method includes the following steps: step 1, taking a temporary carrier board; step 2, mounting a core adapter board on the temporary carrier board; step 3, Mount the fan-out wafer-level packaging structure, the first passive component and the first 3D conductive component on the front of the core adapter board; step 4, plastic encapsulation; step 5, mechanical grinding to expose the first 3D conductive component and remove the temporary load board; Step 6, mount the chip on the back of the core adapter board, the second passive component and the second 3D conductive component; Step 7, plastic packaging, ball planting operation; Step 8, the next step of the packaging process or cutting into a single product, and complete the test . The present invention can use the prefabricated narrow center distance 3D conductive components as the supporting structure of the stack package, which can reduce the size and height of the package module, improve the high frequency performance of the package module and the flexibility of height design and warpage control.
Description
技术领域technical field
本发明涉及一种双面SiP的三维封装结构的制造方法，属于半导体封装技术领域。The invention relates to a method for manufacturing a double-sided SiP three-dimensional packaging structure, which belongs to the technical field of semiconductor packaging.
背景技术Background technique
根据半导体技术的发展，电子器件变得微型化并且越来越轻以满足用户的需求，因此，用于实现与单个封装相同或不同的半导体芯片的多芯片封装技术得到增强。与半导体芯片所实现的封装相比，多芯片封装就封装大小或重量以及安装过程而言是有利的，具体地讲，多芯片封装主要应用于要求微型化和减重的便携式通信终端。According to the development of semiconductor technology, electronic devices have become miniaturized and lighter to meet users' needs, and thus, multi-chip packaging technology for realizing the same or different semiconductor chips from a single package has been enhanced. The multi-chip package is advantageous in terms of package size or weight and mounting process compared to a package realized by a semiconductor chip, and in particular, the multi-chip package is mainly applied to a portable communication terminal requiring miniaturization and weight reduction.
在这些多芯片封装中，封装基板堆叠在另一个封装基板上的层叠型封装被称为堆叠封装（package on package，以下称为“PoP” ）。由于随着半导体封装技术的发展，半导体封装的容量已变得更高，厚度变得更薄并且尺寸变得更小，堆叠的芯片数量最近已经增大。Among these multi-chip packages, a stacked package in which package substrates are stacked on another package substrate is called a package on package (hereinafter referred to as “PoP”). Since semiconductor packages have become higher in capacity, thinner in thickness, and smaller in size with the development of semiconductor packaging technology, the number of chips to be stacked has recently increased.
常规的层叠封装采用焊料球印刷工艺和回流工艺，问题在于，当增大焊料球的尺寸或高度以便增大封装之间的距离时，焊料球会产生开裂或破碎。Conventional package-on-packages employ a solder ball printing process and a reflow process, and the problem is that when the size or height of the solder balls is increased to increase the distance between packages, the solder balls are cracked or broken.
另外随着封装制程中的高密度线路、多种封装材料的使用、以及各种芯片以及功能器件的使用，使得整个封装体很复杂，各种材质的搭配不易平衡，容易导致整体的翘曲变形。In addition, with the high-density circuits in the packaging process, the use of various packaging materials, and the use of various chips and functional devices, the entire package is very complicated, and the matching of various materials is not easy to balance, which may easily lead to overall warping and deformation. .
发明内容Contents of the invention
本发明所要解决的技术问题是针对上述现有技术提供一种双面SiP的三维封装结构的制造方法，它能够使用预制的窄中心距3D导电部件成为堆叠封装的支撑结构，模组中使用薄型晶圆级封装和其他器件的组合，可以降低封装模组的尺寸高度，提高封装模组的高频性能以及高度设计和翘曲控制的灵活性。The technical problem to be solved by the present invention is to provide a method for manufacturing a double-sided SiP three-dimensional packaging structure in view of the above-mentioned prior art, which can use prefabricated narrow-center-distance 3D conductive components as a support structure for stacked packaging, and thin The combination of wafer-level packaging and other devices can reduce the size and height of the packaging module, improve the high-frequency performance of the packaging module, and the flexibility of height design and warpage control.
本发明解决上述问题所采用的技术方案为：一种双面SiP的三维封装结构的制造方法，所述方法包括如下步骤：The technical solution adopted by the present invention to solve the above problems is: a method for manufacturing a three-dimensional packaging structure of double-sided SiP, said method comprising the following steps:
步骤一、取一临时载板；Step 1. Take a temporary carrier board;
步骤二、在临时载板上贴装核心转接板；Step 2. Mount the core adapter board on the temporary carrier board;
步骤三、在核心转接板正面贴装扇出型晶圆级封装结构、第一被动元件和第一3D导电部件，第一3D导电部件布置于扇出型晶圆级封装结构和第一被动元件的外围；Step 3: Mount the fan-out wafer-level packaging structure, the first passive component and the first 3D conductive component on the front of the core interposer board, and the first 3D conductive component is arranged on the fan-out wafer-level packaging structure and the first passive component. the periphery of the component;
步骤四、核心转接板正面进行塑封作业；Step 4: Perform plastic sealing on the front of the core adapter board;
步骤五、机械研磨露出第一3D导电部件并移除临时载板；Step 5, mechanically grinding to expose the first 3D conductive part and removing the temporary carrier;
步骤六、核心转接板背面贴装芯片、第二被动元件和第二3D导电部件，第二3D导电部件布置于芯片和第二被动元件的外围；Step 6, mount the chip, the second passive component and the second 3D conductive component on the back of the core adapter board, and arrange the second 3D conductive component on the periphery of the chip and the second passive component;
步骤七、核心转接板正面进行塑封，植球作业；Step 7. The front of the core adapter board is plastic-sealed and the ball is planted;
步骤八、下一步封装制程或者整体进行切割成单颗产品，完成测试。Step 8, the next step is the packaging process or the whole is cut into a single product to complete the test.
步骤一中的临时载板使用硅或者玻璃晶圆/板材。The temporary carrier in step 1 uses silicon or glass wafers/plates.
步骤一中的脱膜层使用树脂类薄膜或者惰性材料层或者多层惰性金属层。The release layer in step 1 uses a resin film or an inert material layer or a multi-layer inert metal layer.
树脂类薄膜采用HD3000系列；惰性材料层采用SiO2或SiN；多层惰性金属层采用Cu/Ti 或Cu/NiV/Ti。The resin film adopts HD3000 series; the inert material layer adopts SiO2 or SiN; the multilayer inert metal layer adopts Cu/Ti or Cu/NiV/Ti.
步骤二中的核心转接板是由晶圆级或板级制作而成的多层线路板，厚度＜100um，细间距≤15um。The core interposer in step 2 is a multi-layer circuit board manufactured at the wafer level or board level, with a thickness of <100um and a fine pitch of ≤15um.
步骤三中的第一3D导电部件和步骤六中的第二3D导电部件均可连接在一起贴装或单独贴装。The first 3D conductive part in step three and the second 3D conductive part in step six can be connected together or mounted separately.
贴装方式采用焊锡膏、点助焊剂或导电/不导电胶的方式。Mounting method adopts solder paste, dot flux or conductive/non-conductive glue.
步骤五中移除临时载板使用激光扫描、机械研磨或者化学蚀刻的方式。In step five, the temporary carrier is removed by laser scanning, mechanical grinding or chemical etching.
步骤五中的机械研磨在移除临时载板前进行或在移除临时载板后进行。The mechanical grinding in step 5 is performed before or after removing the temporary carrier.
与现有技术相比，本发明的优点在于：Compared with the prior art, the present invention has the advantages of:
1、封装模组中使用晶圆级或者面板级制作的重布线核心转接板以及内部使用的晶圆级封装结构可以降低整体封装模组的高度和尺寸；1. The use of wafer-level or panel-level rewiring core adapter boards and internally used wafer-level packaging structures in packaging modules can reduce the height and size of the overall packaging module;
2、主芯片、其他芯片（如MEMS、控制芯片、集成无源器件）采用晶圆级封装结构，使用低损耗的绝缘材料，可以提高高频性能；另外晶圆级封装结构可以单独另外制作，可以在测试合格之后应用于本模组封装中，可防止多芯片单独植入SiP模组却在最终测试不合格，可以减少芯片损失，且保证最终产品的高良率；2. The main chip and other chips (such as MEMS, control chips, integrated passive devices) adopt a wafer-level packaging structure, using low-loss insulating materials, which can improve high-frequency performance; in addition, the wafer-level packaging structure can be made separately, It can be applied to this module package after passing the test, which can prevent multiple chips from being implanted into the SiP module but fail the final test, reduce chip loss, and ensure a high yield of the final product;
3、可以提高整体封装模组的高度设计的灵活性和翘曲控制的稳定性：上下部分的3D导电部件是预制单独设计的，可以有全金属柱和金属柱中填充树脂的组合，或金属平行侧壁中填充复合材料的组合；具有灵活的CTE设计可以来控制整体结构的翘曲，其高度设计也可以进行灵活的设计；扇出型晶圆级封装也可以通过调整塑封的厚度和凸块设计的高度来调整翘曲度。同时金属平行侧壁中填充复合材料的组合可以提供高深度/间距比的3D低成本导电部件。3. It can improve the flexibility of the height design of the overall packaging module and the stability of warpage control: the 3D conductive parts of the upper and lower parts are prefabricated and designed separately, and can have a combination of full metal columns and metal columns filled with resin, or metal Combination of filling composite materials in parallel sidewalls; flexible CTE design can control the warpage of the overall structure, and its height design can also be flexibly designed; fan-out wafer level packaging can also be adjusted by adjusting the thickness and convexity of the plastic package The height of the block design to adjust the degree of warpage. At the same time, the combination of metal-parallel sidewalls filled with composite materials can provide 3D low-cost conductive parts with high depth/space ratio.
附图说明Description of drawings
图1~图8为本发明一种双面SiP的三维封装结构的制造方法的各工序流程图。1 to 8 are flow charts of each process of a manufacturing method of a double-sided SiP three-dimensional packaging structure of the present invention.
具体实施方式Detailed ways
以下结合附图实施例对本发明作进一步详细描述。The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
本实施例中的一种双面SiP的三维封装结构的制造方法，所述方法包括如下步骤：A method for manufacturing a double-sided SiP three-dimensional packaging structure in this embodiment, the method includes the following steps:
步骤一、参见图1，取一临时载板，并在临时载板正面贴上一层脱膜层；Step 1, see Figure 1, take a temporary carrier, and paste a release layer on the front of the temporary carrier;
临时载板使用硅或者玻璃晶圆/板材，脱膜层使用树脂类薄膜如HD3000系列，或者惰性材料层如SiO2、SiN，或者多层惰性金属层Cu/Ti 或Cu/NiV/Ti 等；Silicon or glass wafers/plates are used for the temporary carrier, resin films such as HD3000 series are used for the release layer, or inert material layers such as SiO2, SiN, or multi-layer inert metal layers Cu/Ti or Cu/NiV/Ti, etc.;
步骤二、参见图2，在临时载板上的脱膜层上贴装核心转接板，或逐层沉积/涂胶/贴膜与薄膜电路成型连接从而形成多层堆叠薄膜电路；Step 2, see Figure 2, mount the core adapter board on the release layer of the temporary carrier, or deposit/coat/stick film layer by layer and form and connect with the thin film circuit to form a multi-layer stacked thin film circuit;
核心转接板是由晶圆级或板级制作而成的多层线路板，厚度＜100um，细间距≤15um，至少两层的线路层，介电层材料相同或者外层使用低CTE（热膨胀系数）、高杨氏模量（E）的材料，内层用高CTE（热膨胀系数）、低杨氏模量（E）的材料，以便控制翘曲度和界面分层，所有的介电层有低的介电常数和介质损耗；The core interposer board is a multi-layer circuit board made at the wafer level or board level, with a thickness of <100um, a fine pitch of ≤15um, at least two layers of circuit layers, and the dielectric layer material is the same or the outer layer uses low CTE (thermal expansion Coefficient), high Young's modulus (E) material, inner layer with high CTE (thermal expansion coefficient), low Young's modulus (E) material, in order to control warpage and interface delamination, all dielectric layers Has low dielectric constant and dielectric loss;
步骤三、参见图3，在核心转接板正面贴装扇出型晶圆级封装结构、第一被动元件和第一3D导电部件，第一3D导电部件布置于扇出型晶圆级封装结构和第一被动元件的外围；Step 3, see Figure 3, mount the fan-out wafer level packaging structure, the first passive element and the first 3D conductive component on the front of the core interposer board, and the first 3D conductive component is arranged on the fan-out wafer level packaging structure and the periphery of the first passive element;
第一3D导电部件可连接在一起或单独贴装；The first 3D conductive components can be connected together or mounted separately;
贴装方式可采用焊锡膏、点助焊剂、导电/不导电胶等方式；Mounting method can use solder paste, dot flux, conductive/non-conductive adhesive, etc.;
高价值的扇出型晶圆级封装结构可经过检测合格后进行贴装，保证产品良率；The high-value fan-out wafer-level packaging structure can be mounted after passing the inspection to ensure product yield;
第一3D导电部件可以连接相邻的两个相同或者不同线路设计的单元；第一3D导电部件可采用两层或多层线路的PCB板、两层线路的MIS板或其他相似的技术；The first 3D conductive part can connect two adjacent units with the same or different circuit designs; the first 3D conductive part can use a PCB board with two or more layers of circuits, an MIS board with two layers of circuits or other similar technologies;
步骤四、参见图4，核心转接板正面进行塑封作业；Step 4, see Figure 4, perform plastic sealing on the front of the core adapter board;
步骤五、参见图5，机械研磨露出第一3D导电部件并移除临时载板；Step 5, referring to Figure 5, mechanically grinding to expose the first 3D conductive part and removing the temporary carrier;
机械研磨可在移除临时载板前进行，也可在移除临时载板后进行；Mechanical grinding can be performed before or after removing the temporary carrier;
移除临时载板可使用激光扫描、机械研磨或者化学蚀刻的方式；Laser scanning, mechanical grinding or chemical etching can be used to remove the temporary carrier;
步骤六、参见图6，核心转接板背面贴装芯片、第二被动元件和第二3D导电部件，第二3D导电部件布置于芯片和第二被动元件的外围；Step 6. Referring to FIG. 6 , mount the chip, the second passive component and the second 3D conductive component on the back of the core adapter board, and the second 3D conductive component is arranged on the periphery of the chip and the second passive component;
价值高的芯片可在最后贴装，贴装芯片期间可以进行OS（开短路）检测，以避免高价值芯片的损失；Chips with high value can be mounted at the end, and OS (open short circuit) detection can be performed during chip mounting to avoid the loss of high-value chips;
第二3D导电部件可连接在一起或单独贴装；The second 3D conductive components can be connected together or mounted separately;
步骤七、参见图7，核心转接板正面进行塑封，植球作业；Step 7, see Figure 7, the front of the core adapter board is plastic-sealed, and the ball is planted;
步骤八、参见图8，下一步封装制程或者整体进行切割成单颗产品，完成测试。Step 8, see Figure 8, the next step is the encapsulation process or the whole is cut into a single product to complete the test.
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