CN107579115A - A silicon carbide light-triggered thyristor with a double-layer thin n-base region and its manufacturing method - Google Patents

Abstract

The invention discloses a silicon carbide light-triggered thyristor with a double-layer thin n-base region, which comprises a SiC substrate, on which a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, and a second epitaxial layer are sequentially fabricated. The fourth epitaxial layer, the fifth epitaxial layer, and the sixth epitaxial layer, the sixth epitaxial layer is divided into a plurality of bosses; a junction terminal is embedded in the upper part of the third epitaxial layer, and the junction terminal is located between the fourth epitaxial layer and the fifth epitaxial layer In addition to the end; it also includes an insulating dielectric film, and the insulating dielectric film covers the side walls of each boss, the surface of the fifth epitaxial layer between each boss, and the side walls and surfaces of the junction terminal mesa; each boss of the sixth epitaxial layer The upper surface of the stage is covered with an anode; the lower surface of the SiC substrate is covered with a cathode. The invention also discloses a manufacturing method of the silicon carbide light-triggered thyristor with double-layer thin n-base regions. The invention has a unique structure and excellent device performance; the manufacturing method of the invention is convenient for implementation.

Description

A silicon carbide light-triggered thyristor with a double-layer thin n-base region and its manufacturing method

technical field

The invention belongs to the technical field of semiconductor devices, and relates to a silicon carbide light-triggered thyristor with a double-layer thin n-base region, and also relates to a manufacturing method of the silicon carbide light-triggered thyristor with a double-layer thin n-base region.

Background technique

Silicon carbide (SiC) material has the advantages of large band gap, high thermal conductivity, high critical avalanche breakdown electric field strength, high saturated carrier drift velocity and good thermal stability, and is an ideal material for manufacturing power semiconductor devices. Compared with silicon devices of the same level, SiC high-voltage devices have lower on-state voltage drop, higher operating frequency, lower power consumption, smaller volume and better high temperature resistance characteristics, and are more suitable for power applications electronic circuit. As a kind of SiC high-voltage device, SiC thyristor has the advantages of high blocking voltage, low on-state voltage, large safe operating area (SOA) and no reliability problem of gate oxide layer. It can break through the physical limit of silicon thyristor and effectively improve Power Density and Efficiency of High Voltage Direct Current Transmission (HVDC) and Smart Grid Power Transmission Systems. Compared with SiC electronically controlled thyristor (SiC ETT), SiC light-triggered thyristor (SiC LTT) has more advantages in simplifying the driving circuit and anti-electromagnetic interference.

Due to the higher ionization energy (0.19eV) of aluminum acceptors in SiC, the p-type SiC material has higher resistivity. In order to avoid the use of p-type substrates with high resistivity, SiC thyristors with a withstand voltage of 10kV and below generally need to adopt a p-type long base structure. For SiC thyristors with a p-type long base structure, the hole concentration in the p ⁺ emitter region is low, which affects the injection efficiency of the p ⁺ -n emitter junction, resulting in the problem of large turn-on delay time in SiCLTT. In order to shorten the turn-on delay time, an ultraviolet laser pulse is generally used to trigger the SiCLTT, but the laser source has the problems of large volume and low efficiency. In view of this, ultraviolet light-emitting diodes (UV LEDs) are used to trigger SiC LTTs. However, the light power density of UV LEDs is small, and it is difficult to meet the triggering requirements of high-voltage SiC LTTs.

N.Dheilly et al. published an article "Optical triggering of SiC thyristors using UV LEDs" in Electronics Letters in 2011. In this paper, a UV LED with a wavelength of 330nm was used to trigger SiC LTT. Only then began to decline. The work of N.Dheilly et al. realized the triggering of UV LEDs of SiC LTT for the first time, but the delay time of SiC LTT turn-on is relatively large, which still needs to be improved.

S.L.Rumyantsev et al. published the article "Optical triggering of high-voltage (18kV-class) 4H-SiC thyristors" in Semiconductor Science and Technology in 2013. In this paper, the amplified gate structure was introduced into SiC LTT for the first time. By introducing the amplified gate, the trigger The optical power density is reduced, but the problem of large turn-on delay time still exists.

Therefore, in view of the above technical problems, it is necessary to provide a high-performance, high-feasibility technical solution for improving the problem of large turn-on delay time of UV LED triggering SiC LTT.

Contents of the invention

The purpose of the present invention is to provide a silicon carbide light-triggered thyristor with a double-layer thin n-base region, which solves the problems of low injection efficiency of the existing SiC LTT p ⁺ -n emitter junction, large turn-on delay time, and high trigger optical power question.

Another object of the present invention is to provide a method for manufacturing the silicon carbide light-triggered thyristor with a double-layer thin n-base region.

The technical solution adopted in the present invention is a silicon carbide light-triggered thyristor with a double-layer thin n-base region, including a SiC substrate, the material of which is n-type 4H-SiC,

A first epitaxial layer, that is, an n ⁺ emitter region, is formed on the SiC substrate, and the material of the first epitaxial layer is n-type 4H-SiC;

A second epitaxial layer, that is, a p ⁺ buffer layer, is formed on the first epitaxial layer, and the material of the second epitaxial layer is p-type 4H-SiC;

A third epitaxial layer, that is, a p ^- long base region, is fabricated on the second epitaxial layer, and the material of the third epitaxial layer is p-type 4H-SiC;

A fourth epitaxial layer is formed on the third epitaxial layer, that is, the lower thin n-base region, and the material of the fourth epitaxial layer is n-type 4H-SiC;

A fifth epitaxial layer, namely the upper thin n ^- base region, is formed on the fourth epitaxial layer, and the material of the fifth epitaxial layer is n-type 4H-SiC;

On the fifth epitaxial layer, a sixth epitaxial layer, that is, the p ⁺ emission region, is divided into a plurality of bosses with the same size, and the side wall of each boss is flat, and the material of the sixth epitaxial layer is p-type 4H-SiC;

A junction terminal is embedded in the upper part of the third epitaxial layer, and the junction terminal is located outside the ends of the fourth epitaxial layer and the fifth epitaxial layer, and is p-type;

It also includes an insulating dielectric film, the insulating dielectric film covers the side walls of each boss of the sixth epitaxial layer, the surface of the fifth epitaxial layer between each boss, and the side walls and surfaces of the junction terminal mesa, and the side walls and surfaces of the junction terminals are located between the bosses. The height of part is lower than the upper end surface of the boss;

An anode is covered on the upper surface of each boss of the sixth epitaxial layer; a cathode is covered on the lower surface of the SiC substrate.

Another technical solution of the present invention is a method for manufacturing a silicon carbide light-triggered thyristor with a double-layer thin n-base region, which is implemented according to the following steps:

Step 1: using the CVD method to sequentially grow the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer, the fifth epitaxial layer, and the sixth epitaxial layer on the upper surface of the SiC substrate;

The doping type of the SiC substrate is n-type, the thickness is 1 μm-500 μm, the doping concentration is 1×10 ¹⁴ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the first epitaxial layer is n-type, the thickness is 0.1 μm-3 μm, the doping concentration is 5×10 ¹⁷ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the second epitaxial layer is p-type, the thickness is 0.1 μm-3 μm, the doping concentration is 5×10 ¹⁶ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the third epitaxial layer is p-type, the thickness is 1 μm-500 μm, the doping concentration is 1×10 ¹⁴ -3×10 ¹⁶ cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the fourth epitaxial layer is n-type, the thickness is 0.1 μm-2.4 μm, the doping concentration is 1×10 ¹⁶ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the fifth epitaxial layer is n ^- type, the thickness is 0.1 μm-2.4 μm, the doping concentration is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the sixth epitaxial layer is p-type, the thickness is 0.1 μm-6 μm, the doping concentration is 1×10 ¹⁸ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

Step 2: Using exposure technology on the sixth epitaxial layer to obtain a patterned surface;

Step 3: Etching is carried out on the patterned surface, and a plurality of bosses of the sixth epitaxial layer are formed by dry etching, the distance between each boss is 0.1 μm-1 cm, and the height of each boss is 0.1 μm-6.1 μm, the height of each boss is not less than the thickness of the sixth epitaxial layer;

Step 4: Use exposure technology on the upper surface of the epitaxial layer to obtain a patterned surface;

Step 5: Etching on the patterned surface, using dry etching to form a terminal mesa, the height of the terminal mesa is 0.2 μm-500 μm, and its height is not less than the sum of the thickness of the fourth epitaxial layer and the fifth epitaxial layer;

Step 6: Perform ion implantation on the device obtained in step 5, and form a junction terminal on the terminal mesa downward, and the implanted ions are aluminum ions or boron ions; the thickness of the junction terminal is not greater than 1 μm, and the width is 1 μm-1mm; the energy of ion implantation is 100eV-700KeV, the implantation temperature is 0°C-900°C, and the implantation dose is 1×10 ¹⁰ -1×10 ¹⁶ cm ^-2 ;

Step 7: remove the photolithography mask, perform high-temperature annealing, the high-temperature annealing temperature is 900°C-2100°C, and the annealing atmosphere is an inert gas atmosphere;

Step 8: growing an insulating dielectric film on the upper surface of the device, the insulating dielectric film covers the sidewalls of the bosses of the sixth epitaxial layer, the surface of the fifth epitaxial layer between the bosses, and the sidewalls and surfaces of the terminal mesas; the insulating The thickness of the dielectric film is 0.1μm-2μm;

Step 9: Etching the insulating dielectric film, removing the insulating dielectric film on the upper surface of each boss of the sixth epitaxial layer, and retaining other parts of the insulating dielectric film;

Step 10: Depositing anode metal on the surface of the boss of the sixth epitaxial layer;

Step 11: Deposit cathode metal on the back side of the SiC substrate;

Step 12: rapid thermal annealing of the product obtained in step 11 under the protection of nitrogen or an inert gas, the annealing temperature is 500°C-1200°C, and the annealing time is 10 seconds-10 minutes;

Step 13: Depositing an anode pressure solder bump on the anode metal;

Step 14: Deposit the cathode pad on the cathode metal to complete the preparation.

The beneficial effect of the present invention is that the thin n base region of the SiC LTT has a double-layer structure, which enhances the injection efficiency of the p ⁺ emitter region, improves the problem of small gain of the upper pnp transistor due to the low hole concentration, and shortens the SiC LTT The turn-on delay time provides a feasible technical solution for UV LED triggering SiC LTT.

Description of drawings

Fig. 1 is a schematic diagram of the structure of a SiC LTT with a double-layer thin n-base region according to an embodiment of the present invention;

Fig. 2 is a schematic diagram of the main device structure of the present invention applied to 10kV 4H-SiC LTT (part of Fig. 1);

Fig. 3 SiC LTT turn-on delay time of the present invention and the doping concentration curve of the sixth epitaxial layer;

Fig. 4 is a schematic diagram of the device structure after step 1 of the method of the present invention is completed;

Fig. 5 is a schematic diagram of the device structure after step 3 of the method of the present invention is completed;

Fig. 6 is a schematic diagram of the device structure after step 5 of the method of the present invention is completed;

Fig. 7 is a schematic diagram of the device structure after step 7 of the method of the present invention is completed;

Fig. 8 is a schematic diagram of the device structure after step 9 of the method of the present invention is completed;

FIG. 9 is a schematic diagram of the device structure after step 12 of the method of the present invention is completed.

In the figure, 1. substrate, 2. first epitaxial layer, 3. second epitaxial layer, 4. third epitaxial layer, 5. fourth epitaxial layer, 6. fifth epitaxial layer, 7. sixth epitaxial layer, 8. Insulating dielectric film, 9. Anode, 10. Junction terminal, 11. Cathode.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

Referring to Fig. 1, the SiC LTT structure with a double-layer thin n-base region of the present invention is,

Including a SiC substrate 1, the material of the SiC substrate 1 is n-type 4H-SiC, the thickness of the SiC substrate 1 is 1 μm-500 μm, and the upper surface area of the SiC substrate 1 is 1 μm ² -2000 cm ² ;

On the SiC substrate 1, a first epitaxial layer 2, that is, an n ⁺ emitter region, is formed. The material of the first epitaxial layer 2 is n-type 4H-SiC, and the thickness of the first epitaxial layer 2 is 0.1 μm-3 μm. The upper end surface area of the first epitaxial layer 2 is 1 μm ² -2000 cm ² ;

On the first epitaxial layer 2, there is a second epitaxial layer 3, that is, a p ⁺ buffer layer, the material of the second epitaxial layer 3 is p-type 4H-SiC, and the thickness of the second epitaxial layer 3 is 0.1 μm-3 μm , the surface area of the upper end of the second epitaxial layer 3 is 1 μm ² -2000 cm ² ;

A third epitaxial layer 4 is formed on the second epitaxial layer 3, that is, a p ^- long base region, the material of the third epitaxial layer 4 is p-type 4H-SiC, and the thickness of the third epitaxial layer 4 is 1 μm-500 μm , the surface area of the upper end of the third epitaxial layer 4 is 1 μm ² -2000 cm ² ;

A fourth epitaxial layer 5 is formed on the third epitaxial layer 4, that is, the lower thin n-base region. The material of the fourth epitaxial layer 5 is n-type 4H-SiC, and the thickness of the fourth epitaxial layer 5 is 0.1 μm- 2.4 μm, the surface area of the upper end of the fourth epitaxial layer 5 is 1 μm ² -2000 cm ² ;

A fifth epitaxial layer 6 is formed on the fourth epitaxial layer 5, that is, the upper thin n ^- base region, the material of the fifth epitaxial layer 6 is n-type 4H-SiC, and the thickness of the fifth epitaxial layer 6 is 0.1 μm -2.4 μm, the upper surface area of the fifth epitaxial layer 6 is 1 μm ² -2000 cm ² ;

On the fifth epitaxial layer 6, a sixth epitaxial layer 7, that is, the p ⁺ emission region, is formed, which is divided into a plurality of bosses with the same size, and the side wall of each boss is a plane, and the material of the sixth epitaxial layer 7 It is p-type 4H-SiC, the thickness of the sixth epitaxial layer 7 is 0.1 μm-6 μm, and the surface area of the upper end of a single boss is 1 μm ² -2000 cm ² ;

A junction terminal 10 is inlaid on the upper part of the third epitaxial layer 4, and the junction terminal 10 is located outside the ends of the fourth epitaxial layer 5 and the fifth epitaxial layer 6, is p-type, has a thickness not greater than 1 μm, and a width of 1 μm-1 mm;

It also includes an insulating dielectric film 8, the insulating dielectric film 8 covers the side walls of each boss of the sixth epitaxial layer 7, the surface of the fifth epitaxial layer 6 between each boss, and the side walls and surfaces of the mesa of the junction terminal 10, located in each The height of the part between the bosses is lower than the upper surface of the bosses, and its thickness is 0.1 μm-2 μm;

The upper surface of each boss of the sixth epitaxial layer 7 is covered with an anode 9, the anode 9 is composed of an anode metal and an anode pressure welding block, and the anode pressure welding block covers the upper surface of the anode metal, with a thickness of 0.1 μm-100 μm;

The lower end surface (back side) of the SiC substrate 1 is covered with a cathode 11, the cathode 11 is composed of a cathode metal and a cathode pad, and the cathode pad covers the back side of the cathode metal with a thickness of 0.1 μm-100 μm.

Each boss of the sixth epitaxial layer 7 is one of interdigitated structure, parallel strip shape, circular ring, square or involute mesa, or a combination thereof, and the distance between each boss is 0.1 μm-1 cm. The height of the mesa is 0.1 μm-6.1 μm, and the height of each raised mesa is not less than the thickness of the p ⁺ emitting region.

The material of the upper thin n base region and the lower thin n base region is n-type, wherein the doping concentration of the upper thin n base region is lower than that of the lower thin n base region.

The material of the above-mentioned anode metal, cathode metal, anode welding block and cathode welding block is one of Ti, Ni, W, Ta, Al, Ag or Au, or Ti, Ni, W, Ta, Al, Ag, Au A combination of any two or more of them.

Due to the above arrangement of the lower thin n-base region and the upper thin n ^- base region, this application is called SiC LTT with double-layer thin n-base region.

The manufacturing method of the SiC LTT with double-layer thin n-base region of the present invention is implemented according to the following steps:

Step 1: Using the CVD method, grow the first epitaxial layer 2, the second epitaxial layer 3, the third epitaxial layer 4, the fourth epitaxial layer 5, the fifth epitaxial layer 6, and the sixth epitaxial layer upwards on the upper surface of the SiC substrate 1. Epitaxial layer 7, see Figure 4;

The doping type of SiC substrate 1 is n-type, the thickness is 1 μm-500 μm, the doping concentration is 1×10 ¹⁴ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the first epitaxial layer 2 is n-type, the thickness is 0.1 μm-3 μm, its doping concentration is 5×10 ¹⁷ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000 cm ² ;

The doping type of the second epitaxial layer 3 is p-type, the thickness is 0.1 μm-3 μm, the doping concentration is 5×10 ¹⁶ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000 cm ² ;

The doping type of the third epitaxial layer 4 is p-type, the thickness is 1 μm-500 μm, the doping concentration is 1×10 ¹⁴ -3×10 ¹⁶ cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ;

The doping type of the fourth epitaxial layer 5 is n-type, the thickness is 0.1 μm-2.4 μm, the doping concentration is 1×10 ¹⁶ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000 cm ² ;

The doping type of the fifth epitaxial layer 6 is n ^- type (the - in the n ^- type is a superscript), the thickness is 0.1 μm-2.4 μm, and the doping concentration is 1×10 ¹⁴ -1×10 ¹⁷ cm ^{− 3} , the upper surface area is 1μm ² -2000cm ² ;

The doping type of the sixth epitaxial layer 7 is p-type, the thickness is 0.1 μm-6 μm, the doping concentration is 1×10 ¹⁸ -1×10 ²² cm ⁻³ , and the upper surface area is 1 μm ² -2000 cm ² .

Step 2: using an exposure technique on the sixth epitaxial layer 7 to obtain a patterned surface, the exposure technique being optical exposure or electron beam exposure;

Step 3: Etching on the patterned surface, using dry etching to form a plurality of bosses of the sixth epitaxial layer 7, the bosses are interdigitated, parallel strips, circular, square or One of the involute-shaped mesa or its combined shape, the distance between each boss is 0.1 μm-1 cm, the height of each boss is 0.1 μm-6.1 μm, and the height of each boss is not less than the thickness of the sixth epitaxial layer 7, see Figure 5;

Step 4: Using exposure technology on the upper surface of the epitaxial layer to obtain a patterned surface, the exposure technology is optical exposure or electron beam exposure; (Here, after the above step 3, repeat step 2 on the upper surface of the entire device structure process, the difference is only in the surface pattern obtained by exposure);

Step 5: Etching on the patterned surface, using dry etching to form a terminal mesa, the height of the terminal mesa is 0.2 μm-500 μm, and its height is not less than the sum of the thicknesses of the fourth epitaxial layer 5 and the fifth epitaxial layer 6 , see FIG. 6; (after the treatment in step 5, the upper surface of the end of the third epitaxial layer 4 is exposed);

Step 6: Perform ion implantation on the device obtained in step 5, and form a junction terminal 10 downward on the terminal mesa, and the implanted ions are aluminum ions or boron ions; the thickness of the junction terminal 10 is not greater than 1 μm, and the width is 1 μm-1 mm; The energy is 100eV-700KeV, the implantation temperature is 0°C-900°C, and the implantation dose is 1×10 ¹⁰ -1×10 ¹⁶ cm ^-2 ;

Step 7: remove the photoresist mask, the photoresist mask is photoresist, silicon oxide, silicon nitride and a combination thereof; the method of removing the photoresist mask is to remove by rinsing with an acidic or alkaline solution or by Removal by dry etching technology; perform high-temperature annealing, the high-temperature annealing temperature is 900°C-2100°C, and the annealing atmosphere is an inert gas atmosphere, see Figure 7;

Step 8: growing an insulating dielectric film 8 on the upper surface of the device, the insulating dielectric film 8 covers the sidewalls of the bosses of the sixth epitaxial layer 7, the surface of the fifth epitaxial layer 6 between the bosses, and the sidewalls and surfaces of the terminal mesas ; The insulating dielectric film 8 is grown by high temperature oxidation, chemical vapor deposition, physical vapor deposition and combinations thereof, and its thickness is 0.1 μm-2 μm;

Step 9: Etching the insulating dielectric film 8, removing the insulating dielectric film 8 on the upper surface of each boss of the sixth epitaxial layer 7, and retaining other parts of the insulating dielectric film 8, see FIG. 8;

Step 10: Depositing anode metal on the surface of the boss of the sixth epitaxial layer 7;

Step 11: Deposit cathode metal on the back side of SiC substrate 1;

Step 12: Rapid thermal annealing of the product obtained in step 11 under the protection of nitrogen or an inert gas, the annealing temperature is 500°C-1200°C, and the annealing time is 10 seconds-10 minutes, see Figure 9;

Step 13: Depositing an anode pressure solder bump on the anode metal;

Step 14: Deposit the cathode pad on the cathode metal to complete the preparation and obtain the finished SiCLTT with double-layer thin n-base region, as shown in FIG. 1 .

Example 1

Hereinafter, the present invention will be further described in detail by taking 10kV 4H-SiC LTT as an example.

The main device structure of this embodiment is shown in Figure 2, the main device includes a SiC substrate 1, and a first epitaxial layer 2, a second epitaxial layer 3, a third epitaxial layer 4, a first epitaxial layer deposited on the SiC substrate 1 Four epitaxial layers 5, fifth epitaxial layer 6, sixth epitaxial layer 7, insulating dielectric film 8 covering the upper surface of the fifth epitaxial layer 6 and the sidewall of the sixth epitaxial layer 7, an anode 9 located on the surface of the sixth epitaxial layer 7 , the cathode 11 located on the back side of the SiC substrate 1 .

The preparation method of the 4H-SiC LTT is specifically implemented according to the following steps:

Step 1. Fabricate a SiC substrate 1 made of 4H-SiC.

Step 2, using the low pressure hot wall chemical vapor deposition method to sequentially grow the first, second, third, fourth, fifth and sixth epitaxial layers (4H-SiC) on the SiC substrate 1 to form 4H-SiC Epitaxial structure made of SiCLTT; the concentration and thickness of the first, second, third, fourth, fifth, and sixth epitaxial layers are 5×18cm ^-3 /1μm, 5×17cm ^-3 /2μm, 2×14cm respectively ^-3 /80μm, 1×17cm ^-3 /1.5μm, 2×14cm ^-3 /0.5μm, 2×18cm- ³ /2.5μm.

Step 3, using exposure technology on the sixth epitaxial layer 7 to obtain a patterned surface;

Step 4. Perform dry etching on the patterned surface to form parallel strip-shaped bosses, the width of the bosses is 4 μm, the distance between the bosses is 6 μm, and the height of the bosses is 2.5 μm;

Step 5, growing an insulating dielectric film 8 on the upper surface of the device by chemical vapor deposition, the insulating dielectric film 8 covers the side walls of the bosses and the upper surface of the fifth epitaxial layer 6 between the bosses, with a thickness of 0.5 μm;

Step 6: performing dry etching on the insulating dielectric film 8, removing the insulating dielectric film 8 on the upper surface of the boss, and retaining the insulating dielectric film 8 on other parts;

Step 7: deposit anodic metal Ti on the surface of the boss;

Step 8: Deposit cathode metal Ni on the back side of SiC substrate 1;

Step 9: rapid thermal annealing under argon protection, the annealing temperature is 1050°C, and the annealing time is 3min;

Step 10: Depositing an anode pressure solder bump Al on the anode metal;

Step 11: Deposit the cathode pad Al on the cathode metal to complete the preparation.

The present invention has the performance of double-layer thin n-base SiC LTT, which is verified by the following numerical simulation.

Using Sentaurus TCAD software, a numerical simulation was carried out on the turn-on characteristics of the above-mentioned 10kV SiC LTT with a double-layer thin n-base region. The device structure used in the simulation is shown in Figure 2. Through numerical simulation, the relationship between the turn-on delay time of the 10kVSiC LTT with a double-layer thin n-base region and the doping concentration of the sixth epitaxial layer 7 is shown in Figure 3. Through comparison, it can be seen that the structure of the double-layer thin n-base region can change SiC LTT turn-on delay time, the lower the concentration of the upper thin n-base region, the shorter the SiC LTT turn-on delay time.

The structure of the present invention includes a silicon carbide SiC substrate 1, and a first epitaxial layer 2, a second epitaxial layer 3, a third epitaxial layer 4, a fourth epitaxial layer 5, and a fifth epitaxial layer deposited on the silicon carbide substrate 6. The sixth epitaxial layer 7, the insulating dielectric film 8 covering the surface of the fifth epitaxial layer 6 and the sidewall of the sixth epitaxial layer 7, the anode 9 located on the surface of the sixth epitaxial layer 7, and the cathode 10 located on the back of the SiC substrate 1 . The injection efficiency of the p+ emitter is enhanced, the problem of small gain of the upper pnp transistor caused by the low hole concentration is improved, the turn-on delay time of the silicon carbide light-triggered thyristor is shortened, and it is feasible for the ultraviolet light-emitting diode to trigger the silicon carbide light-triggered thyristor technical solutions.

Claims (10)

1. A silicon carbide light-triggered thyristor with a double-layer thin n-base region, characterized in that: comprising a SiC substrate (1), the material of the SiC substrate (1) is n-type 4H-SiC, A first epitaxial layer (2), that is, an n ⁺ emitter region, is formed on the SiC substrate (1), and the material of the first epitaxial layer (2) is n-type 4H-SiC; A second epitaxial layer (3), i.e. a p ⁺ buffer layer, is formed on the first epitaxial layer (2), and the material of the second epitaxial layer (3) is p-type 4H-SiC; A third epitaxial layer (4), i.e. a p ^- long base region, is formed on the second epitaxial layer (3), and the material of the third epitaxial layer (4) is p-type 4H-SiC; A fourth epitaxial layer (5), that is, the lower thin n-base region, is formed on the third epitaxial layer (4), and the material of the fourth epitaxial layer (5) is n-type 4H-SiC; On the fourth epitaxial layer (5), a fifth epitaxial layer (6), that is, the upper thin n ^- base region, is formed, and the material of the fifth epitaxial layer (6) is n-type 4H-SiC; On the fifth epitaxial layer (6), a sixth epitaxial layer (7), that is, the p ⁺ emission region, is formed, which is divided into a plurality of bosses with the same size, and the side wall of each boss is a plane, and the sixth epitaxial layer The material of layer (7) is p-type 4H-SiC; A junction terminal (10) is embedded on the upper part of the third epitaxial layer (4), and the junction terminal (10) is located outside the ends of the fourth epitaxial layer (5) and the fifth epitaxial layer (6), and is p-type; It also includes an insulating dielectric film (8), and the insulating dielectric film (8) covers the side walls of each boss of the sixth epitaxial layer (7), the surface of the fifth epitaxial layer (6) between each boss, and the junction terminal (10 ) The height of the side wall and surface of the table, the part between each boss is lower than the upper end surface of the boss; An anode (9) is covered on the upper surface of each boss of the sixth epitaxial layer (7); a cathode (11) is covered on the lower surface of the SiC substrate (1). 2. The silicon carbide light-triggered thyristor with double-layer thin n-base region according to claim 1, characterized in that: each boss of the sixth epitaxial layer (7) is an interdigitated structure, parallel strip-shaped , one of circular, square or involute table tops, or a combination thereof; The pitch of each boss is 0.1 μm-1 cm, the height of each boss is 0.1 μm-6.1 μm, and the height of each boss is not less than the thickness of the p ⁺ emitting region. 3. The silicon carbide light-triggered thyristor with double-layer thin n-base region according to claim 1, characterized in that: the doping concentration of the upper thin n-base region is lower than that of the lower thin n-base region . 4. The silicon carbide light-triggered thyristor with a double-layer thin n-base region according to claim 1, characterized in that: the thickness of the SiC substrate (1) is 1 μm-500 μm, and the SiC substrate (1) The surface area of the upper end is 1 μm ² -2000 cm ² . 5. The silicon carbide light-triggered thyristor with double-layer thin n-base region according to claim 1, characterized in that: The thickness of the first epitaxial layer (2) is 0.1 μm-3 μm, and the upper end surface area of the first epitaxial layer (2) is 1 μm ² -2000 cm ² ; The thickness of the second epitaxial layer (3) is 0.1 μm-3 μm, and the surface area of the upper end of the second epitaxial layer (3) is 1 μm ² -2000 cm ² ; The thickness of the third epitaxial layer (4) is 1 μm-500 μm, and the surface area of the upper end of the third epitaxial layer (4) is 1 μm ² -2000 cm ² ; The thickness of the fourth epitaxial layer (5) is 0.1 μm-2.4 μm, and the surface area of the upper end of the fourth epitaxial layer (5) is 1 μm ² -2000 cm ² ; The thickness of the fifth epitaxial layer (6) is 0.1 μm-2.4 μm, and the upper end surface area of the fifth epitaxial layer (6) is 1 μm ² -2000 cm ² ; The thickness of the sixth epitaxial layer (7) is 0.1 μm-6 μm, and the surface area of the upper end of a single boss is 1 μm ² -2000 cm ² . 6. The silicon carbide light-triggered thyristor with double-layer thin n-base region according to claim 1, characterized in that: the anode (9) is composed of an anode metal and an anode welding block, and the anode welding block covers the The upper surface of the anode metal has a thickness of 0.1 μm-100 μm; the cathode (11) is composed of cathode metal and cathode welding block, and the cathode welding block covers the back of the cathode metal with a thickness of 0.1 μm-100 μm. 7. The silicon carbide light-triggered thyristor with double-layer thin n-base region according to claim 6, characterized in that: the materials of the anode metal, the cathode metal, the anode soldering block and the cathode soldering block are Ti, One of Ni, W, Ta, Al, Ag or Au, or a combination of any two or more of Ti, Ni, W, Ta, Al, Ag, Au. 8. The silicon carbide light-triggered thyristor with double-layer thin n-base region according to claim 1, characterized in that: the thickness of the insulating dielectric film (8) is 0.1 μm-2 μm. 9. The silicon carbide light-triggered thyristor with double-layer thin n-base region according to claim 1, characterized in that: the thickness of the junction terminal (10) is not greater than 1 μm, and the width is 1 μm-1 mm. 10. A method for manufacturing a silicon carbide light-triggered thyristor with a double-layer thin n-base region, characterized in that, it is implemented according to the following steps: Step 1: Using the CVD method, the first epitaxial layer (2), the second epitaxial layer (3), the third epitaxial layer (4), and the fourth epitaxial layer (5) are sequentially grown on the upper surface of the SiC substrate (1). ), the fifth epitaxial layer (6), the sixth epitaxial layer (7); The doping type of the SiC substrate (1) is n-type, the thickness is 1 μm-500 μm, the doping concentration is 1×10 ¹⁴ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ; The doping type of the first epitaxial layer (2) is n-type, the thickness is 0.1 μm-3 μm, its doping concentration is 5×10 ¹⁷ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ; The doping type of the second epitaxial layer (3) is p-type, the thickness is 0.1 μm-3 μm, its doping concentration is 5×10 ¹⁶ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000 cm ² ; The doping type of the third epitaxial layer (4) is p-type, the thickness is 1 μm-500 μm, the doping concentration is 1×10 ¹⁴ -3×10 ¹⁶ cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ; The doping type of the fourth epitaxial layer (5) is n-type, the thickness is 0.1 μm-2.4 μm, the doping concentration is 1×10 ¹⁶ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ; The doping type of the fifth epitaxial layer (6) is n ^- type, the thickness is 0.1 μm-2.4 μm, the doping concentration is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 , and the upper surface area is 1 μm ² -2000cm ² ; The doping type of the sixth epitaxial layer (7) is p-type, the thickness is 0.1 μm-6 μm, its doping concentration is 1×10 ¹⁸ -1×10 ²² cm ^-3 , and the upper surface area is 1 μm ² -2000 cm ² ; Step 2: using exposure technology on the sixth epitaxial layer (7) to obtain a patterned surface; Step 3: Etching is carried out on the patterned surface, and a plurality of bosses of the sixth epitaxial layer (7) are formed by dry etching, the distance between each boss is 0.1 μm-1 cm, and the height of each boss is 0.1 μm-1 cm. μm-6.1μm, the height of each boss is not less than the thickness of the sixth epitaxial layer (7); Step 4: Use exposure technology on the upper surface of the epitaxial layer to obtain a patterned surface; Step 5: Etching is performed on the patterned surface, and a terminal mesa is formed by dry etching. The height of the terminal mesa is 0.2 μm-500 μm, and its height is not less than that of the fourth epitaxial layer (5) and the fifth epitaxial layer (6 ) sum of thicknesses; Step 6: Perform ion implantation on the device obtained in step 5, and form a junction terminal (10) downward on the terminal mesa, the implanted ions are aluminum ions or boron ions; the thickness of the junction terminal (10) is not greater than 1 μm, and the width is 1 μm-1mm ; The ion implantation energy is 100eV-700KeV, the implantation temperature is 0°C-900°C, and the implantation dose is 1×10 ¹⁰ -1×10 ¹⁶ cm ^-2 ; Step 7: remove the photolithography mask, perform high-temperature annealing, the high-temperature annealing temperature is 900°C-2100°C, and the annealing atmosphere is an inert gas atmosphere; Step 8: growing an insulating dielectric film (8) on the upper surface of the device, the insulating dielectric film (8) covering the side walls of the bosses of the sixth epitaxial layer (7) and the surface of the fifth epitaxial layer (6) between the bosses And the side wall and surface of the terminal table; the thickness of the insulating dielectric film (8) is 0.1 μm-2 μm; Step 9: Etching the insulating dielectric film (8), removing the insulating dielectric film (8) on the upper surface of each boss of the sixth epitaxial layer (7), and retaining other parts of the insulating dielectric film (8); Step 10: Depositing anode metal on the surface of the boss of the sixth epitaxial layer (7); Step 11: Deposit cathode metal on the back side of SiC substrate (1); Step 12: rapid thermal annealing the product obtained in step 11 under the protection of nitrogen or inert gas, the annealing temperature is 500°C-1200°C, and the annealing time is 10 seconds-10 minutes; Step 13: Depositing an anode pressure solder bump on the anode metal; Step 14: Deposit the cathode pad on the cathode metal to complete the preparation.