CN107564915B - A kind of 3D nand memory part and its manufacturing method - Google Patents
A kind of 3D nand memory part and its manufacturing method Download PDFInfo
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- 238000009825 accumulation Methods 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 316
- 230000000994 depressogenic effect Effects 0.000 claims description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
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- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 23
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- 239000000463 material Substances 0.000 description 7
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- 239000012212 insulator Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The present invention provides a kind of 3D nand memory part and its manufacturing method, pillar array is formed by etched substrate, the bottom sacrificial layer for surrounding lower part is formd around pillar, insulating layer and the alternately stacked stack layer of sacrificial layer are further formed on bottom sacrificial layer, the channel hole formed in stack layer is located on pillar, the accumulation layer connecting with pillar is used to form in channel hole, channel region of the pillar as the source line selection siphunculus of accumulation layer bottom in channel hole, after bottom sacrificial layer is replaced into metal layer, metal layer is as grid, pillar is as channel region, ultimately form source line selection siphunculus device.In this method, the channel region of source line selection siphunculus is formed by etched substrate, reduce the heat demand in manufacturing process, it reduces and the device formation in peripheral circuit is impacted, simultaneously, the channel region of source line selection siphunculus keeps the lattice structure of substrate, is the channel region of high quality, improves the performance of source line selection siphunculus device.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of 3D nand memory part and its manufacture
Method.
Background technique
Nand flash memory is a kind of storage equipment more better than hard disk drive, with people pursue low in energy consumption, light weight and
The non-volatile memory product of excellent performance, is widely used in electronic product.Currently, the nand flash memory of planar structure is
The limit of nearly true extension reduces the carrying cost of every bit to further improve memory capacity, proposes 3D structure
Nand memory part.
In 3D nand memory structure, by the way of vertical stacking multilayered memory unit, the 3D of stack is realized
Nand memory part.With reference to Fig. 1,3D nand memory part includes：Insulating layer 1101 and the alternately stacked stacking of metal layer 1102
Layer 110, the channel hole in stack layer 110, the accumulation layer being formed in channel hole on epitaxial layer 122 and epitaxial layer 122, outside
Prolong and be formed with gate dielectric layer 124 on the outer wall of layer 122, accumulation layer includes the charge-trapping of ONO (Oxide-Nitride-Oxide)
The channel layer 1302 of layer 1301 and polysilicon is the filled layer 1303 of oxide between channel layer 1302.Wherein, in each channel hole
A string of storage units are formed, for this string of storage units, each layer of metal layer 1102 is control gate, the epitaxial layer 122 of bottom
Be used to form the source line selection siphunculus (SLS, Source Line Selector) of this string of storage units, the source line selection siphunculus also by
Referred to as descend gate tube or bottom gate tube.
In the manufacturing process of existing 3D nand memory part, firstly, formation insulating layer and sacrificial layer are alternately stacked
Stack layer；Then, etching stack layer is until substrate surface, forms channel hole；Then, by selective epitaxial growth process,
Epitaxial layer is formed on the bottom in channel hole；Then, accumulation layer is formed in channel hole；Later, after sacrificial layer being removed, pass through oxygen
Chemical industry skill forms the gate dielectric layer of silica on the surface of epitaxial layer, then, carries out metal filling, forms around epitaxial layer
Metal gates ultimately form source line selection siphunculus device.
During forming source line selection siphunculus device, selective epitaxial growth process is larger to heat demand, and temperature is usual
Greater than 800 DEG C, the device in peripheral circuit can be formed and be impacted.Meanwhile after etching channel hole, the surface of substrate is put down
Whole degree is poor, influences the quality of epitaxial growth, and then influence whether the performance of source line selection siphunculus device.
Summary of the invention
In view of this, improving source line the purpose of the present invention is to provide a kind of 3D nand memory part and its manufacturing method
The device performance of gate tube.
To achieve the above object, the present invention has following technical solution：
A kind of manufacturing method of 3D nand memory part, including：
Substrate is provided；
The substrate is etched, to form the depressed area with pillar array；
Gate dielectric layer is formed on pillar and depressed area surface；
The bottom sacrificial layer for surrounding pillar is formed on the gate dielectric layer of depressed area, the bottom sacrificial layer is lower than described convex
Column；
Insulating layer and the alternately stacked stack layer of sacrificial layer are formed on the bottom sacrificial layer and pillar；
The stack layer is etched, forms channel hole on the region for corresponding to pillar, the pillar is source line selection siphunculus
Channel region, the channel hole are used to form the accumulation layer connecting with pillar.
Optionally, it etches the substrate to form pillar array and etch in the step of stack layer forms channel hole, adopt
With identical mask plate.
Optionally, the substrate is etched, to form the depressed area with pillar array, including：
Hard mask layer and patterned photoresist layer are formed over the substrate；
It is masking with the photoresist layer, patterns the first hard mask layer；
It is masking with patterned hard mask layer, etches the substrate, forms the depressed area with pillar array.
Optionally, the bottom sacrificial layer for surrounding pillar is formed on the gate dielectric layer of depressed area, including：
Carry out the filling of bottom sacrificial layer；
Carry out the planarization of bottom sacrificial layer；
The bottom sacrificial layer of etching removal segment thickness.
Optionally, insulating layer and the alternately stacked stack layer of sacrificial layer are formed on the bottom sacrificial layer and pillar,
Including：
Carry out the filling of the first layer insulating；
The planarization of the first layer insulating is carried out, the first layer insulating is higher than the upper surface of pillar；
It submits in the first layer insulating for stacking sacrificial layer and insulating layer, to form stack layer.
Optionally, further include：
Accumulation layer is formed in the channel hole, accumulation layer includes electric charge capture layer, charge-trapping on the side wall of channel hole
The insulation fill stratum of layer and the channel layer on pillar and channel interlayer；
By in stack layer sacrificial layer and bottom sacrificial layer be replaced into metal layer.
Optionally, the electric charge capture layer includes the silica, silicon nitride and silica stacked gradually, and the channel layer is
Polysilicon.
A kind of 3D nand memory part, including：
Substrate；
Depressed area in the substrate is formed with pillar array on depressed area, is formed on pillar side wall and depressed area surface
There is gate dielectric layer, the pillar array is formed by substrate where etched recesses area；
The bottom metal layer of pillar is surrounded in the depressed area, the bottom metal layer is lower than the pillar；
Insulating layer and the alternately stacked stack layer of metal layer on the bottom metal layer；
Channel hole in the stack layer；
The accumulation layer connecting in the channel hole with pillar, the pillar are the channel region of source line selection siphunculus.
Optionally, the accumulation layer includes the channel on the side wall of channel hole on electric charge capture layer, electric charge capture layer and pillar
The insulation fill stratum of layer and channel interlayer.
Optionally, upper surface of the upper surface of the pillar lower than the first layer insulating in stack layer.
3D nand memory part provided in an embodiment of the present invention and its manufacturing method form pillar battle array by etched substrate
Column form the bottom sacrificial layer for surrounding lower part around pillar, are further formed insulating layer and sacrifice on bottom sacrificial layer
The alternately stacked stack layer of layer, the channel hole formed in stack layer are located on pillar, are used to form in channel hole and pillar
The accumulation layer of connection, channel region of the pillar as the source line selection siphunculus of accumulation layer bottom in channel hole, in bottom sacrificial layer
It is replaced into after metal layer, metal layer, as channel region, ultimately forms source line selection siphunculus device as grid, pillar.The party
In method, the channel region of source line selection siphunculus is formed by etched substrate, reduces the heat demand in manufacturing process, is reduced to peripheral electricity
Device formation in road impacts, meanwhile, the channel region of source line selection siphunculus keeps the lattice structure of substrate, is the ditch of high quality
The performance of source line selection siphunculus device is improved in road area.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the schematic diagram of the section structure for planting 3D nand memory part in the prior art；
Fig. 2 shows the flow charts of the manufacturing method of 3D nand memory part according to an embodiment of the present invention；
Fig. 3-17 shows manufacturing method according to an embodiment of the present invention and forms cuing open during 3D nand memory part
Face structural schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, in 3D nand memory part manufacturing process, channel hole is formed in stack layer
Later, epitaxial layer is grown in channel hole bottom by selective epitaxial growth, which is used to form source line selection siphunculus, and
The technique is larger to heat demand, and temperature is typically larger than 800 DEG C, can be formed and be impacted to the device in peripheral circuit, meanwhile, it carves
After etched groove road hole, the flatness on the surface of substrate is poor, influences the quality of epitaxial growth, and then influences whether source line selection siphunculus
The performance of device.
For this purpose, forming source line by etched substrate the present invention provides a kind of 3D nand memory part and its manufacturing method
The channel region of gate tube reduces the heat demand in manufacturing process, reduces and impacts to the device formation in peripheral circuit, together
When, the channel region of source line selection siphunculus keeps the lattice structure of substrate, is the channel region of high quality, improves source line selection siphunculus device
Performance.
Technical solution and technical effect for a better understanding of the present invention, below with reference to flow chart and attached drawing to specific
Embodiment be described in detail.
Refering to what is shown in Fig. 2, substrate 100 is provided, with reference to shown in Fig. 3 in step S01.
In embodiments of the present invention, substrate 100 is semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe lining
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the semiconductor substrate can also be include other elements semiconductor or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be outside other
Prolong structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, the substrate 100 is body silicon monocrystalline substrate.
Core memory area and peripheral circuit can be integrated simultaneously over the substrate, core memory can also be only for forming
Area, core memory area are the forming region of 3D NAND device, and peripheral circuit is circuit relevant to NAND device operation, usually
It is made of cmos device.
In step S02, the substrate 100 is etched, to form the depressed area 110 with 112 array of pillar, with reference to Fig. 6 institute
Show.
The substrate etched in the step is the region for being used to form memory device, can be already formed with trap in the region and mix
Miscellaneous area, since pillar is what etched substrate was formed, pillar and substrate are the structure of same material and lattice, and depressed area 110 is to carve
The part for losing substrate removal, in depressed area, the part not being etched is pillar, and pillar regular array forms pillar array, convex
Column array is corresponded with channel hole to be formed later, it is preferable that pillar can be cylindrical shape.
In the present embodiment, specifically, forming the depressed area 110 with 112 array of pillar by following steps.
Firstly, sequentially forming the first hard mask layer 102 and the first photoresist layer 104 on substrate 100.
First hard mask layer 102 can be single layer or laminated construction, material for example can for silica, silicon nitride,
Silicon oxynitride, amorphous carbon etc. or their combination, first photoresist layer can be positive photoresist or negative photoresist.In the embodiment
In, amorphous carbon layer, silicon oxynitride layer of first hard mask layer 102 for silica and thereon, first photoresist layer 104
Be negative photoresist, the first hard mask layer can be initially formed on substrate 100 by the way of chemical vapor deposition or thermal oxide, and
The negative photoresist of spin coating on it afterwards, to form the first photoresist layer 104, with reference to shown in Fig. 3.
Then, patterned first photoresist layer 104 is formed, with reference to shown in Fig. 5.
Technique first is exposed to the first photoresist layer 104, refering to what is shown in Fig. 4, under the blocking of mask plate, it will be on mask plate
Pattern be transferred in the first photoresist layer 104, due to using negative photoresist, wherein will not be by the first photoresist layer 1042 of illumination
It is removed, will not be removed by the first photoresist layer 1041 of illumination in development, to form patterned first when development
Photoresist layer 1041, as shown in Figure 5.
Then, it is masking with the first photoresist layer 1401 after patterning, the first hard mask layer 102 is patterned, with reference to Fig. 6 institute
Show.
Dry etching can be used, such as RIE (reactive ion etching) technique can be used, etches the first hard mask layer
102, the pattern of photoresist layer 1401 is transferred in the first hard mask layer 102, and the cleaning of photoresist layer 1041 is got rid of.
Then, it is masking with patterned first hard mask layer 102, etches the substrate 100, there is pillar to be formed
The depressed area 110 of 112 arrays, with reference to shown in Fig. 6 and Fig. 7 (top view of Fig. 6).
Dry etching can be used, such as RIE (reactive ion etching) technique can be used, in the first hard mask layer 102
Blocking under, etched substrate 100 forms the depressed area 110 with pillar array, and the part shape of removal is etched on the substrate area
At depressed area, the part not being removed forms pillar 112, and pillar 112 is arranged in array to form pillar array, with reference to shown in Fig. 7.
The pillar 112 is to be formed by etched substrate, remains the material of substrate, and in the present embodiment, pillar is monocrystalline silicon, without passing through
Growth technique is formed, and is provided higher-quality channel region for source line selection siphunculus, is helped to improve the performance of source line selection siphunculus.
After forming pillar 112, the first hard mask layer 102 on pillar 112 can be removed, and can also be retained
Come, in the present embodiment, which is retained.
The pillar being here formed as is the channel region of source line selection siphunculus, and channel hole, above-mentioned etching step will be formed on pillar
In rapid, the mask plate when mask plate used when shifting pattern to photoresist layer can be to be used to form channel hole, in this way, being not necessarily to
Increase new mask plate, reduces process costs.
In step S03, gate dielectric layer 114 is formed on 112 side wall of pillar and depressed area surface, with reference to shown in Fig. 8.
Pillar 112 is the channel region of source line selection siphunculus, is initially formed grid on the channel region of source line selection siphunculus in this step
Dielectric layer, in order to form channel gate tube, gate dielectric layer can be silica or high K medium material (relative to titanium dioxide
Silicon has higher dielectric constant), in the present embodiment, which is silica, can by thermal oxidation technology come
The gate dielectric layer for forming the silica after thermal oxide, can all form grid in the whole surface of pillar 112 and depressed area
Dielectric layer 114, the gate dielectric layer on 112 upper surface of pillar will be got rid of when being subsequently formed accumulation layer.
In step S04, the bottom sacrificial layer 116 for surrounding pillar 112, institute are formed on the gate dielectric layer 114 of depressed area 110
Bottom sacrificial layer 116 is stated lower than the pillar 112, with reference to shown in Figure 11.
In this step, sacrificial layer 116 is formd in pillar lower part, sacrificial layer 116 is that will be gone in the next steps
The film layer removed, after sacrificial layer 116 is removed, it will be re-filled metal layer, the metal layer refilled surrounds pillar
112 lower part finally, forms source line selection siphunculus as the grid of source line selection siphunculus.
Etch selectivity when can be according to subsequent removal sacrificial layer determines the material of sacrificial layer, in the present embodiment,
The material of sacrificial layer is silicon nitride (Si3N4).Specifically, bottom sacrificial layer 116 can be formed by following steps.
Firstly, the filling of bottom sacrificial layer 116 is carried out, with reference to shown in Fig. 9.
Chemical vapor deposition or other suitable deposition methods can be used, the filling of bottom sacrificial layer 116 is carried out.
Then, the planarization for carrying out bottom sacrificial layer 116, with reference to shown in Figure 10.
The method that chemical mechanical grinding (CMP) can be used, is planarized, in the present embodiment, after planarization, recessed
Bottom sacrificial layer is formd in slot.
Then, the bottom sacrificial layer 116 of etching removal segment thickness, with reference to shown in Figure 11.
Wet process or dry etching can be used, removes certain thickness bottom sacrificial layer 116, after etching, is formed and is surrounded
The bottom sacrificial layer 116 of pillar lower part, that is to say, that bottom sacrificial layer 116 will be lower than the pillar 112.
In step S05, insulating layer is formed on the bottom sacrificial layer 116 and pillar 112 and sacrificial layer is alternately laminated
Stack layer 130, with reference to shown in Figure 14.
The number of plies of stack layer 130 is determined according to the number of the storage unit of formation needed for vertical direction, stack layer 130
The number of plies for example can be 32 layers, 64 layers, 128 layers etc., and the number of plies of stack layer refers to the number of plies of wherein sacrificial layer herein, and sacrificial layer exists
It will be replaced with metal layer in subsequent step, for insulating layer for separating metal interlevel, metal layer is the control of memory device
Grid, the number of plies determine the number of storage unit in vertical direction, and therefore, the number of plies of stack layer is more, can more improve integrated level.
It is understood that only schematical example goes out therein several layers of, in practical devices structure in the diagram of the embodiment of the present invention
In, stack layer has more numbers of plies.
It can determine the material of insulating layer and sacrificial layer according to the Etch selectivity in subsequent technique, in the present embodiment,
Insulating layer is silica (SiO2) layer, sacrificial layer is silicon nitride layer.
When forming stack layer 130, it can be initially formed the first layer insulating 1201, then successively alternating deposit sacrificial layer
122 and insulating layer 120, to form stack layer 130.
Specifically, in the present embodiment, firstly, the filling of the first layer insulating 1201 is carried out, with reference to shown in Figure 12.
The method that chemical vapor deposition can be used, cvd silicon oxide, to carry out the filling of the first layer insulating 1201, ginseng
It examines shown in Figure 12.
Then, the planarization of the first layer insulating 1201 is carried out, the first layer insulating 1201 is higher than the upper table of pillar 112
Face, with reference to shown in Figure 13.
In this step, the first insulating layer of a part 1201 on pillar 112 is removed, only to realize the first insulating layer
1201 planarization, after planarization, the first layer insulating 1201 still covers the upper surface of pillar 112.In this way, can be in order to rear
It is continuous to form the stack layer for being used to form storage unit.
Then, on the first layer insulating 1201 of planarization, alternately laminated sacrificial layer 122 and insulating layer 120, thus
Stack layer 130 is formed, with reference to shown in Figure 14.
The method that chemical vapor deposition can be used, alternating deposit sacrificial layer 122 and insulating layer 120, to form stacking
Layer 130.
In step S06, the stack layer 130 is etched, forms channel hole 140 on the region for corresponding to pillar 112, it is described
Pillar 112 is the channel region of source line selection siphunculus, and the channel hole 140 is used to form the accumulation layer connecting with pillar, with reference to Figure 15
It is shown.
Specifically, the second hard mask layer and patterned second light can be sequentially formed on stack layer in the present embodiment
Resistance layer (not shown go out), the mask plate used when forming patterned second photoresist layer can with mask plate when forming pillar for
Same mask plate；Lithographic technique is then used, the pattern of the second photoresist layer is transferred in the second mask layer, and removes the second light
Resistance layer；Then, using lithographic technique, such as the method for RIE (reactive ion etching), stack layer is etched, until exposing pillar
112 surface, thus, channel hole 140 is formed on pillar, as shown in figure 15, channel hole 140 is located on pillar 112, is used for shape
At accumulation layer, accumulation layer and pillar 112 can pass through contact connectio.
So far, channel hole is formd on pillar 112, channel hole is used to form accumulation layer, later, can complete others
Processing technology.
In step S07, accumulation layer 150 is formed in the channel hole, accumulation layer 150 includes the charge on the side wall of channel hole
The insulation fill stratum between channel layer 1502 and channel layer 1502 on trapping layer 1501, electric charge capture layer 1501 and pillar 112
1503, with reference to shown in Figure 16.
In the present embodiment, electric charge capture layer ONO, the i.e. lamination of oxide-nitride-oxide, channel layer are more
Crystal silicon layer can be sequentially depositing the electric charge capture layer 1501 of ONO in the particular embodiment, then form the channel of polysilicon
Layer 1502 when, when forming polysilicon layer, the ONO layer of 112 upper surface of pillar is got rid of so that deposit polysilicon layer with it is convex
112 upper surface of column connects, and then, fills insulation fill stratum 1503, and in the present embodiment, insulation fill stratum 1503 is oxidation
Silicon, thus, accumulation layer 150 is formed in channel hole.
In step S08, by stack layer 130 sacrificial layer 122 and bottom sacrificial layer 116 be replaced into metal layer 123, join
It examines shown in Figure 17.
In the step, by all sacrificial layers, including in stack layer 130 sacrificial layer 122 and bottom sacrificial layer 116 it is complete
Portion is removed, and is then refilled into metal material, in this way, form bottom metal layer 1231, and it is new by metal layer
With the alternately stacked stack layer 131 of insulating layer, as shown in figure 17.
Specifically, grid line gap (not shown go out) can be initially formed, grid line gap is entered by acid solution, is selected to insulating layer
Phosphoric acid (H can be used in the present embodiment with the acid solution of the high selectivity ratio of sacrificial layer3PO4), the sacrificial layer of silicon nitride is gone
It removes, after removal, is packed into metal layer, metal layer is usually tungsten (W).Then, N-type drain can be formed on channel hole top to connect
Touching 160, for connecting drain electrode selecting pipe.
So far, the 3D nand memory part of the embodiment of the present invention is completed.After the displacement for carrying out metal layer, metal
Layer is grid line, and each layer of metal layer and accumulation layer 150 in stack layer 131 constitute a storage unit, thus, in channel hole
A string of storage units are formed, the bottom of storage unit is source line selection siphunculus, and the channel of source line selection siphunculus is pillar 112, in pillar
Gate dielectric layer 114 is formed on 112 side wall, 112 lower part of pillar is surrounded by bottom metal layer 1231,112 upper surface of pillar with
Accumulation layer 150 thereon connects, thus, it is formed using pillar as the source line selection siphunculus of channel.
The manufacturing method of the embodiment of the present invention is described in detail above, in addition, the present invention also provides by upper
The 3D nand memory part for stating method formation, with reference to shown in Figure 17, including：
Substrate 100；
Depressed area in the substrate 100 is formed with 112 array of pillar, 112 side wall of pillar and depressed area table on depressed area
Gate dielectric layer 114 is formed on face, the pillar array passes through the formation of substrate 100 where etched recesses area；
The bottom metal layer 1231 of pillar 112 is surrounded in the depressed area, the bottom metal layer 1231 is lower than described convex
Column 112；
Insulating layer 123 and the alternately stacked stack layer 131 of metal layer 123 on the bottom metal layer 1231；
Channel hole in the stack layer 131；
The accumulation layer 150 connecting in the channel hole with pillar, the pillar 112 are the channel region of source line selection siphunculus.
In embodiments of the present invention, the accumulation layer 150 includes electric charge capture layer 1501, charge-trapping on the side wall of channel hole
Layer 1501 and the insulation fill stratum 1503 between channel layer 1502 and channel layer 1502 on pillar 112.
Bottom metal layer 1231 surrounds pillar 112, and bottom metal layer 1231 is lower than pillar 112, that is to say, that underlying metal
The upper surface of layer 1231 is lower than the upper surface of pillar 112, and bottom metal layer 1231 only surrounds the lower part of pillar, the bottom metal layers
It is stack layer on 1231, the upper surface of bottom metal layer is lower than the upper surface of the first layer insulating 1201 in stack layer.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (5)
1. a kind of manufacturing method of 3D nand memory part, which is characterized in that including：
Substrate is provided；
The substrate is etched, to form the depressed area with pillar array；
Gate dielectric layer is formed on pillar and depressed area surface；
The bottom sacrificial layer for surrounding pillar is formed on the gate dielectric layer of depressed area, the bottom sacrificial layer is lower than the pillar；
Insulating layer and the alternately stacked stack layer of sacrificial layer are formed on the bottom sacrificial layer and pillar；
The stack layer is etched, forms channel hole on the region for corresponding to pillar, the pillar is the channel of source line selection siphunculus
Area, the channel hole are used to form the accumulation layer connecting with pillar；
Form accumulation layer in the channel hole, accumulation layer include electric charge capture layer on the side wall of channel hole, electric charge capture layer and
The insulation fill stratum of channel layer and channel interlayer on pillar；
By in stack layer sacrificial layer and bottom sacrificial layer be replaced into metal layer；
Wherein, it etches the substrate to form pillar array and etch in the step of stack layer forms channel hole, use is identical
Mask plate.
2. the manufacturing method according to claim 1, which is characterized in that etch the substrate, there is pillar array to be formed
Depressed area, including：
Hard mask layer and patterned photoresist layer are formed over the substrate；
It is masking with the photoresist layer, patterns the first hard mask layer；
It is masking with patterned hard mask layer, etches the substrate, forms the depressed area with pillar array.
3. the manufacturing method according to claim 1, which is characterized in that formed on the gate dielectric layer of depressed area and surround pillar
Bottom sacrificial layer, including：
Carry out the filling of bottom sacrificial layer；
Carry out the planarization of bottom sacrificial layer；
The bottom sacrificial layer of etching removal segment thickness.
4. manufacturing method according to claim 3, which is characterized in that formed on the bottom sacrificial layer and pillar exhausted
Edge layer and the alternately stacked stack layer of sacrificial layer, including：
Carry out the filling of the first layer insulating；
The planarization of the first layer insulating is carried out, the first layer insulating is higher than the upper surface of pillar；
It submits in the first layer insulating for stacking sacrificial layer and insulating layer, to form stack layer.
5. the manufacturing method according to claim 1, which is characterized in that the electric charge capture layer includes the oxidation stacked gradually
Silicon, silicon nitride and silica, the channel layer are polysilicon.
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| CN201710773927.2A CN107564915B (en) | 2017-08-31 | 2017-08-31 | A kind of 3D nand memory part and its manufacturing method |
| CN202010709035.8A CN111653574B (en) | 2017-08-31 | 2018-05-16 | Three-dimensional memory device and method of fabricating the same |
| PCT/CN2018/087158 WO2019041892A1 (en) | 2017-08-31 | 2018-05-16 | Three-dimensional memory device and fabricating method thereof |
| CN201880005174.3A CN110088904B (en) | 2017-08-31 | 2018-05-16 | Three-dimensional memory device and method of fabricating the same |
| TW107122784A TWI682525B (en) | 2017-08-31 | 2018-07-02 | Three-dimensional memory device and fabricating method thereof |
| US16/046,679 US10797067B2 (en) | 2017-08-31 | 2018-07-26 | Three-dimensional memory device and fabricating method thereof |
| US17/012,460 US11437400B2 (en) | 2017-08-31 | 2020-09-04 | Three-dimensional memory device and fabricating method thereof |
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| TWI682525B (en) | 2020-01-11 |
| CN110088904A (en) | 2019-08-02 |
| CN111653574A (en) | 2020-09-11 |
| TW201913969A (en) | 2019-04-01 |
| WO2019041892A1 (en) | 2019-03-07 |
| CN110088904B (en) | 2020-08-25 |
| CN111653574B (en) | 2021-03-12 |
| CN107564915A (en) | 2018-01-09 |
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