CN116249350A - Semiconductor structure, manufacturing method thereof, memory device and memory system - Google Patents

Abstract

Embodiments of the present application provide a semiconductor structure and its manufacturing method, a memory device, and a memory system, wherein the manufacturing method of the semiconductor structure includes: providing a first stack structure; the first stack structure includes several insulating layers arranged alternately in stacks and a sacrificial layer, at least one side of the first stacked structure is formed with a first stepped structure, and the top surface of each step of the first stepped structure is a sacrificial layer; a thickened layer covering the first stepped structure is formed, and the thickened layer includes sequentially The first thickened layer and the second thickened layer are stacked; on each step, a first groove penetrating part of the second thickened layer is formed; based on the first groove, further forming The second groove of the second thickening layer; remove the sacrificial layer and the remaining thickening layer to form the gate and the gate thickening layer, and form a gate contact on each step; wherein, the second groove makes the phase The gate thickening layers on the top surfaces of the two adjacent steps are electrically isolated from each other.

Description

Semiconductor structure and manufacturing method thereof, memory device, memory system

technical field

The present application relates to the technical field of semiconductors, and in particular to a semiconductor structure, a manufacturing method thereof, a memory device, and a memory system.

Background technique

In the memory structure, stacked layers are usually formed by alternately stacking several gate layers and insulating layers. The central area of the stacked layer is the core storage area, and the edge area is the step (SS, Staircase) area. The core storage area is used to form In the memory cell string, the gate layer in the stacked layer is used as the gate line (GL, Gate Line) of each layer of memory cells, and the gate line realizes the extraction of electrical signals through the contact (CT, Contact) on the ladder structure. With the increase in the number of stacked layers in the memory structure, there are still many problems in the preparation process of the memory structure in the related art.

Contents of the invention

In order to solve related technical problems, embodiments of the present application provide a semiconductor structure, a manufacturing method thereof, a memory device, and a memory system.

A method for fabricating a semiconductor structure provided by the present application, the method comprising:

A first stacked structure is provided; the first stacked structure includes several insulating layers and sacrificial layers stacked alternately, at least one side of the first stacked structure is formed with a first stepped structure, and each layer of the first stepped structure The top surface of the ladder is a sacrificial layer;

forming a thickened layer covering the first stepped structure, the thickened layer comprising a first thickened layer and a second thickened layer stacked in sequence;

A first groove penetrating part of the second thickened layer is formed on each step;

Based on the first groove, further forming a second groove penetrating through the first thickened layer and the second thickened layer;

removing the sacrificial layer and the remaining thickening layer to form a gate and a thickening layer for the gate, and forming a gate contact on each of the steps; wherein, the second groove makes two adjacent layers The gate thickening layers on the top surfaces of the steps are electrically isolated from each other.

In the above solution, the first groove penetrating part of the second thickened layer is formed on each step, including:

Removing part of the second thickened layer at the position where the top surface of each step is close to the side wall of the adjacent step to form the first groove;

The further forming a second groove penetrating through the first thickened layer and the second thickened layer includes:

The second thickened layer and the first thickened layer corresponding to the bottom of the first groove and the adjacent step sidewalls are removed to form the second groove.

In the above solution, based on the first groove, further forming a second groove penetrating through the first thickened layer and the second thickened layer includes:

Based on the first groove, oxidize the second thickened layer on the bottom and sidewall of the first groove to form an oxide layer;

removing the oxide layer, and the first thickened layer corresponding to the bottom of the first groove and the sidewall of each step, forming a second thickened layer that runs through the first thickened layer and the second thickened layer. groove.

In the above solution, the first groove penetrating part of the second thickened layer is formed on each step, including:

Removing part of the second thickened layer at the position where the top surface of each step is close to the sidewall of the adjacent step by a dry etching process to form the first groove;

The further forming a second groove penetrating through the first thickened layer and the second thickened layer includes:

The second thickened layer and the first thickened layer corresponding to the bottom of the first groove and adjacent to the sidewall of the adjacent step are removed by wet etching process to form the second groove.

In the above solution, the first stacking structure provided includes:

providing a second stack structure comprising several alternately stacked insulating layers and sacrificial layers;

Etching the second stacked structure to form a second stepped structure on at least one side of the second stacked structure; wherein, the top surface of each step of the second stepped structure is an insulating layer;

The insulating layer on the top surface of each step of the second step structure is removed to form a first stack structure having the first step structure.

In the above solution, the formation of a gate contact on each step includes:

After forming the second groove, a dielectric layer is formed in the second groove and on the top surface of the first stepped structure;

A third groove penetrating through the dielectric layer is formed on each step;

The third groove is filled with a second conductive material to form a plurality of gate contacts; each gate contact is electrically connected to a gate on a corresponding layer step.

In the above solution, the removal of the sacrificial layer and the remaining thickening layer to form the gate and the thickening layer of the gate include:

After forming the dielectric layer, removing the sacrificial layer and the remaining thickening layer in the first stacked structure to form a first gap;

filling the first gap with a first conductive material to form the gate and the gate thickening layer.

In the above scheme, the method also includes:

Before forming the first groove, forming a mask layer covering the second thickened layer and a solidified layer covering the mask layer;

removing the solidified layer on the sidewall of each step to form a second gap at a position where the top surface of each step in the first step structure is close to the sidewall of the step;

removing a portion of the second thickened layer to form the first groove based on the second gap;

Before forming the second groove, the remaining mask layer and the remaining cured layer are removed.

In the above solution, the material of the first thickening layer includes first silicon nitride; the material of the second thickening layer includes second silicon nitride; the material of the sacrificial layer includes third silicon nitride; The etching selectivity ratios of the first silicon nitride, the second silicon nitride and the third silicon nitride are all different.

A semiconductor structure provided by the present application, the semiconductor structure is obtained by using the manufacturing method of the semiconductor structure described in the above-mentioned embodiments of the present application, including:

The first stacked structure; the first stacked structure includes several insulating layers and gates stacked alternately, at least one side of the stacked structure is formed with a first ladder structure; the top of each layer of the first ladder structure The surface is the grid;

A gate thickening layer; located on the top surface of each step of the first stepped structure; wherein, the gate thickening layers on the top surfaces of the steps of two adjacent layers are electrically isolated from each other;

A gate contact; located on each step; the gate contact is electrically connected to the gate on the corresponding step.

A memory device provided by the present application includes: one or more semiconductor structures as described in the foregoing embodiments of the present application.

A memory system provided by the present application includes: the memory device as described in the foregoing embodiments of the present application; and

The memory controller is connected with the memory device and used for controlling the memory device.

The present application provides a method for fabricating a semiconductor structure, the method comprising: providing a first stack structure; the first stack structure includes several insulating layers and sacrificial layers alternately stacked, at least one of the first stack structure A first stepped structure is formed on the side, and the top surface of each step of the first stepped structure is a sacrificial layer; a thickened layer covering the first stepped structure is formed, and the thickened layer includes the first A thickened layer and a second thickened layer; a first groove penetrating part of the second thickened layer is formed on each step; based on the first groove, further forming a groove penetrating through the first thickened layer The thick layer and the second groove of the second thickened layer; removing the sacrificial layer and the remaining thickened layer to form the gate and the thickened layer of the gate, and forming a gate contact on each step ; Wherein, the second groove electrically isolates the thickened gate layers on the top surfaces of two adjacent steps from each other. In the embodiment of the present application, in the process of forming the second groove for electrically isolating the gate thickening layer on the top surface of two adjacent steps, by first forming only the through part for forming the gate thickening layer The second thickened layer is used to form the first groove, and then based on the first groove, the second thickened layer below the first groove and the layer below the second thickened layer that are also used to form the gate thickened layer are removed. The first thickened layer, and then the second groove is formed; since the first groove is shallow, the amount of the second thickened layer removed by etching is small, so that the process window for forming the first groove is increased. Further, The bottom of the first groove is far away from the gate layer. Based on the first groove, when the second groove with gate electrical isolation effect is further formed, the process control difficulty of the second groove is reduced and the process window is increased. In this way, the accuracy and reliability of the electrical connection between the gate contact and the gate can be better guaranteed.

Description of drawings

FIG. 1a is a schematic structural diagram of a core storage area and a step area in a semiconductor structure provided by an embodiment of the present application;

FIG. 1b is a schematic structural diagram of a step region in a semiconductor structure provided by an embodiment of the present application;

Fig. 1c is a schematic diagram of a semiconductor structure with etching residues in the through hole provided by the embodiment of the present application;

FIG. 2 is a schematic flow diagram of another memory manufacturing method provided in the embodiment of the present application;

3a to 3o are schematic cross-sectional views of another memory forming process 1 provided by the embodiment of the present application.

In the above drawings (which are not necessarily drawn to scale), like reference numerals may describe like parts in the different views. Similar reference numbers with different letter suffixes may indicate different instances of similar components. The drawings generally illustrate the various embodiments discussed herein, by way of example and not limitation.

Explanation of reference signs:

10-central area; 20-edge area; 30-high area; 40-low area; 101-insulating layer; 102-gate layer; 103-contact; 104-thickened layer; 1041-first thickened layer; 1042 - second thickened layer; 105 - second via; 300 - first stacked structure; 400 - second stacked structure; 301 - sacrificial layer; 302 - insulating layer; 303 - thickened layer; 3031 - first thickened Layer; 3032-second thickening layer; 304-mask layer; 305-cured layer; 306-second gap; 307-first groove; 308-oxidation layer; 309-second groove; 310-dielectric layer 311-first gap; 312-gate; 313-gate thickening layer; 314-third groove; 315-adhesive layer; 316-gate contact.

Detailed ways

Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided for a more thorough understanding of the present application and for fully conveying the scope disclosed in the present application to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiment are not described here, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It should be understood that spatially relative terms such as "below", "under", "under", "under", "on", "above", etc. are used herein Descriptive convenience may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to understand the characteristics and technical contents of the embodiments of the present application in more detail, the implementation of the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present application.

It should be noted that, for the convenience of description in the embodiments of the present application, the first direction and the second direction are represented as two orthogonal directions in the substrate plane or the stack structure plane, that is, the direction extending laterally in the substrate plane or the stack structure plane. Two lateral surfaces; the third direction is the direction perpendicular to the substrate plane or the plane of the stacked structure, that is, the direction in which the stacked structure is stacked. Exemplarily, the first direction is represented as the X direction in the drawings; the second direction is represented as the Y direction in the drawings; and the third direction is represented as the Z direction in the drawings.

The semiconductor structure involved in the embodiments of the present application is to be used in subsequent processes to form at least a part of the final device structure. Here, the final device may include a memory, and the memory includes but is not limited to a NAND memory, and the following only uses the NAND memory as an example for illustration. However, it should be noted that the description of the NAND memory in the following embodiments is only used to illustrate the present application, and is not intended to limit the scope of the present application.

Referring to FIG. 1a, in the related art, when forming stacked layers in NAND-type memory, a method of stacking several insulating layers 101 and gate layers 102 is usually adopted. The stacked layer includes a central region 10 and an edge region 20; wherein, the central region 10 is a core storage area, and the core storage area includes a plurality of memory cell strings; the edge area 20 is a stepped area, and the stepped area includes a multi-layer ladder structure, and a contact 103 is formed on each step in the multi-layer ladder structure, and each storage The gate layer 102 in the cell string can lead out the electrical signal through the corresponding contact 103 .

In practical applications, when forming a contact on each step, the usual method is to form a contact hole first, and then deposit a conductive material in the contact hole; however, due to the small process window of the etching process used to form the contact hole, It is necessary to form a thickened layer 104 on each gate layer 102 corresponding to each step to avoid damage to the gate layer by the etching process; the higher the number of stacked layers, the greater the thickness of the required thickened layer .

It should be noted that, referring to FIG. 1b and FIG. 1c, when forming the thickened layer 104, it is necessary to deposit a thickened material layer on each gate layer 102 corresponding to the step region 20, and the thickened material layer includes the first thickened The material layer and the second thickened material layer on the first thickened material layer, and then perform the first etching on the thickened material layer near the adjacent step on each step by dry etching to form a through The first through hole of the second thickened material layer and part of the first thickened material layer, and then perform second etching on the first through hole by wet etching to form the second through hole 105 and the second through hole located at the second The thickened layer 104 on both sides of the through hole 105, here, the thickened layer 104 includes a first thickened layer 1041 and a second thickened layer 1042 on the first thickened layer 1041, and the second through hole 105 will be relatively The thickened layer 104 on adjacent two steps is electrically isolated. However, in the process of performing the first etching, when part of the thickened material layer needs to be removed, since the etching process, such as plasma etching, has a certain directionality, the etching degree of the thickened material layer in different regions Different, for example, the etching rate of the thickened material layer in the high area is fast, and the etching rate of the thickened material layer in the low area is slow, so that the problem of uneven etching occurs, thereby reducing the process window of the first etching.

Exemplarily, for example, there is over-etching on the thickened material layer on the top surface of the step of the high region 30, which will cause F-attack (F-attack) problems in subsequent processes, thereby destroying the integrity of the gate layer 102 , as shown by the dotted line box in FIG. The problem of electrical connection (such as current leakage, Leakage) between the electrode layers 102 through the remaining thickened material layer is shown in FIG. 1c.

It should be noted that there is a certain height difference between the steps of the high region 30 and the steps of the low region 40 in the Z-axis direction, so that the thickened material layer deposited on the top surface of the steps of the high region 30 is different from that deposited on the bottom surface of the low region 40. The thickness of the thickened material layer on the step top surface is different, for example, the thickness of the thickened material layer on the step top surface of the high region 30 is greater than the thickness of the thickened material layer on the step top surface of the low region 40, that is, the upper thickness and the lower thickness. In this way, when performing the first etching process, the aforementioned incomplete etching and over-etching problems can be alleviated to a certain extent; however, for the characteristics of the plasma etching process itself, the high and low regions The difference in thickness of the thickened material layer on the top surface of the corresponding step is far from enough to solve the aforementioned problems of incomplete etching and over-etching.

In view of this, an embodiment of the present application provides a method for fabricating a semiconductor structure, and FIG. 2 is a schematic flowchart of an implementation of the method for fabricating a semiconductor structure provided in the embodiment of the present application. As shown in Figure 2, the method includes the following steps:

Step S201: providing a first stack structure; the first stack structure includes several insulating layers and sacrificial layers stacked alternately, at least one side of the first stack structure is formed with a first ladder structure, and the first ladder structure The top surface of each ladder is the sacrificial layer;

Step S202: forming a thickened layer covering the first stepped structure, the thickened layer includes a first thickened layer and a second thickened layer stacked in sequence;

Step S203: forming a first groove penetrating part of the second thickening layer on each step;

Step S204: Based on the first groove, further forming a second groove penetrating through the first thickened layer and the second thickened layer;

Step S205: removing the sacrificial layer and the remaining thickening layer to form a gate and a thickening layer for the gate, and forming a gate contact on each step; wherein, the second groove makes the corresponding The gate thickening layers on the top surfaces of the two adjacent steps are electrically isolated from each other.

It should be understood that the steps shown in FIG. 2 are not exclusive, and other steps may be performed before, after or between any steps in the shown operations; the order of the steps shown in FIG. 2 may be adjusted according to actual needs. 3a to 3o are schematic cross-sectional views of a manufacturing process of a semiconductor structure provided by an embodiment of the present application. The manufacturing method of the semiconductor structure provided by the embodiment of the present application will be described in detail below with reference to FIG. 2 , and FIG. 3 a to FIG. 3 o.

Step S201 is executed, referring to FIG. 3 a , to provide a first stack structure 300 .

Referring to FIG. 3a, the first stack structure 300 includes several insulating layers 302 and sacrificial layers 301 alternately stacked, and at least one side of the first stack structure 300 is formed with a first ladder structure; The top surface of each step is a sacrificial layer 301 . It should be noted that, FIG. 3a to FIG. 3h of the present application only show the step region (the first step structure or the second step structure) in the stack structure (the first stack structure or the second stack structure).

In some specific embodiments, the provision of the first stack structure 300 includes: providing a substrate (not shown in Fig. 3a-Fig. 3o); forming several insulating layers 302 and sacrificial layer 301 . The substrate may have a main surface extending in a first direction and a second direction as a horizontal direction.

In some embodiments, the structure of the substrate can be selected and set according to the actual requirements of the device; for example, the substrate can be a composite laminated structure, including sequentially following along the third direction (Z direction in the drawing). A pad oxide layer, a bottom polysilicon layer, a buffer oxide layer and a top polysilicon layer are stacked on the substrate. The material of the substrate may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI, Silicon-on-insulator) substrate or a germanium-on-insulator ( GOI, Germanium-on-Insulator) substrate, etc.; the material of the pad oxide layer may include silicon oxide, the material of the bottom polysilicon layer may include polysilicon, the material of the buffer oxide layer may include silicon oxide, The material of the top polysilicon layer may include polysilicon. In practical application, the pad oxide layer, bottom polysilicon layer, buffer oxide layer and top polysilicon layer on the substrate can be formed by PVD process, CVD process or ALD process. The substrate formed in this way is suitable for performing epitaxial growth of silicon on the back of the substrate to form a silicon epitaxial layer (SEG, Selective Epitaxial Growth) in the subsequent process, and realizing the extraction of the common source (Common Source) on the back of the substrate.

Here, the material of the sacrificial layer 301 includes but not limited to nitride, silicon carbide (SiC), silicon and silicon germanium. The material of the insulating layer 302 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, and other high dielectric constant (High K) dielectrics; in some specific embodiments, the sacrificial layer 301 can be made of silicon nitride ( SiN); the insulating layer 302 may be formed of silicon oxide (SiO), so that the formed first stack structure is a nitride-oxide (NO) stack. In some embodiments, the sacrificial layer 301 and the insulating layer 302 may have the same thickness as each other, or may have different thicknesses from each other.

It should be noted that the first stacked structure 300 may have a first stepped structure on one side, or may have a first stepped structure on both opposite sides. The actual situation may be selected according to actual needs. Here, only the first One side of the stack structure has a first ladder structure as an example for illustration.

Here, the top surface of each step of the first stepped structure is a sacrificial layer 301. In actual operation, the first stacked structure 300 in which the top surface is the sacrificial layer can be directly provided, as shown in FIG. 3a; the top can also be formed first. The second stack structure 400 with the insulating layer 302 on the surface, referring to FIG. 3 b , and then the first stack structure 300 with the sacrificial layer 301 on the top surface of each step is formed through subsequent manufacturing processes. specifically,

In some embodiments, the providing a first stack structure includes:

providing a second stack structure comprising several alternately stacked insulating layers and sacrificial layers;

Etching the second stacked structure to form a second stepped structure on at least one side of the second stacked structure; wherein, the top surface of each step of the second stepped structure is an insulating layer;

The insulating layer on the top surface of each step of the second step structure is removed to form a first stack structure having the first step structure.

Referring to FIG. 3b, the second stack structure 400 includes several alternately stacked insulating layers 302 and sacrificial layers 301, and the top surface of the second stepped structure on at least one side of the second stack structure 400 is the insulating layer 302; through the removal process, the The insulating layer 302 on the top surface of each step of the second step structure is removed to form a first stack structure 300 in which the top surface of each step is a sacrificial layer 301 . The removal process includes but not limited to dry etching process. Exemplarily, the removal process includes a plasma dry etching process.

Here, both the insulating layer 302 and the sacrificial layer 301 can be formed by physical vapor deposition (PVD, Physical Vapor Deposition) process, chemical vapor deposition (CVD, Chemical Vapor Deposition) process, atomic layer deposition (ALD, Atomic Layer Deposition) and other processes.

In the subsequent process, the sacrificial layer 301 can be removed, and the removed position is filled with a gate metal material (refer to FIG. W), which will be described in detail later, and will not be repeated here.

Step S202 is executed, referring to FIG. 3 c , to form a thickened layer 303 .

Referring to Figure 3c, the thickened layer 303 includes a first thickened layer 3031 and a second thickened layer 3032 stacked in sequence; the first thickened layer 3031 covers the top surface and sidewall of each step in the first stepped structure ; The second thickened layer 3032 covers the first thickened layer 3031 . In practical applications, according to the requirements of the process, the first thickened layer 3031 and the second thickened layer 3032 can also selectively cover other areas except the first stepped structure.

In some embodiments, the material of the first thickening layer includes first silicon nitride; the material of the second thickening layer includes second silicon nitride; the material of the sacrificial layer includes third silicon nitride ; The etching selectivity ratios of the first silicon nitride, the second silicon nitride and the third silicon nitride are all different.

When using plasma (Plasma) to dry etch the first silicon nitride, the second silicon nitride, and the third silicon nitride, the first etching selectivity of the plasma to the first silicon nitride is smaller than that of the first silicon nitride. The second etching selection ratio of the second silicon nitride; for example, the second etching selection ratio is about two to three times of the first etching selection ratio. However, the etching selectivity of the plasma to the first silicon nitride and the second silicon nitride is greater than its third etching selectivity to the third silicon nitride.

When hydrofluoric acid (HF) or the like is used as an etchant for wet etching, the fourth etching selectivity of the etchant to the first silicon nitride is smaller than the fifth etching selectivity of the second silicon nitride; Exemplarily, the fifth etching selection ratio is more than ten times of the fourth etching selection ratio. However, the etching selectivity ratio of the etchant to the first silicon nitride and the second silicon nitride is greater than the sixth etching selectivity ratio of the etchant to the third silicon nitride.

Exemplarily, the first silicon nitride is a first type of topological structure silicon oxide (Topology Structure Silicon Nitride, TS SiN); the second silicon nitride is a second type of topological structure silicon oxide; the third silicon nitride is a conventional silicon nitride silicon.

Here, the methods for forming the first thickened layer 3031 and the second thickened layer 3032 include but not limited to PVD process, CVD process or ALD process. The thicknesses of the first thickened layer 3031 , the second thickened layer 3032 and the sacrificial layer 301 can be the same or different. If the total thickness of the first thickened layer 3031 and the second thickened layer 3032 (that is, the thickness of the thickened layer 303) is set to be the same as the thickness of the sacrificial layer 301, it is beneficial to simultaneously form the gate in the same step in the subsequent process. electrode and gate thickening layer.

Step S203 is executed to form a first groove.

In some embodiments, the method also includes:

Before forming the first groove, forming a mask layer covering the second thickened layer and a solidified layer covering the mask layer;

removing the solidified layer on the sidewall of each step to form a second gap at a position where the top surface of each step in the first step structure is close to the sidewall of the step;

Based on the second gap, part of the second thickened layer is removed to form the first groove.

Referring to FIG. 3 d, a mask layer 304 is formed on the second thickened layer 3032; the mask layer 304 can be used to form various preset patterns for etching, and the material of the mask layer 304 includes But not limited to carbon (C), carbon-containing polymers. The method of forming the mask layer 304 includes but not limited to PVD process, CVD process or ALD process.

A solidified layer 305 is formed on the mask layer 304; the solidified layer 305 is used in subsequent processes to balance the etching time of the mask layer on the top surface and sidewall of each step by dry etching. Materials of the solidified layer 305 include, but are not limited to, carbon, carbon-containing polymers. The method of forming the cured layer 305 includes but not limited to PVD process, CVD process or ALD process.

Next, referring to FIG. 3e, the solidified layer 305 is trimmed, that is, the solidified layer 305 located on the sidewall of each step is removed to form the second gap 306; since the dry etching used in the subsequent process is directional, and the carbon layer The material of the (cured layer or mask layer) is relatively loose and easy to be etched. In this way, when the mask layer 304 and the cured layer 305 are dry-etched using plasma, the mask layer positioned at the sidewall of each step can be removed completely.

Next, referring to FIG. 3f, based on the second gap 306, a part of the second thickening layer 3032 on the top surface of each step in the first step structure is removed through a dry etching process to form a first groove. 307.

In some embodiments, the first groove penetrating part of the second thickened layer is formed on each step, including:

The first groove is formed by removing part of the second thickened layer at the position where the top surface of each step is close to the side wall of the adjacent step.

In other words, the first groove is located at the position where the top surface of each step is close to the side wall of the adjacent step; in this way, it is beneficial to completely remove the first thickening on the side wall of each step when the second groove is subsequently formed. Layer 3031.

It should be noted that, since dry etching has relatively small etching options for the second thickened layer 3032, when removing part of the second thickened layer 3032, the etching time is longer and the controllability of the process is increased. That is, the process window increases. On the other hand, since the second thickened layer 3032 is not completely penetrated by the first groove, the first thickened layer 3031 in different regions (high regions or regions) will not be over-etched, that is, the sacrificial layer will not be damaged. Layer 301 Integrity.

Next, referring to FIG. 3g, before forming the second groove, the remaining mask layer 304 and the remaining cured layer 305 are removed.

It should be noted that, referring to FIG. 3 f , during the process of forming the first groove 307 , the dry etching process has already removed the cured layer 305 located on the top surface of each step. Therefore, after the first groove 307 is formed, it is only necessary to remove the mask layer 304 located on the top surface of each step. The removal process includes but not limited to etching process and heat treatment.

Step S204 is executed to form a second groove.

In some embodiments, referring to FIG. 3g, FIG. 3h, and FIG. 3i, the further forming of the second groove penetrating through the first thickened layer and the second thickened layer includes:

The second thickened layer 3032 and the first thickened layer 3031 corresponding to the bottom of the first groove 307 and adjacent to the sidewall of the adjacent step are removed to form the second groove.

In some specific embodiments, in step S204, the further forming a second groove penetrating through the first thickened layer and the second thickened layer includes:

performing oxidation treatment on the second thickened layer on the bottom and sidewall of the first groove to form an oxide layer;

removing the oxide layer, and the first thickened layer corresponding to the bottom of the first groove and the sidewall of each step, forming a second thickened layer that runs through the first thickened layer and the second thickened layer. groove.

Referring to FIG. 3 h , the second thickened layer 3032 at the bottom and sidewalls of the first groove 307 is completely oxidized, and part of the second thickened layer 3032 at the top of each step is oxidized to form an oxide layer 308 .

Here, the second thickened layer 3032 may be oxidized by using a low-pressure thermal oxidation process, such as an in-situ water vapor generation ISSG process, to form the oxide layer 308 .

It should be noted that the ISSG process is a rapid thermal annealing process, which can heat and cool the wafer in a short period of time, with a small thermal budget and good temperature uniformity. The ISSG process usually adds a small amount of hydrogen as a catalyst in an oxygen atmosphere, and a chemical reaction similar to combustion occurs on the front of the wafer at high temperature. This reaction generates a large number of active free radicals in the gas phase, namely atomic oxygen, which participate in the oxidation process of the silicon wafer. The oxidation process is fast, but the quality of the oxide layer is average. In the subsequent steps of this application, the oxide layer needs to be removed, therefore, the quality of the oxide layer is not a major concern.

Next, referring to FIG. 3 i , the oxide layer 308 and the first thickened layer 3031 corresponding to the bottom of the first groove and the sidewall of each step are removed to form a second groove 309 .

The removal process includes but not limited to a wet etching process. In other words, in the embodiment of the present application, based on the first groove, a second groove penetrating through the first thickened layer and the second thickened layer may be formed through a wet etching process. The etchant used in the wet etching process includes but not limited to hydrofluoric acid and the like.

It should be noted that, under the etching conditions of an etchant such as hydrofluoric acid, the etching selectivity ratio of the oxide layer 308 is greater than the etching selectivity ratios of the first thickened layer 3031 and the second thickened layer 3032. Therefore, using When an etchant such as hydrofluoric acid removes the oxide layer 308 , the etching rate is faster, which is beneficial for the complete removal of the oxide layer 308 .

It should be noted that in the embodiment of the present application, only one method of modifying part of the second thickened layer is shown. In other embodiments, ion implantation, Thermal diffusion, etc., to form an oxide layer, the main principle is to increase the etching selectivity of the second thickened layer located at the bottom and side walls of the first groove, so that after the formation of the second groove, there is no Residual second thickened layer; in this way, the occurrence of electrical connection problems between different gate layers caused by the second thickened layer remaining in the second groove in the subsequent process can be avoided; thereby improving the reliability of the semiconductor structure .

Step S205 is executed to form a gate, a gate thickening layer and a gate contact.

In some embodiments, the method includes:

After forming the second groove, a dielectric layer is formed in the second groove and on the top surface of the first stepped structure.

Referring to FIG. 3j , the dielectric layer 310 filling the step region can be formed by HDPCVD (High-Density Plasma Chemical Vapor Deposition) or plasma-enhanced chemical vapor deposition (PECVD, PlasmaEnhanced Chemical Vapor Deposition) process. Here, the material of the dielectric layer 310 includes but not limited to tetraethyl orthosilicate (TEOS). Afterwards, the surface of the dielectric layer 310 may be planarized by a chemical mechanical polishing (CMP, Chemical Mechanical Polishing) process.

In some embodiments, the removal of the sacrificial layer and the remaining thickening layer to form a gate and a thickening layer of the gate includes:

After forming the dielectric layer, removing the sacrificial layer and the remaining thickening layer in the first stacked structure to form a first gap;

filling the first gap with a first conductive material to form the gate and the gate thickening layer.

Referring to FIG. 3k , the remaining sacrificial layer 301 , the first thickened layer 3031 , and the second thickened layer 3032 are removed through a wet etching process to form a first gap 311 .

Referring to FIG. 3 l , the first gap 311 is filled with a first conductive material to form the gate 312 and the gate thickening layer 313 . The first conductive material includes but not limited to metal tungsten. The method of forming the first conductive material includes but not limited to PVD process, CVD process or ALD process.

In some embodiments, as shown in FIG. 3m, FIG. 3n, and FIG. 3o, forming a gate contact on each step includes:

A third groove 314 penetrating through the dielectric layer 310 is formed on each step;

The second conductive material is filled in the third groove 314 to form a plurality of gate contacts 316; each gate contact 316 is electrically connected to the gate 312 on the corresponding layer step.

Referring to FIG. 3m , the third groove may penetrate the dielectric layer 310 and the thickened gate layer 313 and directly contact the gate 312 , or may only penetrate the dielectric layer 310 and indirectly contact the gate 312 through the thickened gate layer 313 . The method of forming the third groove 314 includes but not limited to dry etching process.

Referring to FIG. 3n, in some embodiments, the semiconductor structure further includes an adhesive layer 315; the adhesive layer 315 is located at least between the gate contact 316 and the dielectric layer 310; in some specific embodiments , the adhesive layer 315 is also located between the gate contact 316 and the gate, gate contact and gate thickening layer 313; wherein, the adhesive layer is used to reduce the gate contact 316 and the gate 312 and the contact resistance between the gate contact 316 and the gate thickening layer 313 .

Based on this, the method of forming a semiconductor structure further includes:

Before filling the second conductive material in the third groove 314, an adhesive layer 315 is formed on the bottom and sidewall of the third groove; the material of the adhesive layer 315 includes but not limited to metal silicide, Such as nickel silicide, etc.; the method of forming the bonding layer 315 includes but not limited to PVD process, CVD process or ALD process.

Next, referring to FIG. 3 o , in the third groove formed with the adhesive layer 315 , a second conductive material is deposited to form the plurality of gate contacts 316 . The material of the gate contact 316 includes but not limited to metal tungsten; the deposition process includes but not limited to PVD process, CVD process or ALD process.

Based on this, in the embodiment of the present application, in the process of forming the second groove for electrically isolating the gate thickening layer on the top surface of two adjacent steps, by first forming only the penetrating part for forming the gate thickening layer The second thickened layer of the thick layer to form the first groove, and then based on the first groove, the second thickened layer under the first groove and the second thickened layer under the second thickened layer that are also used to form the gate increaser are removed. The first thickened layer of the thick layer, thereby forming the second groove; because the first groove is shallow, the amount of the second thickened layer removed by etching is less, so that the process window for forming the first groove is increased, Furthermore, the bottom of the first groove is far away from the gate layer. Based on the first groove, when the second groove with the effect of gate electrical isolation is further formed, the process control difficulty of the second groove is reduced, and the process The window is enlarged, so that the accuracy and reliability of the electrical connection between the gate contact and the gate can be better ensured.

A semiconductor structure provided by the present application, the semiconductor structure is obtained by using the manufacturing method of the semiconductor structure described in the above-mentioned embodiments of the present application, including:

The first stacked structure; the first stacked structure includes several insulating layers and gates stacked alternately, at least one side of the stacked structure is formed with a first ladder structure; the top of each layer of the first ladder structure The surface is the grid;

A gate thickening layer; located on the top surface of each step of the first stepped structure; wherein, the gate thickening layers on the top surfaces of the steps of two adjacent layers are electrically isolated from each other;

A gate contact; located on each step; the gate contact is electrically connected to the gate on the corresponding step.

In some embodiments, the semiconductor structure further includes an adhesive layer; the adhesive layer is located at least between the gate contact and the dielectric layer.

A memory device provided by the present application includes: one or more semiconductor structures as described in the foregoing embodiments of the present application.

A memory system provided by the present application includes: the memory device as described in the foregoing embodiments of the present application; and

The memory controller is connected with the memory device and used for controlling the memory device.

It should be noted that: "first", "second", etc. are used to distinguish similar objects, and not necessarily used to describe a specific order or sequence.

In addition, the technical solutions described in the embodiments of the present application may be combined arbitrarily if there is no conflict.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application.

Claims (12)

1. A method for manufacturing a semiconductor structure, characterized in that the method comprises: A first stacked structure is provided; the first stacked structure includes several insulating layers and sacrificial layers stacked alternately, at least one side of the first stacked structure is formed with a first stepped structure, and each layer of the first stepped structure The top surface of the ladder is a sacrificial layer; forming a thickened layer covering the first stepped structure, the thickened layer comprising a first thickened layer and a second thickened layer stacked in sequence; A first groove penetrating part of the second thickened layer is formed on each step; Based on the first groove, further forming a second groove penetrating through the first thickened layer and the second thickened layer; removing the sacrificial layer and the remaining thickening layer to form a gate and a thickening layer for the gate, and forming a gate contact on each of the steps; wherein, the second groove makes two adjacent layers The gate thickening layers on the top surfaces of the steps are electrically isolated from each other. 2 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the first groove penetrating part of the second thickened layer is formed on each step, comprising: Removing part of the second thickened layer at the position where the top surface of each step is close to the side wall of the adjacent step to form the first groove; The further forming a second groove penetrating through the first thickened layer and the second thickened layer includes: The second thickened layer and the first thickened layer corresponding to the bottom of the first groove and the adjacent step sidewalls are removed to form the second groove. 3. The method for manufacturing a semiconductor structure according to claim 2, wherein, based on the first groove, a second groove penetrating through the first thickened layer and the second thickened layer is further formed ,include: Based on the first groove, oxidize the second thickened layer on the bottom and sidewall of the first groove to form an oxide layer; removing the oxide layer, and the first thickened layer corresponding to the bottom of the first groove and the sidewall of each step, forming a second thickened layer that runs through the first thickened layer and the second thickened layer. groove. 4. The method for manufacturing a semiconductor structure according to claim 2, wherein the first groove penetrating part of the second thickened layer is formed on each step, comprising: Removing part of the second thickened layer at the position where the top surface of each step is close to the sidewall of the adjacent step by a dry etching process to form the first groove; The further forming a second groove penetrating through the first thickened layer and the second thickened layer includes: The second thickened layer and the first thickened layer corresponding to the bottom of the first groove and adjacent to the sidewall of the adjacent step are removed by wet etching process to form the second groove. 5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The first stack structure provided includes: providing a second stack structure comprising several alternately stacked insulating layers and sacrificial layers; Etching the second stacked structure to form a second stepped structure on at least one side of the second stacked structure; wherein, the top surface of each step of the second stepped structure is an insulating layer; The insulating layer on the top surface of each step of the second step structure is removed to form a first stack structure having the first step structure. 6. The method for manufacturing a semiconductor structure according to claim 1, wherein the forming a gate contact on each step comprises: After forming the second groove, a dielectric layer is formed in the second groove and on the top surface of the first stepped structure; A third groove penetrating through the dielectric layer is formed on each step; The third groove is filled with a second conductive material to form a plurality of gate contacts; each gate contact is electrically connected to a gate on a corresponding layer step. 7. The manufacturing method of the semiconductor structure according to claim 6, wherein the removal of the sacrificial layer and the remaining thickening layer to form a gate and a thickening layer of the gate comprises: After forming the dielectric layer, removing the sacrificial layer and the remaining thickening layer in the first stacked structure to form a first gap; filling the first gap with a first conductive material to form the gate and the gate thickening layer. 8. The manufacturing method of the semiconductor structure according to claim 1, wherein the method further comprises: Before forming the first groove, forming a mask layer covering the second thickened layer and a solidified layer covering the mask layer; removing the solidified layer on the sidewall of each step to form a second gap at a position where the top surface of each step in the first step structure is close to the sidewall of the step; removing part of the second thickened layer based on the second gap to form the first groove; Before forming the second groove, the remaining mask layer and the remaining cured layer are removed. 9. The method for manufacturing a semiconductor structure according to claim 1, wherein the material of the first thickened layer comprises a first silicon nitride; the material of the second thickened layer comprises a second silicon nitride The material of the sacrificial layer includes third silicon nitride; the etching selectivity ratios of the first silicon nitride, the second silicon nitride and the third silicon nitride are all different. 10. A semiconductor structure obtained by using the method for manufacturing a semiconductor structure according to any one of claims 1-9, characterized in that it comprises: The first stacked structure; the first stacked structure includes several insulating layers and gates stacked alternately, at least one side of the stacked structure is formed with a first ladder structure; the top of each layer of the first ladder structure The surface is the grid; A gate thickening layer; located on the top surface of each step of the first stepped structure; wherein, the gate thickening layers on the top surfaces of the steps of two adjacent layers are electrically isolated from each other; A gate contact; located on each step; the gate contact is electrically connected to the gate on the corresponding step. 11. A memory device, comprising: one or more semiconductor structures as claimed in claim 10. 12. A memory system, comprising: the memory device according to claim 11 ; and The memory controller is connected with the memory device and used for controlling the memory device.

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