CN107527820A - A kind of preparation method of PMOS device - Google Patents

Abstract

The invention provides a kind of preparation method of PMOS device, belong to power semiconductor device technology field.The present invention in deep groove structure by introducing gate electrode and the strain dielectric layer located at gate electrode periphery, so as to which semiconductor material regions apply compression strain where flow channel, hole mobility is lifted by compression strain, device hole current in forward conduction is caused to flow through the lower path of conducting resistance, so as to reduce the conducting resistance of device；Simultaneously as drift region produces the transverse electric field of assisted depletion drift region with introducing gate electrode, it is possible to increase device it is reverse pressure-resistant.The present invention compares the preparation technology of existing super-junction structure, avoids the problem of technological requirement difficulty present in multiple extension alignment precision and charge balance control is big, thus has inexpensive and simple to operate advantage, is advantageous to the production of Large scale processes metaplasia.

Description

A kind of manufacturing method of PMOS device

technical field

The invention belongs to the technical field of power semiconductors, and in particular relates to a manufacturing method of a PMOS device.

Background technique

Two key parameters of a power Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) are breakdown voltage BV and on-resistance R _on . Since MOSFET devices are unipolar devices, their breakdown voltage is related to the thickness of the drift region and the doping concentration of the drift region. A high breakdown voltage requires a thick drift region and a low doping concentration of the drift region, but this will make its conduction The on-resistance R _on increases. There is a relationship between the on-resistance R _on and the withstand voltage BV: Ron∝BV ^2.5 , which is the silicon limit. Therefore, as the withstand voltage of the device increases, the on-resistance increases exponentially, and the power consumption increases greatly. In particular, the on-resistance in typical high-voltage MOSFET devices is mainly determined by the drift region resistance. Therefore, it is of great significance to reduce the on-resistance by reducing the resistance of the drift region without affecting the breakdown voltage performance of the device. Based on the improvement of the traditional MOSFET structure, academician Chen Xingbi and others proposed a vertical superjunction structure, which replaces the original lightly doped region as the drift region by introducing alternately arranged P regions and N regions in the drift region of traditional MOSFET devices. , the introduction of the transverse electric field makes the longitudinal electric field change from a triangle (or trapezoidal distribution) to a rectangular distribution due to the two-dimensional electric field effect, thereby increasing the breakdown voltage, breaking the silicon limit, and optimizing the relationship between the on-resistance and the breakdown voltage as Ron ∝BV ^1.32 , which significantly improves the relationship between on-resistance and breakdown voltage of power MOSFET devices, that is, while enhancing the breakdown voltage performance of the device, it also reduces the on-resistance of the device. However, it is still difficult to realize high-performance power MOS devices. First, as far as VDMOS devices are concerned, the higher the withstand voltage, the deeper the vertical P-type column region and the N-type column region. The conventional super-junction structure adopts multiple Epitaxy, multiple implants, and annealing form P-type column regions and N-type column regions alternately distributed vertically. On the one hand, this manufacturing process requires a lot of epitaxy and implantation times when producing large-depth P-type column regions and N-type column regions. As a result, the process is difficult and costly; on the other hand, it is difficult to form high concentration and high density (that is, narrow P-type pillar regions and narrow N-type pillar regions alternately) with this manufacturing process, thus limiting the on-resistance of the device further decrease. Secondly, the electrical performance of superjunction devices is very sensitive to charge imbalance, which means that the width and concentration of the P-type pillar region and N-type pillar region must be precisely controlled in the process, otherwise the electrical performance of the device will be degraded. From this point of view It also increases the difficulty of the process. Furthermore, the junction surface of the lateral PN junction inside the device increases, causing defects such as the reverse recovery of the body diode of the device to become hard, and there will be a decrease in reliability in applications with high currents and conduction due to the expansion of the depletion layer of the lateral PN junction. The problem of resistance drop.

Contents of the invention

The technical problem to be solved by the present invention is to provide a manufacturing method of a PMOS device with low process precision requirements, low on-resistance and high withstand voltage performance.

In order to solve the problems of the technologies described above, the technical solutions provided by the invention are as follows:

A method for manufacturing a PMOS device, comprising:

Provide a semiconductor substrate formed with a deep trench gate structure, form a metallized source on the surface of the semiconductor substrate, and form a metallized drain after thinning the semiconductor substrate and the metallized back; it is characterized in that: the step of forming the deep trench gate structure includes :

A strain medium layer (5) is formed on the bottom sidewall and bottom wall of the deep groove (4), and the material of the strain medium layer (5) has compressive strain characteristics; a medium layer is formed on the surface of the strain medium layer (5) (6); then form the first grid electrode (71) at the bottom of the deep groove (4); the upper surface of the first grid electrode (71) coincides with the upper surface of the dielectric layer (6) and the strained dielectric layer (5) ; Form the oxide layer (8) on the upper surface of the first gate electrode (71), the dielectric layer (6) and the strained dielectric layer (5) in the deep groove (4); on the oxide layer (8) Form the gate dielectric layer (9) on the sidewall of the deep trench; then etch the oxide layer (8) to expose the first gate electrode (71); A second gate electrode (72) in contact with the two; finally an isolation dielectric layer (12) is formed between the second gate electrode (72) and the source metal (15).

Further, the specific operation of forming the strain medium layer in the present invention is as follows:

The substrate is subjected to deoxidation treatment at a temperature of 800-900°C, then a buffer layer is epitaxially grown at a temperature of 700-760°C, and a strained medium layer (5) is epitaxially grown at a temperature of 600-650°C.

Further, in order to make the strain medium layer (5) have compressive strain characteristics, the thickness of the strain medium layer (5) is smaller than its critical thickness.

Further, in order to prevent the lining bias effect and to turn on the parasitic triode when withstand voltage ^, the present invention makes the N ⁺ contact region ⁽ 13) is lower than the upper surface of the P ⁺ source region (11), and the lower surface junction depth of the N ⁺ contact region (14) is greater than the lower surface junction depth of the P ⁺ source region (11), so that the source metal ( 15) Contacting the P ⁺ source region (11) and the N-type body region (9) simultaneously.

Further, the material of the strain medium layer (5) is preferably SiGe.

Further, the junction depth on the upper surface of the second gate electrode (72) is smaller than the junction depth on the lower surface of the P ⁺ source region (11) in the present invention, and the junction depth on the lower surface of the second gate electrode (72) is greater than N The lower surface junction depth of the body region (10).

Further, in order to prevent the strained dielectric layer (5) from contacting the second gate electrode (72), the thickness of the oxide layer (8) on the inner wall of the deep groove in the present invention is respectively greater than the thickness of the strained dielectric layer (5) on the inner side of the deep groove and the thickness of the gate dielectric layer (9) on the inner wall of the deep groove.

Furthermore, in order to ensure sufficient voltage between gate and drain, the thickness of the oxide layer (8) along the longitudinal direction of the deep groove in the present invention is not less than the thickness of the dielectric layer (6).

Further, in order to make the absolute value of the threshold voltage of the device smaller, the thickness of the strained dielectric layer (5) on the inner wall of the deep groove is greater than the thickness of the gate dielectric layer (9) on the inner wall of the deep groove.

Further, the material of the first gate electrode (71) and the second gate electrode (72) is preferably polysilicon material.

Compared with the prior art, the beneficial effects of the present invention are:

(1). The PMOS device prepared by the preparation method of the present invention has high withstand voltage performance and low on-resistance; the present invention introduces the gate electrode and the strained dielectric layer arranged on the periphery of the gate electrode in the deep groove structure, due to the strained dielectric The layer is set in the flow channel of the hole current in the PMOS device, which can apply compressive stress to the semiconductor material area where the flow channel is located, and because the strained dielectric layer has a compressive stress that can increase the mobility of the holes, so holes are formed in the strained dielectric layer The accumulation layer further reduces the resistance of the strained dielectric layer, causing the hole current to flow through a path with lower on-resistance when the device is conducting forward, thereby reducing the on-resistance of the device; at the same time, due to the auxiliary The lateral electric field that depletes the drift region can increase the reverse withstand voltage of the device, thereby allowing the device to adopt a higher concentration of the drift region, thereby reducing the on-resistance of the device.

(2). The present invention provides a method for preparing PMOS devices with high withstand voltage performance and low on-resistance, which avoids the existing process requirements of using multiple epitaxy overlay accuracy and charge balance control in the existing super junction structure preparation process Therefore, the present invention has the advantages of low cost and simple operation.

Description of drawings

Fig. 1 is a method flowchart of a kind of PMOS device provided by the present invention;

Fig. 2 is the structural representation that makes PMOS device according to the process flow provided by the present invention;

Fig. 3 provides a kind of specific process flowchart of PMOS device for the present invention;

Among them, Figure (3-1) is a schematic diagram of epitaxially growing a drift region on a substrate according to an embodiment of the present invention;

Figure (3-2) is a schematic diagram of etching a deep groove on the drift region according to an embodiment of the present invention;

Figure (3-3) is a schematic diagram of an epitaxially grown strained medium layer material according to an embodiment of the present invention;

Figure (3-4) is a schematic diagram of depositing a dielectric layer material according to an embodiment of the present invention;

Figure (3-5) is a schematic diagram of depositing gate material according to an embodiment of the present invention;

Figure (3-6) is a schematic diagram of forming a first gate electrode, a dielectric layer and a strained dielectric layer by etching according to an embodiment of the present invention;

Figure (3-7) is a schematic diagram of depositing an oxide layer material according to an embodiment of the present invention;

Figure (3-8) is a schematic diagram of forming an oxide layer by etching according to an embodiment of the present invention;

Figure (3-9) is a schematic diagram of a thermally grown gate oxide layer material according to an embodiment of the present invention;

Figure (3-10) is a schematic diagram of etching the oxide layer to expose the first gate electrode according to an embodiment of the present invention;

Figure (3-11) is a schematic diagram of depositing gate material on the first gate electrode (71) and the oxide layer (8) according to an embodiment of the present invention;

Figure (3-12) is a schematic diagram of forming a second gate electrode and forming a body region and a source region by etching according to an embodiment of the present invention;

Figure (3-13) is a schematic diagram of depositing an isolation dielectric layer according to an embodiment of the present invention;

Figure (3-14) is a schematic diagram of forming a source contact hole by etching and performing NSD implantation on the hole region according to an embodiment of the present invention;

Figure (3-15) is a schematic diagram of depositing source metal, thinning the substrate, and backside metallization according to an embodiment of the present invention.

In the figure: 1 is the P ⁺ substrate, 2 is the P-type drift region, 3 is the mask layer, 4 is the deep groove, 5 is the strained dielectric layer, 6 is the dielectric layer, 71 is the first gate electrode, 72 is the second Gate electrode, 8 is an oxide layer, 9 is a gate dielectric layer, 10 is an N-type body region, 11 is a P ⁺ source region, 12 is an isolation dielectric layer, 13 is a source contact hole, 14 is an N ⁺ contact region, and 15 is a source pole metal, 16 is the drain metal.

detailed description

The present invention will be described more fully below with reference to the accompanying drawings, in which the same reference numerals represent the same or similar components or elements.

The gist of the present invention is to provide a method for preparing a strained PMOS device, by introducing a strained dielectric layer into the flow channel of the hole current of the device, so that the strained dielectric layer applies compressive stress to the semiconductor material region where the flow channel of the hole current is located, and then Improve hole mobility.

The semiconductor substrate provided by the present invention has an N-type body region 10, the N-type body region 10 is located on both sides of the deep trench gate or under the surface of the semiconductor substrate at the periphery, and the N-type body region 10 has a P ⁺ source region 11 and an N ⁺ contact region 14.

The semiconductor substrate provided by the present invention may have a silicon-on-insulator layer or an epitaxial layer structure on silicon, and any other suitable structures.

The manufacturing method of the PMOS device of the present invention is described in detail below in conjunction with specific embodiments. As shown in FIG ^. The step of forming the deep trench 4; the step of forming the strained dielectric layer 5, the dielectric layer 6 and the first gate electrode 71 distributed from outside to inside by epitaxial growth or deposition and etching at the bottom of the deep trench 4; The step of etching the oxide layer 8 in the deep groove; the step of forming the gate dielectric layer 9 on the inner wall of the deep groove above the oxide layer 8; The step of forming the second gate electrode 72 by depositing and etching on the electrode 71; forming an N-type body region 10 in the P-type drift region 2 on both sides of the deep trench 4 and forming a P ⁺ source region in the N-type body region 10 11 and the N ⁺ contact region 14; and the steps of forming an isolation dielectric layer 12 on the upper surface of the second gate electrode 72, depositing source metal, thinning the substrate and metallizing the back of the substrate.

Compared with the prior art, the present invention uses the technical means of "forming the strained dielectric layer 5, the dielectric layer 6 and the first gate electrode 71 distributed from the outside to the inside through epitaxial growth or deposition and etching at the bottom of the deep groove 4". The PMOS device has low on-resistance and high withstand voltage performance, and has the advantages of low cost and simple operation compared with the existing process for preparing a super junction structure.

The manufacturing process of the present invention is further described below in conjunction with the corresponding structural cross-sectional schematic diagrams of each step of making the PMOS device shown in Figure 3:

Example:

As shown in Figure 3, a specific embodiment of the present invention provides a method for manufacturing a PMOS device, comprising the following steps:

Step 1: As shown in Figure 3-1, epitaxially grow the P-type drift region 2 on the P ⁺ substrate 1, then grow the field oxide layer, and etch the field oxide layer in the active region; the substrate material of this embodiment is preferably For the bulk silicon material.

Step 2: As shown in Figure 3-2, etch a deep groove in the active region of the P-type drift region 2; the present invention does not limit the manufacturing process of the deep groove, and any suitable method can be used to form the deep groove.

Step 3: As shown in Figure 3-3, a layer of SiGe alloy thin film is epitaxially grown in the deep groove as the strained medium layer 5. The present invention does not limit the material of the strained medium layer 5 and its manufacturing process, and any suitable materials and any suitable method to form the strained dielectric layer 5; in this embodiment, the strained dielectric layer 5 is epitaxially grown by CVD, and the specific operations are as follows:

Deoxidize the silicon substrate at a temperature of 850°C, then epitaxially layer a silicon buffer layer at a temperature of 750°C, and epitaxially layer a SiGe alloy film at a temperature of 650°C;

Since the lattice constant of SiGe alloy is larger than that of bulk silicon material, SiGe alloy thin film epitaxial growth on bulk silicon substrate can obtain SiGe material with compressive strain characteristics. In order to ensure that SiGe material has compressive strain characteristic, this implementation requires SiGe alloy thin film The thickness of the SiGe alloy thin film is less than its critical thickness. According to the common knowledge in the art, the critical thickness is defined as: when the growth thickness of the SiGe alloy thin film is less than a certain thickness, the lattice distortion can be accommodated by elastic deformation, and when it exceeds the thickness, Part or all of the lattice distortion will be released by introducing misfit dislocations at the heterojunction interface, which is the critical thickness of the film.

Step 4: As shown in Figure 3-4, deposit a dielectric material on the surface of the strained dielectric layer 5; in order to achieve a better isolation effect, the material of the dielectric layer 6 in the present invention is silicon dioxide or any suitable high relative Dielectric constant material, preferably, the material of the dielectric layer 6 in the present invention includes but not limited to HfO ₂ , Si ₃ N ₄ , high relative permittivity material is conducive to the formation of a hole accumulation layer in the strained dielectric layer 5 .

Step 5: As shown in Fig. 3-5, deposit a gate material on the bottom of the deep trench 4; the gate material is preferably polysilicon, and it can be known from formulas in the field that it can be any suitable conductive material.

Step 6: As shown in Figure 3-6, remove the excess strained dielectric layer material, dielectric layer material and gate material on the semiconductor surface, and form the first gate electrode 71 through an etching process; the present invention does not limit the etching process, In this embodiment, dry etching is adopted. Specifically, the gate material on the top of the deep groove is first etched to form the first gate electrode 71, and then the dielectric layer material and the strained dielectric layer on the top of the deep groove are sequentially etched using the first gate electrode 71 as a barrier. The material further forms the dielectric layer 6 and the strained dielectric layer 5 , and the upper surfaces of the dielectric layer 6 , the strained dielectric layer 5 and the first gate electrode 71 are all located on the same plane by etching.

Step 7: As shown in Fig. 3-7, deposit an oxide layer material in the deep groove 4 obtained through step 6;

Step 8: As shown in Figure 3-8, back-etch the oxide layer material, remove all the oxide layer material on the semiconductor surface, and make the thickness of the remaining oxide layer in the deep groove 4 not less than the thickness of the dielectric layer 6 relative to the inner wall of the deep groove , so as to ensure that the gate-drain can withstand sufficient voltage.

Step 9: As shown in Figure 3-9, a thinner gate dielectric layer 9 is thermally grown on the sidewall of the deep groove above the oxide layer 8. The method of forming the gate dielectric layer 9 is not limited in the present invention. Growth can make the gate dielectric layer denser.

Step 10: As shown in Figure 3-10, etch and remove the oxide layer 8 in the central part to expose the upper surface or part of the upper surface of the first gate electrode; the oxide layer 8 left after etching should at least cover the dielectric layer 6 and the strained dielectric layer 5 to prevent gate-drain punch-through; due to the influence of photolithography precision, the oxide layer 8 left after etching can cover part of the upper surface of the first gate electrode 71;

Step 11: As shown in FIG. 3-11, deposit a gate material in contact with the first gate electrode 71 and the oxide layer 8; as mentioned above, the gate material is preferably polysilicon, which can be known according to common knowledge of formulas in the field : can be any suitable conductive material.

Step 12: As shown in Figure 3-12, etch to remove excess gate material on the semiconductor surface, and then prepare N-type body region 10 and P ⁺ source region 11 in the drift region on both sides of the deep groove. The methods of the type body region 10 and the P ⁺ source region 11 are not limited, and can be realized in any suitable manner according to the common knowledge in the art. Specifically, this embodiment adopts phosphorous ion or arsenic ion implantation followed by high-temperature advancement to form them under the semiconductor surface N-type body region 10, when the N-type body region is formed, the doping concentration of the N-type body region can be adjusted by ion implantation, and then boron ions are implanted with low energy, and then undergo rapid annealing to form under the surface of the N-type body region P ⁺ source region 11.

Step 13: As shown in FIG. 3-13, deposit an isolation dielectric layer material to form an isolation dielectric layer 12 on the upper surface of the second polysilicon 72 and the P ⁺ source region 11. In this embodiment, boron phosphorus is used as the isolation dielectric layer material Silicon glass BPSG, BPSG has good fluidity at high temperatures of 800°C to 950°C, and is widely used as an interlayer insulating film with good flatness on semiconductor surfaces; combined with common knowledge in the field, the material of the isolation dielectric layer is not limited to this embodiment BPSG, can also be any suitable material.

Step 14: As shown in FIG. 3-14, photolithography and etching treatment isolate the dielectric layer 12 and the source contact hole 13, and perform implantation of the N ⁺ contact region 14 by self-alignment. The specific operation is as follows:

In this embodiment, the source contact hole 13 is etched by dry method, and it can also be any other suitable method. The etching depth of the source contact hole 13 should be greater than the junction depth of the P ⁺ source region 11, so that the source metal 15 and the P ⁺ The source region 11 and the N-type body region 9 are in contact at the same time, thereby preventing the lining bias effect and the opening of the parasitic triode during withstand voltage;

NSD implantation is performed after the source contact hole 13 is etched, and an N ⁺ contact region 14 is formed at the bottom of the contact hole 13 by rapid annealing, thereby reducing the contact resistance between the body region and the source metal.

Step 15: As shown in FIG. 3-15 , form the source metal 15 on the upper surface of the N ⁺ contact region 14 and the isolation dielectric layer 12 according to the process sequence of deposition, photolithography, and etching metal materials; Thin, backside metallization treatment forms drain metal 16, the operation of this embodiment is specifically as follows:

Before depositing the source metal 15, BPSG high-temperature reflow is carried out. Because the reflow temperature is lower than the push-junction temperature, it will not have a great impact on the impurity distribution; after the reflow, the chamfer of the isolation dielectric layer 12 becomes rounded, which can reduce the source The stress of pole metal 15 here;

Depositing the source metal 15 is divided into two steps, first depositing a layer of thinner barrier metal, such as metal Co and metal Ti, to improve contact reliability; then sputtering a thicker source metal layer, usually the source The metal layer uses metal Al. Then photolithography and etching are performed on the source metal layer 14 to form structures such as source Pad and gate Pad; finally, the substrate is thinned and the metal drain 16 is fabricated on the back side.

The device structure prepared by the above preparation process is shown in Figure 2, including: a P ⁺ type substrate 1 with a drain metal 16 on the back side of the P ⁺ type substrate 1, and a drain metal 16 on the P ⁺ type substrate 1 There is a P-type drift region 2 on the front side of the P-type drift region 2, and an N-type body region 10 is provided under the surface of the P-type drift region 2, and a deep groove 4 is arranged in the N-type body region 10, and the deep groove 4 passes through the N-type body region 10 And the bottom end extends to the P-type drift region 2, the N-type body region 10 on both sides of the deep trench 4 has adjacent P ⁺ source region 11 and N ⁺ contact region 14 below the surface, and the upper surface of the P ⁺ source region 11 is high On the upper surface of the N ⁺ contact region 14, a source metal 15 in an inverted groove structure is connected on the surface of the P ⁺ source region 11 and the N ⁺ contact region 14, and the two ends of the source metal 15 are directed towards The lower extension is in contact with the side surfaces of the P ⁺ source region 11 and the upper surface of the N ⁺ contact region 14; it is characterized in that the deep groove 4 has a first gate electrode 71, a gate dielectric layer 9, a second gate electrode 72, a strain dielectric layer 5, dielectric layer 6 and oxide layer 8; the second gate electrode 72 and the P ⁺ source region 11 are isolated from the source metal 15 by the isolation dielectric layer 12, and the upper surface junction depth of the second gate electrode 72 is smaller than P ⁺ The lower surface junction depth of the source region 11, the lower surface junction depth of the second gate electrode 72 is greater than the lower surface junction depth of the N-type body region 10, and the top periphery of the second gate electrode 72 or the inner walls of the deep grooves on both sides are provided with The gate dielectric layer 9, the outer periphery of the bottom of the second gate electrode 72 or the inner walls of the deep grooves on both sides are provided with an oxide layer 8 in contact with the gate dielectric layer 9, and the first gate electrode 71 is located directly below the second gate electrode 72 and connected to it. In contact with each other, the inner wall of the deep groove on the periphery or both sides of the first gate electrode 71 is provided with a strained dielectric layer 5 and a dielectric layer 6 in sequence from the outside to the inside, and the material of the strained dielectric layer 5 has a compressive strain characteristic; the oxide layer 8 The lower surface or part of the lower surface is in contact with the upper surfaces of the strained dielectric layer 5 and the dielectric layer 6 .

Further, in the present invention, the upper surface junction depth of the second gate electrode 72 is smaller than the lower surface junction depth of the P ⁺ source region 11, and the lower surface junction depth of the second gate electrode 72 is greater than the lower surface junction depth of the N-type body region 10 in the present invention. The surface knot is deep.

Furthermore, in order to prevent the strained dielectric layer 5 from being in contact with the second gate electrode 72, the thickness of the oxide layer 8 on the inner wall of the deep groove in the present invention is greater than the thickness of the strained dielectric layer 5 on the inner side of the deep groove or the thickness of the gate dielectric layer 9 on the inner wall of the deep groove. The thickness of the inner wall.

Furthermore, in order to ensure sufficient voltage between the gate and the drain, the thickness of the oxide layer 8 along the longitudinal direction of the deep groove in the present invention is not less than the thickness of the dielectric layer 6 .

Further, in order to make the absolute value of the threshold voltage of the device smaller, the thickness of the strained dielectric layer 5 on the inner wall of the deep trench is greater than the thickness of the gate dielectric layer 9 on the inner wall of the deep trench.

Principle and characteristic of the present invention are described in detail below in conjunction with the device structure shown in Fig. 2:

Forward conduction characteristics of the device:

The connection mode of the electrodes of the PMOS device provided by the present invention is as follows: the second gate electrode 72 of the PMOS device is connected to a negative potential, the drain metal 16 is connected to a negative potential, and the source metal 15 is connected to a zero potential;

When the negative voltage applied by the first gate electrode 71 reaches the threshold voltage, an inversion channel is formed on the side close to the gate dielectric layer 9 in the N-type body region 10. Since the thickness of the gate dielectric layer 9 is relatively thin, the threshold voltage of the device is absolutely absolute. The value is small; at this time, under the negative bias of the drain metal 16, the holes as carriers pass from the P ⁺ source region 11 through the inversion channel formed in the N-type body region 10; because the deep groove 4 has a second Gate electrode 72, so a hole accumulation layer is formed in the strained dielectric layer 5, thereby reducing the resistance in the strained dielectric layer 5, that is, injecting the P-type drift region 2 through the strained dielectric layer 5 and then reaching the drain metal 16 to form a forward current Realize the conduction of the PMOS device; because the strained dielectric layer 5 adopts the SiGe alloy film formed by epitaxial growth on the bulk silicon, and the lattice constant of the SiGe alloy film is greater than that of the bulk silicon material, and the SiGe alloy epitaxial growth on the bulk silicon material substrate can be A compressively strained SiGe alloy thin film is obtained, and the strained dielectric layer 5 is located in the flow path of the multi-substance current in the PMOS device, while the multisubstances of the PMOS device are holes, and the compressive strain can increase the mobility of the holes, thereby reducing the on-resistance.

Device reverse blocking characteristics:

The electrode connection mode of the PMOS device provided by the present invention in reverse blocking is as follows: the drain metal 16 of the PMOS device is connected to a negative potential, and the second gate electrode 72 and the source metal 15 are short-circuited and connected to zero potential;

When the device is in the blocking state, the drain metal 16 applies a negative bias voltage, and the P-type drift region 2 begins to be depleted. Since the deep trench 4 is introduced into the PMOS device, and the first gate electrode 71 is introduced into the deep trench 4, when During reverse blocking, the P-type drift region 2 and the first gate electrode 71 generate a lateral electric field to assist in depleting the P-type drift region 2 and thereby improve the reverse withstand voltage of the device, so that under the same withstand voltage condition, the present invention The device can use a higher drift region concentration, which reduces the on-resistance of the device.

The embodiments of the present invention have been described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementations, which are only illustrative and not restrictive. Under the enlightenment of the present invention, those skilled in the art can also make many forms without departing from the gist of the present invention and the protection scope of the claims, and these all belong to the protection of the present invention.

Claims (9)

1. a kind of preparation method of PMOS device, including：The semiconductor base formed with deep slot grid structure is provided, semiconductor-based The surface at bottom forms metallizing source, and metalized drain is formed after semiconductor base and metalized backside is thinned；Its feature exists In：The step of forming deep slot grid structure includes：

Strain dielectric layer (5) is formed in the bottom sidewall and bottom wall of deep trouth (4), the material of the strain dielectric layer (5) has pressure Shrinkage strain characteristic；Dielectric layer (6) is formed on the surface of the strain dielectric layer (5)；Then the first grid is formed in deep trouth (4) bottom Electrode (71)；The upper surface of the first gate electrode (71) overlaps with the upper surface of dielectric layer (6) and strain dielectric layer (5)；Again Formed in deep trouth (4) positioned at first gate electrode (71), dielectric layer (6) and the oxide layer (8) for straining dielectric layer (5) upper surface； Deep trouth side wall on the oxide layer (8) forms gate dielectric layer (9)；Then etching oxidation layer (8) is electric to expose the first grid Pole (71)；The second gate electrode (72) contacted with the two is formed on first gate electrode (71) and oxide layer (8) again；Finally exist Spacer medium layer (12) is formed between second gate electrode (72) and source metal (15).

2. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that form the specific behaviour of strained layer Make as follows：Deoxidation treatment is carried out to substrate under 800~900 DEG C of temperature conditionss, then in 700~760 DEG C of temperature conditionss Lower one layer of cushion of extension, the extension strain dielectric layer (5) under 600~650 DEG C of temperature conditionss.

A kind of 3. preparation method of PMOS device according to claim 1, it is characterised in that the strain dielectric layer (5) Thickness be less than its critical thickness.

A kind of 4. preparation method of PMOS device according to claim 1, it is characterised in that second gate electrode (72) Upper surface junction depth be less than P⁺The lower surface junction depth of source region (11), the lower surface junction depth of second gate electrode (72) are more than N-type The lower surface junction depth in body area (10),.

5. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that oxide layer (8) is in deep trouth The thickness of wall be respectively greater than strain dielectric layer (5) deep trouth inwall thickness and gate dielectric layer (9) deep trouth inwall thickness.

6. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that oxide layer (8) is indulged along deep trouth It is not less than thickness of the dielectric layer (6) in deep trouth inwall to the thickness in direction.

A kind of 7. preparation method of PMOS device according to claim 1, it is characterised in that the strain dielectric layer (5) It is more than thickness of the gate dielectric layer (9) in deep trouth inwall in the thickness of deep trouth inwall.

8. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that the grid material is polycrystalline Silicon materials.

9. the preparation method of a kind of PMOS device according to claim 1 to 8, it is characterised in that separate being formed P⁺Source region (11) and N⁺In the operation of contact zone (14), by etching N⁺The upper surface of contact zone (13) is less than P⁺Source region (11) upper surface, and N⁺The lower surface junction depth of contact zone (14) is more than P⁺The lower surface junction depth of source region (11) so that source electrode gold Belong to (15) and P⁺Source region (11) and NXing Ti areas (9) contact.