CN107508556B - Design method of DE frequency multiplier - Google Patents
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Abstract
本发明公开了一种DE类倍频器的设计方法，包括直流电压源，第一场效应管、第二场效应管、第一电感、第二电感、隔直电容、并联补偿电容、LC并联调谐电路和负载电阻，隔直电容一端接第一电感和第二电感的一端，另一端分别接LC并联调谐电路、并联补偿电容和负载电阻的一端，第一电感的另一端串接第一场效应管的漏极，第二电感的另一端串接第二场效应管的漏极，LC并联调谐电路、并联补偿电容和负载电阻的另一端接电源地，第一场效应管S1源极接电源地，栅极接第一驱动电压，第二场效应管S2源极接直流电压源，栅极接第二驱动电压。本发明在不改变原DE类放大器结构和驱动信号波形下仅仅调整无源器件的元件值即可获得倍频信号。
The invention discloses a design method of a DE type frequency multiplier, comprising a DC voltage source, a first field effect transistor, a second field effect transistor, a first inductor, a second inductor, a DC blocking capacitor, a parallel compensation capacitor, and an LC parallel connection. Tuning circuit and load resistor, one end of the DC blocking capacitor is connected to one end of the first inductor and the second inductor, the other end is respectively connected to one end of the LC parallel tuning circuit, the parallel compensation capacitor and the load resistor, and the other end of the first inductor is connected in series with the first field The drain of the effect transistor, the other end of the second inductor is connected to the drain of the second field effect transistor in series, the other end of the LC parallel tuning circuit, the parallel compensation capacitor and the load resistor is connected to the power supply ground, the source of the first field effect transistor S 1 It is connected to the power supply ground, the gate is connected to the first driving voltage, the source of the second field effect transistor S2 is connected to the DC voltage source, and the gate is connected to the second driving voltage. In the invention, the frequency multiplication signal can be obtained only by adjusting the component value of the passive device without changing the structure of the original DE class amplifier and the driving signal waveform.
Description
技术领域technical field
本发明涉及一种DE类倍频器的设计方法，属于倍频器技术领域。The invention relates to a design method of a DE type frequency multiplier, and belongs to the technical field of frequency multipliers.
背景技术Background technique
倍频器是通信中的重要器件，通过倍频器可以获得数倍的源信号频率。晶体管倍频器除了可以实现频率倍增，其输出信号通常还有功率增益。晶体管倍频器与开关式放大器类似，有D类、E类、DE类等，通常都具有较高的效率。The frequency multiplier is an important device in communication, and the frequency multiplier can be used to obtain several times the frequency of the source signal. In addition to frequency multiplication, transistor frequency multipliers usually have power gain in their output signals. Transistor frequency multipliers are similar to switching amplifiers, including class D, class E, class DE, etc., and usually have higher efficiency.
发明内容SUMMARY OF THE INVENTION
本发明所要解决的技术问题是克服现有技术的缺陷，提供一种DE类倍频器的设计方法，在不改变原DE类放大器结构和驱动信号波形下仅仅调整无源器件的元件值即可获得倍频信号。The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a design method of a class DE frequency multiplier, which can only adjust the component values of the passive device without changing the structure of the original class DE amplifier and driving signal waveform. Get the multiplied signal.
为解决上述技术问题，本发明提供一种DE类倍频器的设计方法，包括以下步骤：In order to solve the above-mentioned technical problems, the present invention provides a design method of a class DE frequency multiplier, comprising the following steps:
1)DE类倍频器的驱动信号占空比为25％，当第一场效应管开关S1断开时，第一电感L1中的电流下降到0，且电流随时间的变化率为0，使得第一电感L1的功率损耗为0；当第一场效应管开关S2断开时，第二电感L2中的电流下降到0，且电流随时间的变化率为0，使得第二电感L2的功率损耗为0；根据此电感零电流转换和零电流导数转换条件，得到N倍频器中的参数关系：1) The duty cycle of the driving signal of the class DE frequency multiplier is 25%. When the first FET switch S1 is turned off, the current in the first inductor L1 drops to 0, and the change rate of the current with time is 0, so that the power loss of the first inductor L 1 is 0; when the first FET switch S 2 is turned off, the current in the second inductor L 2 drops to 0, and the rate of change of the current with time is 0, so that The power loss of the second inductor L 2 is 0; according to the zero current conversion and zero current derivative conversion conditions of this inductor, the parameter relationship in the N frequency multiplier is obtained:
其中，in,
B＝NωC是并联补偿电容C的电纳，B=NωC is the susceptance of the parallel compensation capacitor C,
X＝ωL1＝ωL2是串联电感L1和L2的感抗，X = ωL1 = ωL2 is the inductive reactance of series inductance L1 and L2,
ω＝2πf；ω=2πf;
2)给定DE类倍频器的设计参数，包括直流电压源Vdd，输出功率Po，负载品质因数QLC，驱动信号频率f和频率倍数N；2) Given the design parameters of the class DE frequency multiplier, including the DC voltage source V dd , the output power P o , the load quality factor Q LC , the drive signal frequency f and the frequency multiple N;
3)结合步骤1)的参数关系，负载电阻的表达式和DE类倍频器的设计参数，得到N倍频器的元件参数：负载电阻RL、第一电感L1、第二电感L2、并联补偿电容C、并联调谐电容Cp和并联调谐电感Lp；3) Combining the parameter relationship in step 1), the expression of the load resistance and the design parameters of the DE-type frequency multiplier, the component parameters of the N frequency multiplier are obtained: load resistance R L , first inductance L 1 , second inductance L 2 , parallel compensation capacitor C, parallel tuning capacitor C p and parallel tuning inductance L p ;
4)利用步骤3)的计算结果设计DE类倍频器。4) Use the calculation result of step 3) to design a class DE frequency multiplier.
前述的N倍频器中的N为奇数。N in the aforementioned N multiplier is an odd number.
前述的负载电阻RL满足：
前述的并联调谐电容Cp和并联调谐电感Lp的计算公式如下：The calculation formulas of the aforementioned parallel tuning capacitance C p and parallel tuning inductance L p are as follows:
进一步的，所述DE类倍频器包括直流电压源Vdd、第一场效应管S1、第二场效应管S2、第一电感L1、第二电感L2、隔直电容CDC、并联补偿电容C、LC并联调谐电路和负载电阻RL；Further, the class DE frequency multiplier includes a DC voltage source V dd , a first field effect transistor S 1 , a second field effect transistor S 2 , a first inductor L 1 , a second inductor L 2 , and a DC blocking capacitor C DC , parallel compensation capacitor C, LC parallel tuning circuit and load resistance RL ;
所述隔直电容CDC一端接第一电感L1和第二电感L2的一端，隔直电容CDC的另一端分别接LC并联调谐电路、并联补偿电容C和负载电阻RL的一端；所述第一电感L1的另一端串接第一场效应管S1的漏极；所述第二电感L2的另一端串接第二场效应管S2的漏极；所述LC并联调谐电路、并联补偿电容C和负载电阻RL的另一端接电源地；One end of the DC blocking capacitor C DC is connected to one end of the first inductor L1 and the second inductor L2, and the other end of the DC blocking capacitor C DC is respectively connected to one end of the LC parallel tuning circuit, the parallel compensation capacitor C and the load resistance RL ; The other end of the first inductor L1 is connected in series with the drain of the first field effect transistor S1; the other end of the second inductor L2 is connected in series with the drain of the second field effect transistor S2; the LCs are connected in parallel The other end of the tuning circuit, the parallel compensation capacitor C and the load resistor RL is connected to the power ground;
所述第一场效应管S1源极接电源地，栅极接第一驱动电压；The source of the first field effect transistor S1 is connected to the power supply ground, and the gate is connected to the first driving voltage;
所述第二场效应管S2源极接直流电压源Vdd，栅极接第二驱动电压。The source electrode of the second field effect transistor S 2 is connected to the DC voltage source V dd , and the gate electrode is connected to the second driving voltage.
进一步的，所述LC并联调谐电路包括调谐电容Cp和调谐电感Lp，其中，调谐电容Cp两端连接调谐电感Lp的两端，谐振于倍频目标频率。Further, the LC parallel tuning circuit includes a tuning capacitor C p and a tuning inductor L p , wherein both ends of the tuning capacitor C p are connected to both ends of the tuning inductor L p and resonate at the frequency multiplied target frequency.
本发明所达到的有益效果为：在不改变原DE类放大器结构和驱动信号波形下仅仅调整无源器件的元件值即可获得倍频信号，且保持很高的效率。The beneficial effects achieved by the invention are as follows: the frequency-doubling signal can be obtained by only adjusting the component value of the passive device without changing the structure of the original DE class amplifier and the driving signal waveform, and the high efficiency is maintained.
附图说明Description of drawings
图1是一种DE类倍频器的电路图；Figure 1 is a circuit diagram of a class DE frequency multiplier;
图2是一种DE类倍频器的等效电路；Figure 2 is an equivalent circuit of a class DE frequency multiplier;
图3是驱动信号占空比为25％，N＝3时，DE类3倍频器各电流电压波形图；图3(a)为第一场效应管的驱动电压波形vDr1(θ)；图3(b)为第二场效应管的驱动电压波形vDr2(θ)；图3(c)为流过第一场效应管S1的电流is1(θ)的波形图；图3(d)为流过第二场效应管S2的电流is2(θ)的波形图；图3(e)为第一场效应管漏极的电压波形vD1(θ)；图3(f)为第二场效应管漏极电压波形vD2(θ)；图3(g)是输出电压波形vo(θ)。Figure 3 is the current and voltage waveforms of the
具体实施方式Detailed ways
下面对本发明作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。The present invention is further described below. The following examples are only used to illustrate the technical solutions of the present invention more clearly, and cannot be used to limit the protection scope of the present invention.
如图1所示，本发明的DE类倍频器包括直流电压源Vdd，第一场效应管S1、第二场效应管S2、第一电感L1、第二电感L2、隔直电容CDC、并联补偿电容C、LC并联调谐电路和负载电阻RL。图1中，vDr1(θ)和vDr2(θ)是第一、二场效应管驱动电压，vs2(θ)，is2(θ)是第二场效应管漏源极电压和流过它的电流，i1(θ)是流过隔直电容的交变电流，vm(θ)是第一电感L1和第二电感L2连接点的电压，vs1(θ)和is1(θ)是第一场效应管漏源极电压和流过它的电流，ix(θ)是并联补偿电容C中的电流，io(θ)是负载电阻RL中的电流，vo(θ)是负载电阻上的电压，θ是角时间,，θ＝ωt。As shown in FIG. 1 , the class DE frequency multiplier of the present invention includes a DC voltage source V dd , a first field effect transistor S 1 , a second field effect transistor S 2 , a first inductor L 1 , a second inductor L 2 , a spacer Direct capacitance C DC , parallel compensation capacitance C, LC parallel tuning circuit and load resistance RL . In Figure 1, v Dr1 (θ) and v Dr2 (θ) are the driving voltages of the first and second FETs, v s2 (θ), i s2 (θ) are the drain-source voltages of the second FET and the flow through Its current, i 1 (θ) is the alternating current flowing through the DC blocking capacitor, vm (θ) is the voltage at the junction of the first inductor L 1 and the second inductor L 2 , v s1 (θ) and i s1 (θ) is the drain-source voltage of the first FET and the current flowing through it, i x (θ) is the current in the parallel compensation capacitor C, i o (θ) is the current in the load resistor RL , v o (θ) is the voltage across the load resistance, θ is the angular time, and θ=ωt.
隔直电容CDC一端接第一电感L1和第二电感L2的一端，另一端分别接LC并联调谐电路、并联补偿电容C和负载电阻RL的一端。One end of the blocking capacitor C DC is connected to one end of the first inductor L1 and the second inductor L2, and the other end is respectively connected to one end of the LC parallel tuning circuit, the parallel compensation capacitor C and the load resistor RL .
LC并联调谐电路、并联补偿电容C和负载电阻RL的另一端接电源地。The other end of the LC parallel tuning circuit, the parallel compensation capacitor C and the load resistor RL is connected to the power ground.
第一场效应管S1源极接电源地，栅极接第一驱动电压，漏极串联接第一电感L1的另一端。The source of the first field effect transistor S1 is connected to the power supply ground, the gate is connected to the first driving voltage, and the drain is connected to the other end of the first inductor L1 in series.
第二场效应管S2源极接直流电压源Vdd，栅极接第二驱动电压，漏极串联接第二电感L2的另一端。The source of the second field effect transistor S2 is connected to the DC voltage source Vdd , the gate is connected to the second driving voltage, and the drain is connected to the other end of the second inductor L2 in series.
LC并联调谐电路包括调谐电容Cp和调谐电感Lp，其中，调谐电容Cp两端连接调谐电感Lp的两端，谐振于倍频目标频率。The LC parallel tuning circuit includes a tuning capacitor C p and a tuning inductor L p , wherein the two ends of the tuning capacitor C p are connected to the two ends of the tuning inductor L p and resonate at the target frequency of frequency multiplication.
图2是DE类倍频器的等效电路。将第一场效应管S1、第二场效应管S2等效为两个电压控制开关。Figure 2 is the equivalent circuit of a class DE frequency multiplier. The first field effect transistor S 1 and the second field effect transistor S 2 are equivalent to two voltage-controlled switches.
DE类倍频器的驱动信号占空比为25％。当第一场效应管开关S1断开时，第一电感L1中的电流下降到0，且电流随时间的变化率(即电流的斜率)为0，使得第一电感L1的功率损耗为0。当第一场效应管开关S2断开时，第二电感L2中的电流下降到0，且电流随时间的变化率(即电流的斜率)为0，使得第二电感L2的功率损耗为0。The drive signal duty cycle of the Class DE frequency multiplier is 25%. When the first FET switch S 1 is turned off, the current in the first inductor L 1 drops to 0, and the rate of change of the current with time (ie, the slope of the current) is 0, so that the power loss of the first inductor L 1 is 0. When the first FET switch S 2 is turned off, the current in the second inductor L 2 drops to 0, and the rate of change of the current with time (ie the slope of the current) is 0, so that the power loss of the second inductor L 2 is 0.
运用以上电感零电流转换和零电流导数转换条件，得到N倍频器(N是奇数)中的参数关系：Using the above inductor zero-current conversion and zero-current derivative conversion conditions, the parameter relationship in the N frequency multiplier (N is an odd number) is obtained:
其中：in:
B＝NωC是并联补偿电容C的电纳，B=NωC is the susceptance of the parallel compensation capacitor C,
X＝ωL1＝ωL2是串联电感L1和L2的感抗。X=ωL 1 =ωL 2 is the inductive reactance of the series inductances L 1 and L 2 .
ω＝2πf。ω=2πf.
为了方便N倍频器的设计，将奇数N＝3、5、7对应的设计参数列于表1：In order to facilitate the design of the N frequency multiplier, the design parameters corresponding to the odd N=3, 5, and 7 are listed in Table 1:
表1N倍频器的参数关系Table 1. Parameter relationship of N frequency multiplier
图3是驱动信号占空比D＝25％时，DE类3倍频器实例在一个2π周期内的工作过程为：Figure 3 shows the working process of the
(1)在0＜θ≤0.5π，如图3(a)驱动信号使第一场效应管S1闭合；如图3(b)驱动信号使第二场效应管S2断开；如图3(c)流过第一场效应管S1的电流iS1(也是流过第一电感L1的电流)有一个上升的过程，上升到峰值后出现一个下降的过程，最后到0，到达0时电流iS1随时间的导数也为0；如图3(e),第一场效应管漏极电压为0，即第一场效应管S1两端电压vS1为0；如图3(d)，流过第二场效应管S2的电流iS2(也是流过第二电感L2的电流)为0；如图3(f)，第二场效应管S2断开,第二场效应管漏极电压vD2随输出电压变化。(1) When 0<θ≤0.5π, as shown in Fig. 3(a), the driving signal makes the first FET S1 closed; as shown in Fig. 3(b), the driving signal makes the second FET S2 open; as shown in Fig. 3(b) 3(c) The current i S1 flowing through the first FET S 1 (also the current flowing through the first inductor L 1 ) has a rising process, rises to a peak value and then has a falling process, and finally reaches 0, reaching At 0, the derivative of current i S1 with time is also 0; as shown in Figure 3(e), the drain voltage of the first FET is 0, that is, the voltage v S1 across the first FET S 1 is 0; as shown in Figure 3 (d), the current i S2 flowing through the second field effect transistor S 2 (also the current flowing through the second inductor L 2 ) is 0; The drain voltage v D2 of the two FETs varies with the output voltage.
(2)在0.5π＜θ≤π，如图3(a)驱动信号使第一场效应管S1断开；如图3(b)驱动信号使第二场效应管S2断开。图3(c)流过第一场效应管电流iS1(也是流过第一电感L1的电流)为0；如图3(e)，第一场效应管S1断开,第一场效应管漏极电压vD1随输出电压变化；图3(d)流过第二场效应管电流iS2(也是流过第二电感L2的电流)为0；如图3(f)，第二场效应管S2断开,第二场效应管漏极电压vD2随输出电压变化。(2) When 0.5π<θ≤π, as shown in Fig. 3(a), the first FET S1 is turned off by the driving signal; as shown in Fig. 3(b), the second FET S2 is turned off by the driving signal. In Fig. 3(c), the current i S1 flowing through the first FET (also the current flowing through the first inductor L 1 ) is 0; The drain voltage v D1 of the effect transistor varies with the output voltage; Fig. 3(d) flows through the second FET current i S2 (also the current flowing through the second inductor L 2 ) is 0; as shown in Fig. 3(f), the first The second field effect transistor S2 is disconnected, and the drain voltage v D2 of the second field effect transistor changes with the output voltage.
(3)在π＜θ≤1.5π，如图3(a)驱动信号使第一场效应管S1断开；如图3(b)驱动信号使第二场效应管S2闭合；图3(c)流过第一场效应管电流iS1(也是流过第一电感L1的电流)为0；如图3(e)，第一场效应管S1断开,第一场效应管漏极电压vD1随输出电压变化；图3(d)，流过第二场效应管S2的电流iS2(也是流过第二电感L2的电流)有一个上升的过程，上升到峰值后出现一个下降的过程，最后到0，到达0时电流iS2随时间的导数也为0；图3(f)，第二场效应管漏极电压等于直流电源电压，即第二场效应管S2两端电压vS2为0。(3) When π<θ≤1.5π, as shown in Fig. 3(a), the driving signal makes the first field effect transistor S1 open; as shown in Fig. 3(b), the driving signal makes the second field effect transistor S2 close; (c) The current i S1 flowing through the first FET (also the current flowing through the first inductor L 1 ) is 0; The drain voltage v D1 changes with the output voltage; Figure 3(d), the current i S2 flowing through the second FET S 2 (also the current flowing through the second inductor L 2 ) has a rising process, rising to a peak value Then there is a process of decline, and finally it reaches 0. When it reaches 0, the derivative of current i S2 with time is also 0; Figure 3(f), the drain voltage of the second FET is equal to the DC power supply voltage, that is, the second FET The voltage v S2 across S 2 is 0.
(4)在1.5π＜θ≤2π，此范围内工作过程同(2)。如图3(a)驱动信号使第一场效应管S1断开；如图3(b)驱动信号使第二场效应管S2断开。图3(c)流过第一场效应管电流iS1(也是流过第一电感L1的电流)为0；如图3(e)，第一场效应管S1断开,第一场效应管漏极电压vD1随输出电压变化；图3(d)流过第二场效应管电流iS2(也是流过第二电感L2的电流)为0；如图3(f)，第二场效应管S2断开,第二场效应管漏极电压vD2随输出电压变化。(4) In the range of 1.5π<θ≤2π, the working process is the same as (2). As shown in Fig. 3(a), the driving signal causes the first FET S1 to be disconnected; as shown in Fig. 3(b), the driving signal causes the second FET S2 to be disconnected. In Fig. 3(c), the current i S1 flowing through the first FET (also the current flowing through the first inductor L 1 ) is 0; The drain voltage v D1 of the effect transistor varies with the output voltage; in Fig. 3(d), the current i S2 flowing through the second FET (also the current flowing through the second inductor L 2 ) is 0; as shown in Fig. 3(f), the first The second field effect transistor S2 is disconnected, and the drain voltage v D2 of the second field effect transistor changes with the output voltage.
图3(g)是输出电压波形，输出电信号电压是直流电压源Vdd的2.9倍，频率是驱动信号的3倍，实现了3倍频。Figure 3(g) is the output voltage waveform, the output electrical signal voltage is 2.9 times that of the DC voltage source V dd , and the frequency is 3 times that of the driving signal, achieving triple frequency.
给定DE类倍频器的设计参数，包括直流电压源Vdd，输出功率Po，负载品质因数QLC，驱动信号频率f和频率倍数N，结合参数关系以及负载电阻的表达式，得到DE类倍频器元件的各参数：Given the design parameters of the class DE frequency multiplier, including the DC voltage source V dd , the output power P o , the load quality factor Q LC , the driving signal frequency f and the frequency multiple N, combined with the parameter relationship and the expression of the load resistance, DE can be obtained Parameters of frequency doubler-like components:
其中，负载电阻满足：
LC并联调谐电路用于提取所需的频率，LC并联调谐电路的元件参数为：The LC parallel tuning circuit is used to extract the desired frequency, and the component parameters of the LC parallel tuning circuit are:
ω＝2πfω=2πf
输出电压为：
在驱动信号占空比为25％时，当N＝3时，即DE-1类3倍频器，输出信号电压是直流电源电压Vdd的2.9倍，频率是驱动信号的3倍，实现了3倍频。其负载电阻RL、第一电感L1、第二电感L2、并联补偿电容C、并联调谐电容Cp和并联调谐电感Lp的计算公式(隔直电容CDC只需足够大，不需要特别计算)；When the duty cycle of the driving signal is 25%, when N=3, that is, a DE -1 class 3 frequency multiplier, the output signal voltage is 2.9 times the DC power supply voltage V dd , and the frequency is 3 times the driving signal. 3 times the frequency. The calculation formula of its load resistance R L , the first inductance L 1 , the second inductance L 2 , the parallel compensation capacitor C, the parallel tuning capacitor C p and the parallel tuning inductance L p (the blocking capacitor C DC only needs to be large enough and does not need to be special calculation);
品质因数为QLC的LC并联调谐元件参数：Parameters of an LC parallel tuning element with a quality factor of Q LC :
其中,ω＝2πf。Among them, ω=2πf.
最后，利用计算结果设计DE类倍频器。Finally, the class DE frequency multiplier is designed using the calculation results.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变形，这些改进和变形也应视为本发明的保护范围。The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the technical principles of the present invention, several improvements and modifications can be made. These improvements and modifications It should also be regarded as the protection scope of the present invention.
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