CN107490913B - Array substrate, display panel and display device - Google Patents

Abstract

The invention discloses an array substrate, a display panel and a display device, comprising a display area and a non-display area surrounding the display area, the non-display area includes a plurality of first electrode leads and a plurality of second electrode leads, the non-display area of the array substrate The area includes: a substrate; a first conductive layer disposed on the surface of the substrate; a gate dielectric layer disposed on the side of the first conductive layer away from the substrate; a second conductive layer disposed on the side of the gate dielectric layer away from the substrate; The isolation layer on the side away from the substrate, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer; the third conductive layer disposed on the side of the isolation layer away from the substrate The first electrode lead is arranged on the first conductive layer or the second conductive layer, and the second electrode lead is arranged on the third conductive layer. Through reasonable wiring, the wiring layout of the array substrate can be greatly saved.

Description

Array substrate, display panel and display device

This application is a divisional application with an application date of April 1, 2015, an application number of 201510152790.X, and the title of the invention: array substrate, display panel and display device.

technical field

The present invention relates to the field of touch display technology, and more particularly, to an array substrate, a display panel and a display device including the array substrate.

Background technique

With the development of display technology, the liquid crystal display panel has been continuously improved, so that the liquid crystal display panel has the advantages of thin body, power saving, no radiation, etc., thus making the application of the liquid crystal display panel more and more widely. The array substrate is one of the important components in the liquid crystal display panel. It has the characteristics of high integration and complex wiring. It needs to integrate various devices in a limited wiring layout. One of the main research projects.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present invention provide an array substrate, a display panel and a display device. By arranging two electrode leads with overlapping applied signals on different conductive layers, the wiring layout of the array substrate is saved, so as to improve the performance of the array substrate. Utilization of the array substrate.

To achieve the above purpose, the technical solutions provided in the embodiments of the present invention are as follows:

An array substrate includes a display area and a non-display area surrounding the display area, the non-display area includes a plurality of first electrode leads and a plurality of second electrode leads, and the non-display area of the array substrate includes:

substrate;

a first conductive layer disposed on the surface of the substrate;

a gate dielectric layer disposed on the side of the first conductive layer away from the substrate;

a second conductive layer disposed on the side of the gate dielectric layer away from the substrate;

an isolation layer disposed on the side of the second conductive layer away from the substrate, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer The dielectric constant of ;

and, a third conductive layer disposed on the side of the isolation layer away from the substrate;

Wherein, the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

In addition, an embodiment of the present invention further provides a display panel including the above-mentioned array substrate.

Finally, an embodiment of the present invention also provides a display device, including the above-mentioned display panel.

Compared with the prior art, the technical solutions provided by the embodiments of the present invention have at least the following advantages:

Embodiments of the present invention provide an array substrate, a display panel, and a display device, including a display area and a non-display area surrounding the display area, the non-display area including a plurality of first electrode leads and a plurality of second electrode leads , the non-display area of the array substrate includes: a substrate; a first conductive layer disposed on the surface of the substrate; a gate dielectric layer disposed on the side of the first conductive layer away from the substrate; disposed on the gate dielectric a second conductive layer on the side away from the substrate; an isolation layer disposed on the side of the second conductive layer away from the substrate, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the The dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer; and a third conductive layer disposed on the side of the isolation layer away from the substrate; wherein the first electrode lead is disposed on the The first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

It can be seen from the above content that in the technical solution provided by the embodiments of the present invention, since the thickness of the isolation layer is greater than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer, the first electrode leads and the When the signal is applied to the second electrode lead at the same time, the interference phenomenon between the first electrode lead and the second electrode lead located in different conductive layers is improved, and then through reasonable wiring, the wiring layout of the array substrate can be greatly saved, thereby improving the utilization of the array substrate.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

FIG. 1 is a schematic structural diagram of an existing array substrate;

FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

Fig. 3a is a kind of sectional view along aa' direction in Fig. 2;

Fig. 3b is another sectional view along aa' direction in Fig. 2;

4a is a wiring diagram of a first electrode lead and a second electrode lead provided by an embodiment of the application;

Fig. 4b is another wiring diagram of the first electrode lead and the second electrode lead provided by the embodiment of the application;

FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 11 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 13 is a schematic diagram of a touch control structure of an array substrate according to an embodiment of the present application;

Fig. 14a is a sectional view along the direction of bb' in Fig. 13;

Fig. 14b is another sectional view taken along the direction bb' in Fig. 13 .

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As mentioned in the background art, because the array substrate has the characteristics of high integration and complex wiring, it is necessary to integrate various devices in a limited wiring layout. Therefore, an array substrate that saves wiring layout is one of the main research projects of researchers today. one.

Specifically, referring to FIG. 1 , which is a schematic structural diagram of an existing array substrate, wherein the array substrate includes a display area 101 and a non-display area 102 surrounding the display area, and the display area 101 includes a plurality of gate lines 101a and a plurality of data lines 101b; the non-display area 102 includes a gate driving circuit area 102a and a step area 102b; The data line leads 101b' located in the step area 102b are drawn out. Since the adjacent data line leads 101b' need to apply signals at the same time, in order to avoid mutual signal interference between the adjacent data line leads 101b', the adjacent data line leads 101b The distance between ' is increased, thereby increasing the wiring layout of the array substrate.

Based on this, the embodiments of the present application provide an array substrate, which can save the wiring layout of the array substrate and improve the performance of the array substrate by arranging two electrode leads with overlapping signal applied periods on different conductive layers, and performing reasonable wiring. utilization rate. Specifically, the array substrate provided by the embodiment of the present application will be described in detail with reference to FIG. 2 to FIG. 14b.

2 , FIG. 3 a and FIG. 3 b , FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application, FIG. 3 a is a cross-sectional view along the aa' direction in FIG. Another sectional view along the aa' direction in the middle, wherein the array substrate includes:

display area 10;

and a non-display area 20 surrounding the display area 10, the non-display area 20 includes a plurality of first electrode leads 20a and a plurality of second electrode leads 20b, and the first electrode leads 20a and the second electrode leads 20b are applied with signals during periods of Overlapping, the non-display area of the array substrate includes:

substrate 100;

the first conductive layer 200 disposed on the surface of the substrate 100;

the gate dielectric layer 300 disposed on the side of the first conductive layer 200 away from the substrate 100;

the second conductive layer 400 disposed on the side of the gate dielectric layer 300 away from the substrate 100;

the isolation layer 500 disposed on the side of the second conductive layer 400 away from the substrate 100, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer;

and, the third conductive layer 600 disposed on the side of the isolation layer 500 away from the substrate 100;

The first electrode lead 20 a is disposed on the first conductive layer 200 or the second conductive layer 400 , and the second electrode lead 20 b is disposed on the third conductive layer 600 .

That is, as shown in FIG. 3a, the first electrode lead 20a is disposed on the first conductive layer 200, and the second electrode lead 20b is disposed on the third conductive layer 600;

And, as shown in FIG. 3 b , the first electrode lead 20 a is disposed on the second conductive layer 400 , and the second electrode lead 20 b is disposed on the third conductive layer 600 .

It should be noted that the above-mentioned thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer, including three cases, namely, the first one is The thickness of the isolation layer is greater than that of the gate dielectric layer, and the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer; the second is that when the thickness of the gate dielectric layer and the isolation layer are the same, the dielectric constant of the isolation layer is less than The dielectric constant of the gate dielectric layer; and the third type is that when the dielectric constant of the isolation layer is the same as the dielectric constant of the gate dielectric layer, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer. The preferred thickness of the isolation layer in the embodiment of the present application is not less than 1.8 microns.

The first electrode leads and the second electrode leads provided in the embodiments of the present application can be arbitrarily set, and most preferably, along the light transmission direction of the array substrate, there is an overlapping area between the first electrode leads and the second electrode leads. Specifically, referring to FIG. 4a, a wiring diagram of a first electrode lead and a second electrode lead provided in an embodiment of the present application, wherein the first electrode lead 20a and the second electrode lead 20b have an overlapping area , and the extending directions of the first electrode lead 20a and the second electrode lead 20b are the same. That is, along the extending direction of any one electrode lead, one electrode lead can cover part of the other electrode lead; or, along the extending direction of any one electrode lead, one electrode lead can completely cover the other electrode lead;

In addition, referring to FIG. 4b, another wiring diagram of the first electrode lead and the second electrode lead provided by the embodiment of the present application, wherein the first electrode lead 20a and the second electrode lead 20b have an overlapping area. , and there is an included angle between the extending directions of the first electrode lead 20a and the second electrode lead 20b, wherein the included angle can be any degree such as 45 degrees, 60 degrees, etc., which is not limited.

It should be noted that the embodiment of the present application does not impose specific restrictions on the wiring structure between the first electrode lead and the second electrode lead, which needs to be designed according to the actual application, and then the wiring layout of the array substrate can be reduced through reasonable wiring. In addition, in order to maintain the consistency of the transmission signals of the first electrode lead and the second electrode lead, the resistances of the first electrode lead and the second electrode lead provided in the embodiments of the present application are the same.

Further, referring to FIG. 5 , which is a schematic structural diagram of another array substrate provided by the embodiment of the present application, wherein the non-display area 20 includes a gate driving circuit area 21 and a step area 22 , wherein,

The gate driving circuit area 21 includes a plurality of gate line leads 21a, and each gate line 21a lead is respectively connected to a gate line 10a of the array substrate;

And the step area 22 includes a plurality of data line leads 22a, and each data line lead 22a is respectively connected to a data line 10b of the array substrate;

The first electrode lead 20a and the second electrode lead 20b are both gate line leads or data line leads.

For the array substrate provided in this embodiment of the present application, the present application does not specifically limit the type thereof, wherein the transistor for the array substrate may be a bottom-gate transistor or a top-gate transistor, as shown in FIG. 6 and FIG. 7 . , the array substrate provided by the embodiment of the present application will be described in detail. It should be noted that both FIG. 6 and FIG. 7 are described by taking the array substrate provided in FIG. 3 a or FIG. 3 b as an example.

The transistors of the array substrate may be bottom-gate transistors. Referring to FIG. 6 , which is a schematic structural diagram of another array substrate provided in an embodiment of the present application, the first conductive layer 200 of the array substrate includes a gate G, The second conductive layer 400 includes source and drain electrodes (including source electrodes S and drain electrodes D), and the array substrate includes:

The semiconductor layer 700 disposed between the gate dielectric layer 300 and the second conductive layer 400, the semiconductor layer 700 includes an active region A, wherein the gate G, the source and drain (source S and drain D) and the active region A forms a thin film transistor.

Alternatively, the transistors of the array substrate may be top-gate transistors. Referring to FIG. 7 , which is a schematic structural diagram of another array substrate provided by the embodiment of the present application, the first conductive layer 200 of the array substrate includes a gate G, The second conductive layer 400 includes source and drain electrodes (including source electrodes S and drain electrodes D), and the array substrate includes:

A semiconductor layer 700 disposed between the substrate 100 and the first conductive layer 200, the semiconductor layer 700 includes an active region A; and a gate insulating layer 301 disposed between the semiconductor layer 700 and the first conductive layer 200, wherein the gate The electrode G, the source and drain electrodes (including the source electrode S and the drain electrode D) and the active region A form a thin film transistor.

In addition, the present application also does not specifically limit the positions of the common electrode and the pixel electrode of the array substrate. Specifically, the array substrate provided by the embodiments of the present application is described in detail with reference to FIGS. 8 to 12 .

Referring to FIG. 8 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein,

The array substrate includes: a substrate 100, a first conductive layer 200, a gate dielectric layer 300, and a second conductive layer 400;

the first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

a first electrode 802 disposed on the side of the first insulating layer 801 away from the substrate 100;

a second insulating layer 803 disposed on the side of the first electrode 802 away from the substrate 100;

a second electrode 804 disposed on the side of the second insulating layer 803 away from the substrate 100;

a third insulating layer 805 disposed on the side of the second electrode 804 away from the substrate 100;

and, the third conductive layer 600 disposed on the side of the third insulating layer 805 away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer, a second insulating layer and a third insulating layer.

Alternatively, referring to FIG. 9 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

the first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

a first electrode 802 disposed on the side of the first insulating layer 801 away from the substrate 100;

a second insulating layer 803 disposed on the side of the first electrode 802 away from the substrate 100;

the third conductive layer 600 disposed on the side of the second insulating layer 803 away from the substrate 100;

a third insulating layer 805 disposed on the side of the third conductive layer 600 away from the substrate 100;

and, the second electrode 804 disposed on the side of the third insulating layer 805 away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer and a second insulating layer.

Alternatively, referring to FIG. 10 , which is a schematic structural diagram of another array substrate provided in an embodiment of the present application, the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

the first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

the third conductive layer 600 disposed on the side of the first insulating layer 801 away from the substrate 100;

the second insulating layer 803 disposed on the side of the third conductive layer 600 away from the substrate 100;

the first electrode 802 disposed on the side of the second insulating layer 803 away from the substrate 100;

a third insulating layer 805 disposed on the side of the first electrode 802 away from the substrate 100;

and, the second electrode 804 disposed on the side of the third insulating layer 805 away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer.

Alternatively, referring to FIG. 11 , which is a schematic structural diagram of another array substrate provided in an embodiment of the present application, the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

the first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

a driving electrode 806 disposed on the side of the first insulating layer 801 away from the substrate 100, the driving electrode 806 includes a first electrode and a second electrode;

a second insulating layer 803 disposed on the side of the driving electrode 802 away from the substrate 100;

and, the third conductive layer 600 disposed on the side of the driving electrode 803 away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer and a second insulating layer.

Alternatively, referring to FIG. 12 , which is a schematic structural diagram of yet another array substrate provided in an embodiment of the present application, the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

the first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

the third conductive layer 600 disposed on the side of the first insulating layer 801 away from the substrate 100;

the second insulating layer 803 disposed on the side of the third conductive layer 600 away from the substrate 100;

And, the driving electrode 806 disposed on the side of the second insulating layer 803 away from the substrate 100, the driving electrode 806 includes a first electrode and a second electrode;

Wherein, the isolation layer includes a first insulating layer.

In the above content, in this embodiment of the present application, the first electrode may be a common electrode, and the second electrode may be a pixel electrode; or, the first electrode may be a pixel electrode, and the second electrode may be a common electrode.

Further, the array substrate provided by the embodiment of the present application may be a self-capacitance touch control array substrate. Referring to FIG. 13 , a schematic diagram of the touch control structure of the array substrate provided by the embodiment of the present application is shown, wherein the common electrode of the array substrate is is divided into a plurality of mutually independent touch electrodes 201;

a plurality of touch lines 202 disposed in the display area 10, each touch line 202 is electrically connected to a touch electrode 201 respectively;

The common voltage is applied to the touch electrodes 201 in the display stage, and the touch detection signals are applied to the touch electrodes in the touch stage;

The touch wires 202 are disposed on the third conductive layer.

Optionally, the non-display area 20 includes: a plurality of touch wire leads 203, each touch wire lead 203 is respectively connected to a touch wire 202;

14a, which is a sectional view in the direction of bb' in FIG. 13, wherein FIG. 14a is described based on FIG. 3a, when the first electrode lead 20a is disposed on the first conductive layer 200, the touch The wire leads 203 are disposed on the second conductive layer 400 , and the touch wire leads and the touch wires are electrically connected by vias;

Or, referring to FIG. 14b , which is another sectional view in the direction of bb′ in FIG. 13 , wherein FIG. 14b is described based on FIG. 3b , when the first electrode lead 20a is disposed on the second conductive layer 400 , the contact The control wire lead 203 is disposed on the first conductive layer 200 , and the touch wire lead 203 is electrically connected to the touch wire by means of a via hole. Wherein, the above-mentioned first electrode leads, second electrode leads and touch electrode leads can all overlap, which saves the area occupied by the leads and improves the utilization rate of the array substrate.

In addition, an embodiment of the present application further provides a display panel, including the array substrate provided by any one of the foregoing embodiments.

Finally, the embodiments of the present application further provide a display device, including the display panel provided by the above embodiments.

Embodiments of the present application provide an array substrate, a display panel, and a display device, including a display area and a non-display area surrounding the display area, the non-display area including a plurality of first electrode leads and a plurality of second electrode leads , and the periods during which the signals are applied to the first electrode leads and the second electrode leads overlap, and the non-display area of the array substrate includes: a substrate; a first conductive layer disposed on the surface of the substrate; A gate dielectric layer on the side of the first conductive layer facing away from the substrate; a second conductive layer on the side of the gate dielectric layer facing away from the substrate; isolation on the side of the second conductive layer facing away from the substrate layer, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer; The third conductive layer on one side of the substrate; wherein, the first electrode lead is arranged on the first conductive layer or the second conductive layer, and the second electrode lead is arranged on the third conductive layer.

It can be seen from the above content that, in the technical solutions provided by the embodiments of the present application, since the thickness of the isolation layer is greater than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer, the first electrode leads and the When the signal is applied to the second electrode lead at the same time, the interference phenomenon between the first electrode lead and the second electrode lead located in different conductive layers is improved, and then through reasonable wiring, the wiring layout of the array substrate can be greatly saved, thereby improving the utilization of the array substrate.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (16)

1. An array substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a plurality of first electrode leads and a plurality of second electrode leads, and the array substrate is characterized by further comprising:

a substrate;

the first conducting layer is arranged on the surface of the substrate and comprises a grid electrode;

a semiconductor layer disposed between the substrate and the first conductive layer, the semiconductor layer including an active region, a gate insulating layer disposed between the semiconductor layer and the first conductive layer;

the gate dielectric layer is arranged on one side, away from the substrate, of the first conducting layer;

the second conducting layer is arranged on one side, away from the substrate, of the gate dielectric layer and comprises a source drain electrode, wherein the gate electrode, the source drain electrode and the active region form a thin film transistor;

the isolation layer is arranged on one side, away from the substrate, of the second conducting layer, the thickness of the isolation layer is larger than that of the gate dielectric layer, the thickness of the isolation layer is not smaller than 1.8 microns, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer;

the third conducting layer is arranged on one side, away from the substrate, of the isolation layer;

wherein the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

2. The array substrate of claim 1, wherein the first electrode lead and the second electrode lead have an overlapping region therebetween along a light transmission direction of the array substrate.

3. The array substrate of claim 2, wherein the first electrode lead and the second electrode lead extend in the same direction.

4. The array substrate of claim 2, wherein the first electrode lead and the second electrode lead extend at an angle therebetween.

5. The array substrate of claim 1, wherein the first and second electrode leads have the same resistance.

6. The array substrate of claim 1, wherein the non-display region comprises a gate driving circuit region and a step region, wherein,

the grid driving circuit area comprises a plurality of grid line leads, and each grid line lead is connected with one grid line of the array substrate;

the step area comprises a plurality of data line leads, and each data line lead is connected with a data line of the array substrate;

the first electrode lead and the second electrode lead are both gate line leads or data line leads.

7. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the first insulating layer is arranged on one side, away from the substrate, of the second conducting layer;

the first electrode is arranged on one side, away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, away from the substrate, of the first electrode;

the second electrode is arranged on one side, away from the substrate, of the second insulating layer;

the third insulating layer is arranged on one side, away from the substrate, of the second electrode;

the third conducting layer is arranged on one side, away from the substrate, of the third insulating layer;

wherein the isolation layer includes the first, second, and third insulating layers.

8. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the first insulating layer is arranged on one side, away from the substrate, of the second conducting layer;

the first electrode is arranged on one side, away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, away from the substrate, of the first electrode;

the third conducting layer is arranged on one side, away from the substrate, of the second insulating layer;

the third insulating layer is arranged on one side, away from the substrate, of the third conducting layer;

the second electrode is arranged on one side, away from the substrate, of the third insulating layer;

wherein the isolation layer includes the first and second insulating layers.

9. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the first insulating layer is arranged on one side, away from the substrate, of the second conducting layer;

the third conducting layer is arranged on one side, away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, away from the substrate, of the third conducting layer;

the first electrode is arranged on one side, away from the substrate, of the second insulating layer;

the third insulating layer is arranged on one side, away from the substrate, of the first electrode;

the second electrode is arranged on one side, away from the substrate, of the third insulating layer;

wherein the isolation layer comprises the first insulating layer.

10. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the first insulating layer is arranged on one side, away from the substrate, of the second conducting layer;

the driving electrode is arranged on one side, away from the substrate, of the first insulating layer and comprises a first electrode and a second electrode;

the second insulating layer is arranged on one side, away from the substrate, of the driving electrode;

the third conducting layer is arranged on one side, away from the substrate, of the driving electrode;

wherein the isolation layer includes the first and second insulating layers.

11. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the first insulating layer is arranged on one side, away from the substrate, of the second conducting layer;

the third conducting layer is arranged on one side, away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, away from the substrate, of the third conducting layer;

the driving electrode is arranged on one side, away from the substrate, of the second insulating layer and comprises a first electrode and a second electrode;

wherein the isolation layer comprises the first insulating layer.

12. The array substrate of any one of claims 7 to 11, wherein the first electrode is a common electrode and the second electrode is a pixel electrode;

or, the first electrode is a pixel electrode, and the second electrode is a common electrode.

13. The array substrate of claim 12, wherein the common electrode is divided into a plurality of independent touch electrodes;

the touch control lines are arranged in the display area, and each touch control line is electrically connected with one touch control electrode;

the touch electrode is applied with a common voltage in a display stage, and the touch electrode is applied with a touch detection signal in a touch stage;

wherein the touch line is disposed on the third conductive layer.

14. The array substrate of claim 13, wherein the non-display area comprises: the touch control line leads are connected with one touch control line respectively;

when the first electrode lead is arranged on the first conductive layer, the touch control line lead is arranged on the second conductive layer, and the touch control line lead is electrically connected with the touch control line in a via hole mode;

or when the first electrode lead is arranged on the second conductive layer, the touch line lead is arranged on the first conductive layer, and the touch line lead is electrically connected with the touch line in a via hole mode.

15. A display panel comprising the array substrate according to any one of claims 1 to 14.

16. A display device characterized by comprising the display panel according to claim 15.

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