CN104865756B - Array substrate, display panel and display device - Google Patents

Abstract

The invention discloses an array substrate, a display panel and a display device, comprising a display area and a non-display area surrounding the display area, the non-display area includes a plurality of first electrode leads and a plurality of second electrode leads, and the non-display area of the array substrate The area includes: the substrate; the first conductive layer arranged on the surface of the substrate; the gate dielectric layer arranged on the side of the first conductive layer away from the substrate; the second conductive layer arranged on the side of the gate dielectric layer away from the substrate; The isolation layer on the side away from the substrate, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer; the third conductive layer arranged on the side of the isolation layer away from the substrate layer; the first electrode leads are arranged on the first conductive layer or the second conductive layer, and the second electrode leads are arranged on the third conductive layer, through rational wiring, the wiring layout of the array substrate is greatly saved.

Description

Array substrate, display panel and display device

technical field

The present invention relates to the field of touch display technology, and more specifically, relates to an array substrate, a display panel and a display device including the array substrate.

Background technique

With the development of the display technology, the liquid crystal display panel has been continuously improved, so that the liquid crystal display panel has the advantages of thin body, power saving, and no radiation, so that the application of the liquid crystal display panel is becoming wider and wider. The array substrate is one of the important components in the liquid crystal display panel. It has the characteristics of high integration and complicated wiring. It needs to integrate various devices in a limited wiring layout. One of the main research projects.

Contents of the invention

In view of this, an embodiment of the present invention provides an array substrate, a display panel, and a display device. By arranging two overlapping electrode leads for applying signals on different conductive layers, the wiring layout of the array substrate is saved, so as to improve Utilization of the array substrate.

In order to achieve the above object, the technical solutions provided by the embodiments of the present invention are as follows:

An array substrate, including a display area and a non-display area surrounding the display area, the non-display area includes a plurality of first electrode leads and a plurality of second electrode leads, and the non-display area of the array substrate includes:

Substrate;

a first conductive layer disposed on the surface of the substrate;

a gate dielectric layer disposed on a side of the first conductive layer away from the substrate;

a second conductive layer disposed on a side of the gate dielectric layer away from the substrate;

An isolation layer disposed on the side of the second conductive layer away from the substrate, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer The dielectric constant;

And, a third conductive layer disposed on a side of the isolation layer away from the substrate;

Wherein, the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

In addition, an embodiment of the present invention also provides a display panel, including the above-mentioned array substrate.

Finally, an embodiment of the present invention also provides a display device, including the above-mentioned display panel.

Compared with the prior art, the technical solutions provided by the embodiments of the present invention have at least the following advantages:

An embodiment of the present invention provides an array substrate, a display panel, and a display device, including a display area and a non-display area surrounding the display area, and the non-display area includes a plurality of first electrode leads and a plurality of second electrode leads , the non-display area of the array substrate includes: a substrate; a first conductive layer arranged on the surface of the substrate; a gate dielectric layer arranged on the side of the first conductive layer away from the substrate; layer away from the second conductive layer on the side of the substrate; an isolation layer disposed on the side of the second conductive layer away from the substrate, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the The dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer; and the third conductive layer is disposed on the side of the isolation layer away from the substrate; wherein, the first electrode lead is disposed on the The first conductive layer or the second conductive layer, and the second electrode leads are arranged on the third conductive layer.

It can be seen from the above that, in the technical solution provided by the embodiments of the present invention, since the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer, the first electrode lead and When the second electrode leads are applied with signals at the same time, the interference phenomenon between the first electrode leads and the second electrode leads on different conductive layers is improved, and then through reasonable wiring, the wiring layout of the array substrate can be greatly saved, thereby improving The utilization rate of the array substrate is improved.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings on the premise of not paying creative efforts.

FIG. 1 is a schematic structural diagram of an existing array substrate;

FIG. 2 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

Fig. 3 a is a kind of sectional view along aa ' direction in Fig. 2;

Fig. 3b is another kind of sectional view along aa' direction in Fig. 2;

Fig. 4a is a wiring diagram of a first electrode lead and a second electrode lead provided in an embodiment of the present application;

Fig. 4b is another wiring diagram of the first electrode lead and the second electrode lead provided by the embodiment of the present application;

FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another array substrate provided in the embodiment of the present application;

FIG. 11 is a schematic structural diagram of another array substrate provided in the embodiment of the present application;

FIG. 12 is a schematic structural diagram of another array substrate provided in the embodiment of the present application;

FIG. 13 is a schematic diagram of a touch control structure of an array substrate provided by an embodiment of the present application;

Fig. 14a is a kind of sectional view along bb ' direction in Fig. 13;

Fig. 14b is another cross-sectional view along the bb' direction in Fig. 13 .

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As mentioned in the background technology, because the array substrate has the characteristics of high integration and complicated wiring, various devices need to be integrated in a limited wiring layout. Therefore, an array substrate that saves wiring layout is one of the main research projects of researchers today. one.

Specifically, as shown in FIG. 1 , it is a schematic structural diagram of an existing array substrate, wherein the array substrate includes a display area 101 and a non-display area 102 surrounding the display area, and the display area 101 includes a plurality of gate lines 101a and a plurality of data lines 101b; the non-display area 102 includes a gate drive circuit area 102a and a step area 102b; Leading out through the data line leads 101b' located in the stepped area 102b, since adjacent data line leads 101b' need to apply signals at the same time, in order to avoid signal interference between adjacent data line leads 101b', the adjacent data line leads 101b The distance between 'is enlarged, thereby increasing the wiring layout of the array substrate.

Based on this, an embodiment of the present application provides an array substrate, by arranging two electrode leads with overlapping signal application periods on different conductive layers, and through rational wiring, the wiring layout of the array substrate can be saved, and the array substrate can be improved. utilization rate. Specifically referring to FIG. 2 to FIG. 14 b , the array substrate provided by the embodiment of the present application will be described in detail.

In combination with Figure 2, Figure 3a and Figure 3b, Figure 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application, Figure 3a is a cut-away view along the aa' direction in Figure 2, and Figure 3b is a cross-sectional view of Figure 2 Another sectional view along the aa' direction in , wherein the array substrate includes:

display area 10;

and a non-display area 20 surrounding the display area 10, the non-display area 20 includes a plurality of first electrode leads 20a and a plurality of second electrode leads 20b, and the period during which signals are applied to the first electrode leads 20a and the second electrode leads 20b is Overlapping, the non-display area of the array substrate includes:

Substrate 100;

a first conductive layer 200 disposed on the surface of the substrate 100;

The gate dielectric layer 300 disposed on the side of the first conductive layer 200 away from the substrate 100;

The second conductive layer 400 disposed on the side of the gate dielectric layer 300 away from the substrate 100;

The isolation layer 500 disposed on the side of the second conductive layer 400 away from the substrate 100, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer;

And, the third conductive layer 600 disposed on the side of the isolation layer 500 away from the substrate 100;

Wherein, the first electrode lead 20 a is disposed on the first conductive layer 200 or the second conductive layer 400 , and the second electrode lead 20 b is disposed on the third conductive layer 600 .

That is, referring to FIG. 3a, the first electrode lead 20a is disposed on the first conductive layer 200, and the second electrode lead 20b is disposed on the third conductive layer 600;

And, referring to FIG. 3 b , the first electrode lead 20 a is disposed on the second conductive layer 400 , and the second electrode lead 20 b is disposed on the third conductive layer 600 .

It should be noted that the above mentioned isolation layer has a thickness greater than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer, including three situations, that is, the first one is The thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer; the second is that when the thickness of the gate dielectric layer and the isolation layer are the same, the dielectric constant of the isolation layer is less than The dielectric constant of the gate dielectric layer; and, the third type is that when the dielectric constant of the isolation layer is the same as that of the gate dielectric layer, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer. The preferred thickness of the isolation layer in the embodiment of the present application is not less than 1.8 microns.

The first electrode leads and the second electrode leads provided in the embodiment of the present application can be arranged arbitrarily, and most preferably, along the light transmission direction of the array substrate, there is an overlapping area between the first electrode leads and the second electrode leads. Specifically, referring to FIG. 4a, it is a wiring diagram of a first electrode lead and a second electrode lead provided by an embodiment of the present application, wherein there is an overlapping area between the first electrode lead 20a and the second electrode lead 20b , and the extending direction of the first electrode lead 20a and the second electrode lead 20b are the same. That is, along the extension direction of any electrode lead, one electrode lead can cover part of the other electrode lead; or, along the extension direction of any electrode lead, one electrode lead can completely cover the other electrode lead;

In addition, as shown in FIG. 4b, another wiring diagram of the first electrode lead and the second electrode lead provided by the embodiment of the present application, wherein there is an overlapping area between the first electrode lead 20a and the second electrode lead 20b , and there is an included angle between the extension directions of the first electrode lead 20a and the second electrode lead 20b, wherein the included angle can be any number of degrees such as 45 degrees, 60 degrees, etc., without limitation.

It should be noted that the embodiment of the present application does not specifically limit the wiring structure between the first electrode lead and the second electrode lead, and it needs to be designed according to the actual application, and then the wiring layout of the array substrate can be reduced through reasonable wiring. In addition, in order to maintain the consistency of signal transmission between the first electrode lead and the second electrode lead, the resistances of the first electrode lead and the second electrode lead provided in the embodiment of the present application are the same.

Further, referring to FIG. 5 , which is a schematic structural diagram of another array substrate provided by the embodiment of the present application, wherein the non-display area 20 includes a gate drive circuit area 21 and a step area 22, wherein,

The gate drive circuit area 21 includes a plurality of gate line leads 21a, and each gate line 21a lead is respectively connected to a gate line 10a of the array substrate;

And the stepped area 22 includes a plurality of data line leads 22a, and each data line lead 22a is respectively connected to a data line 10b of the array substrate;

Wherein, the first electrode leads 20 a and the second electrode leads 20 b are gate line leads or data line leads.

For the array substrate provided in the embodiment of the present application, the present application does not specifically limit its type, wherein the transistors on the array substrate can be bottom-gate transistors or top-gate transistors, as shown in Figure 6 and Figure 7 , the array substrate provided by the embodiment of the present application will be described in detail. It should be noted that both FIG. 6 and FIG. 7 take the array substrate provided based on FIG. 3 a or FIG. 3 b as an example for illustration.

Wherein, the transistors of the array substrate may be bottom-gate transistors, as shown in FIG. 6 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein the first conductive layer 200 of the array substrate includes a gate G, The second conductive layer 400 includes source and drain (including source S and drain D), and the array substrate includes:

The semiconductor layer 700 disposed between the gate dielectric layer 300 and the second conductive layer 400, the semiconductor layer 700 includes an active region A, wherein the gate G, source and drain (source S and drain D) and the active region A forms a thin film transistor.

Alternatively, the transistors of the array substrate may be top-gate transistors, as shown in FIG. 7 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein the first conductive layer 200 of the array substrate includes a gate G, The second conductive layer 400 includes source and drain (including source S and drain D), and the array substrate includes:

A semiconductor layer 700 disposed between the substrate 100 and the first conductive layer 200, the semiconductor layer 700 includes an active region A; and a gate insulating layer 301 disposed between the semiconductor layer 700 and the first conductive layer 200, wherein the gate G, source and drain (including source S and drain D) and active region A form a thin film transistor.

In addition, the present application also does not specifically limit the positions of the common electrode and the pixel electrode of the array substrate. Specifically, referring to FIG. 8 to FIG. 12 , the array substrate provided by the embodiment of the present application will be described in detail.

Referring to FIG. 8 , it is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein,

The array substrate includes: a substrate 100, a first conductive layer 200, a gate dielectric layer 300, and a second conductive layer 400;

The first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

a first electrode 802 disposed on a side of the first insulating layer 801 away from the substrate 100;

a second insulating layer 803 disposed on the side of the first electrode 802 away from the substrate 100;

a second electrode 804 disposed on a side of the second insulating layer 803 away from the substrate 100;

a third insulating layer 805 disposed on the side of the second electrode 804 away from the substrate 100;

And, the third conductive layer 600 disposed on the side of the third insulating layer 805 facing away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer, a second insulating layer and a third insulating layer.

Alternatively, refer to FIG. 9 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

The first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

a first electrode 802 disposed on a side of the first insulating layer 801 away from the substrate 100;

a second insulating layer 803 disposed on the side of the first electrode 802 away from the substrate 100;

The third conductive layer 600 disposed on the side of the second insulating layer 803 away from the substrate 100;

The third insulating layer 805 disposed on the side of the third conductive layer 600 away from the substrate 100;

And, the second electrode 804 disposed on the side of the third insulating layer 805 facing away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer and a second insulating layer.

Alternatively, refer to FIG. 10 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

The first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

The third conductive layer 600 disposed on the side of the first insulating layer 801 away from the substrate 100;

The second insulating layer 803 disposed on the side of the third conductive layer 600 away from the substrate 100;

The first electrode 802 disposed on the side of the second insulating layer 803 away from the substrate 100;

a third insulating layer 805 disposed on the side of the first electrode 802 away from the substrate 100;

And, the second electrode 804 disposed on the side of the third insulating layer 805 facing away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer.

Alternatively, refer to FIG. 11 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

The first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

The driving electrode 806 disposed on the side of the first insulating layer 801 away from the substrate 100, the driving electrode 806 includes a first electrode and a second electrode;

a second insulating layer 803 disposed on the side of the driving electrode 802 away from the substrate 100;

And, the third conductive layer 600 disposed on the side of the driving electrode 803 away from the substrate 100;

Wherein, the isolation layer includes a first insulating layer and a second insulating layer.

Alternatively, refer to FIG. 12 , which is a schematic structural diagram of another array substrate provided by an embodiment of the present application, wherein the array substrate includes: a substrate 100 , a first conductive layer 200 , a gate dielectric layer 300 , and a second conductive layer 400 ;

The first insulating layer 801 disposed on the side of the second conductive layer 400 away from the substrate 100;

The third conductive layer 600 disposed on the side of the first insulating layer 801 away from the substrate 100;

The second insulating layer 803 disposed on the side of the third conductive layer 600 away from the substrate 100;

And, the driving electrode 806 disposed on the side of the second insulating layer 803 away from the substrate 100, the driving electrode 806 includes a first electrode and a second electrode;

Wherein, the isolation layer includes a first insulating layer.

In the above, in the embodiment of the present application, the first electrode may be a common electrode, and the second electrode may be a pixel electrode; or, the first electrode may be a pixel electrode, and the second electrode may be a common electrode.

Further, the array substrate provided by the embodiment of the present application may be a self-capacitance touch array substrate. Referring to FIG. Divided into multiple independent touch electrodes 201;

A plurality of touch lines 202 arranged in the display area 10, each touch line 202 is electrically connected to a touch electrode 201;

Wherein, the common voltage is applied to the touch electrode 201 in the display stage, and the touch detection signal is applied to the touch electrode in the touch stage;

Wherein, the touch wire 202 is disposed on the third conductive layer.

Optionally, located in the non-display area 20, including: a plurality of touch wire leads 203, each touch wire lead 203 is respectively connected to a touch wire 202;

Wherein, referring to FIG. 14a, it is a cross-sectional view along the bb' direction in FIG. 13, wherein, FIG. 14a is described based on FIG. The wire leads 203 are disposed on the second conductive layer 400, and the touch wire leads and the touch wires are electrically connected through via holes;

Or, referring to FIG. 14b, which is another cross-sectional view along the bb' direction in FIG. 13, wherein FIG. 14b is described based on FIG. The control wire leads 203 are disposed on the first conductive layer 200 , and the touch wire leads 203 are electrically connected to the touch wires through via holes. Wherein, the above-mentioned first electrode leads, second electrode leads and touch electrode leads can all overlap, which saves the area occupied by the leads and improves the utilization rate of the array substrate.

In addition, an embodiment of the present application further provides a display panel, including the array substrate provided in any one of the above embodiments.

Finally, an embodiment of the present application further provides a display device, including the display panel provided in the foregoing embodiment.

Embodiments of the present application provide an array substrate, a display panel, and a display device, including a display area and a non-display area surrounding the display area, and the non-display area includes a plurality of first electrode leads and a plurality of second electrode leads , and the periods during which signals are applied to the first electrode leads and the second electrode leads overlap, the non-display area of the array substrate includes: a substrate; a first conductive layer disposed on the surface of the substrate; disposed on the The gate dielectric layer on the side of the first conductive layer away from the substrate; the second conductive layer arranged on the side of the gate dielectric layer away from the substrate; the isolation layer arranged on the side of the second conductive layer away from the substrate layer, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer; and, the isolation layer is arranged away from the A third conductive layer on one side of the substrate; wherein, the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

It can be seen from the above that, in the technical solution provided by the embodiment of the present application, since the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than the dielectric constant of the gate dielectric layer, the first electrode lead and When the second electrode leads are applied with signals at the same time, the interference phenomenon between the first electrode leads and the second electrode leads on different conductive layers is improved, and then through reasonable wiring, the wiring layout of the array substrate can be greatly saved, thereby improving The utilization rate of the array substrate is improved.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (19)

1. An array substrate, comprising a display area and a non-display area surrounding the display area, the non-display area includes a plurality of first electrode leads and a plurality of second electrode leads, characterized in that the array substrate Non-display areas include: Substrate; a first conductive layer disposed on the surface of the substrate; a gate dielectric layer disposed on a side of the first conductive layer away from the substrate; a second conductive layer disposed on a side of the gate dielectric layer away from the substrate; An isolation layer disposed on the side of the second conductive layer away from the substrate, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer The dielectric constant; And, a third conductive layer disposed on a side of the isolation layer away from the substrate; Wherein, the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer. 2 . The array substrate according to claim 1 , wherein there is an overlapping area between the first electrode leads and the second electrode leads along the light transmission direction of the array substrate. 3. The array substrate according to claim 2, wherein the extending direction of the first electrode lead and the second electrode lead are the same. 4 . The array substrate according to claim 2 , wherein there is an included angle between the extending directions of the first electrode lead and the second electrode lead. 5. The array substrate according to claim 1, wherein the resistance of the first electrode lead and the second electrode lead are the same. 6. The array substrate according to claim 1, wherein the non-display area comprises a gate drive circuit area and a step area, wherein, The area of the gate driving circuit includes a plurality of gate line leads, and each gate line lead is respectively connected to a gate line of the array substrate; And the stepped area includes a plurality of data line leads, each data line lead is respectively connected to a data line of the array substrate; Wherein, the first electrode leads and the second electrode leads are both gate line leads or data line leads. 7. The array substrate according to claim 1, wherein the thickness of the isolation layer is not less than 1.8 microns. 8. The array substrate according to claim 1, wherein the first conductive layer comprises a gate, the second conductive layer comprises a source and drain, and the array substrate comprises: A semiconductor layer disposed between the gate dielectric layer and the second conductive layer, the semiconductor layer includes an active region, wherein the gate, source and drain and the active region form a thin film transistor. 9. The array substrate according to claim 1, wherein the first conductive layer comprises a gate, the second conductive layer comprises a source and drain, and the array substrate comprises: a semiconductor layer disposed between the substrate and the first conductive layer, the semiconductor layer including an active region; and a gate insulating layer disposed between the semiconductor layer and the first conductive layer. 10. The array substrate according to claim 1, wherein the array substrate comprises: the substrate, a first conductive layer, a gate dielectric layer, and a second conductive layer; a first insulating layer disposed on a side of the second conductive layer away from the substrate; a first electrode disposed on a side of the first insulating layer away from the substrate; a second insulating layer disposed on a side of the first electrode away from the substrate; a second electrode disposed on a side of the second insulating layer away from the substrate; a third insulating layer disposed on a side of the second electrode away from the substrate; And, the third conductive layer is disposed on the side of the third insulating layer away from the substrate; Wherein, the isolation layer includes the first insulating layer, the second insulating layer and the third insulating layer. 11. The array substrate according to claim 1, wherein the array substrate comprises: the substrate, a first conductive layer, a gate dielectric layer, and a second conductive layer; a first insulating layer disposed on a side of the second conductive layer away from the substrate; a first electrode disposed on a side of the first insulating layer away from the substrate; a second insulating layer disposed on a side of the first electrode away from the substrate; the third conductive layer disposed on the side of the second insulating layer facing away from the substrate; a third insulating layer disposed on a side of the third conductive layer away from the substrate; And, a second electrode disposed on a side of the third insulating layer away from the substrate; Wherein, the isolation layer includes the first insulating layer and the second insulating layer. 12. The array substrate according to claim 1, wherein the array substrate comprises: the substrate, a first conductive layer, a gate dielectric layer, and a second conductive layer; a first insulating layer disposed on a side of the second conductive layer away from the substrate; a third conductive layer disposed on a side of the first insulating layer away from the substrate; a second insulating layer disposed on a side of the third conductive layer away from the substrate; a first electrode disposed on a side of the second insulating layer away from the substrate; a third insulating layer disposed on a side of the first electrode away from the substrate; And, a second electrode disposed on a side of the third insulating layer away from the substrate; Wherein, the isolation layer includes the first insulating layer. 13. The array substrate according to claim 1, wherein the array substrate comprises: the substrate, a first conductive layer, a gate dielectric layer, and a second conductive layer; a first insulating layer disposed on a side of the second conductive layer away from the substrate; a driving electrode disposed on a side of the first insulating layer away from the substrate, the driving electrode comprising a first electrode and a second electrode; a second insulating layer disposed on a side of the driving electrode away from the substrate; And, the third conductive layer is disposed on the side of the driving electrode away from the substrate; Wherein, the isolation layer includes the first insulating layer and the second insulating layer. 14. The array substrate according to claim 1, wherein the array substrate comprises: the substrate, a first conductive layer, a gate dielectric layer, and a second conductive layer; a first insulating layer disposed on a side of the second conductive layer away from the substrate; the third conductive layer disposed on the side of the first insulating layer facing away from the substrate; a second insulating layer disposed on a side of the third conductive layer away from the substrate; And, a driving electrode disposed on a side of the second insulating layer away from the substrate, the driving electrode includes a first electrode and a second electrode; Wherein, the isolation layer includes the first insulating layer. 15. The array substrate according to any one of claims 10-14, wherein the first electrode is a common electrode, and the second electrode is a pixel electrode; Alternatively, the first electrode is a pixel electrode, and the second electrode is a common electrode. 16. The array substrate according to claim 15, wherein the common electrode is divided into a plurality of mutually independent touch electrodes; a plurality of touch lines arranged in the display area, each touch line is electrically connected to a touch electrode; Wherein, the touch electrodes are applied with a common voltage during the display phase, and the touch detection signals are applied with the touch electrodes during the touch phase; Wherein, the touch wire is disposed on the third conductive layer. 17. The array substrate according to claim 16, wherein the non-display area comprises: a plurality of touch wire leads, each of which is connected to a touch wire; Wherein, when the first electrode leads are arranged on the first conductive layer, the touch wire leads are arranged on the second conductive layer, and the touch wire leads and the touch wires use via holes way of electrical connection; Alternatively, when the first electrode leads are disposed on the second conductive layer, the touch wire leads are disposed on the first conductive layer, and the touch wire leads and the touch wires use via holes way of electrical connection. 18. A display panel, comprising the array substrate according to any one of claims 1-17. 19. A display device, comprising the display panel according to claim 18.