CN107424969B - Semiconductor packaging device and method of manufacturing the same - Google Patents

Abstract

According to one or more embodiments of the present invention, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer and a conductive contact. The redistribution layer has a first surface and a second surface opposite to the first surface. The conductive pad is located on the first surface of the redistribution layer. The dielectric layer is located on the first surface of the redistribution layer to cover a first portion of the conductive pad and expose a second portion of the conductive pad. The silicon layer is located on the dielectric layer. The silicon layer has a groove to expose the second portion of the conductive pad. The conductive contact is placed on the silicon layer and extends into the groove of the silicon layer.

Description

Semiconductor packaging device and method of manufacturing the same

technical field

The present invention relates to a semiconductor packaging device and a method of manufacturing the same, and more particularly, to a semiconductor packaging device having a stack structure and a method of manufacturing the same.

Background technique

In conventional three-dimensional semiconductor packaging, one or more semiconductor devices (eg, processing units or memories) can be attached to a substrate (ball grid array (BGA) substrate) via an interposer, where the interposer The through-silicon vias (TSVs) provide electrical connection between the semiconductor device and the substrate. However, the use of through silicon via interposers increases the overall thickness or height of the semiconductor package.

SUMMARY OF THE INVENTION

This case claims priority to US Provisional Patent Application No. 62/326,678, filed on April 22, 2016, the contents of which are incorporated by reference as the disclosure of this case. This case is a continuation-in-part of US patent application (No. 15/404,093, filed on January 11, 2017) and claims the priority of said US patent application, the contents of which are incorporated by reference as disclosure of the case.

According to an embodiment of the present invention, the interposer includes: a redistribution layer, a conductive pad, and a dielectric layer. The redistribution layer has a first surface and a second surface opposite the first surface. The conductive pads are on the first surface of the redistribution layer. The conductive pad includes a first portion and a second portion. A dielectric layer is on the first surface of the redistribution layer to cover the first portion of the conductive pad and expose the second portion of the conductive pad. The surface of the second portion of the conductive pad is substantially coplanar with the surface of the dielectric layer.

According to an embodiment of the present invention, a semiconductor package includes a redistribution layer, conductive pads, a dielectric layer, a silicon layer, and conductive contacts. The redistribution layer has a first surface and a second surface opposite the first surface. The conductive pads are on the first surface of the redistribution layer. A dielectric layer is on the first surface of the redistribution layer to cover the first portion of the conductive pad and expose the second portion of the conductive pad. The silicon layer is on the dielectric layer. The silicon layer has recesses to expose the second portion of the conductive pads. Conductive contacts are placed on the silicon layer and extend into the recesses in the silicon layer.

According to an embodiment of the present invention, a method of fabricating a semiconductor package includes: providing a silicon carrier; placing a dielectric layer on the silicon carrier, the dielectric layer including conductive pads; placing a redistribution layer on the dielectric layer to electrically connect to the conductive pads; connect the die to the redistribution layer; remove a portion of the silicon carrier and dielectric layer to expose the conductive pads; and place conductive contacts to contact the conductive pads.

Description of drawings

1A illustrates a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

1B illustrates an enlarged view of a portion of the semiconductor package of FIG. 1A in accordance with an embodiment of the present invention.

1C illustrates an enlarged view of a portion of the semiconductor package of FIG. 1A in accordance with an embodiment of the present invention.

2A, 2B, 2C, 2D, and 2E illustrate a method of fabricating a semiconductor package according to an embodiment of the present invention.

3A, 3B, and 3C illustrate a method of fabricating a semiconductor package according to an embodiment of the present invention.

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or similar components. The present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Detailed ways

1A illustrates a cross-sectional view of a semiconductor package 100 in accordance with some embodiments of the present invention. The semiconductor package device 100 includes a semiconductor package device 1 , an interposer 10 and a substrate 13 .

Depending on the particular application, the substrate 13 may be a flexible substrate or a rigid substrate. In some embodiments, the substrate 13 includes a plurality of conductive wirings. In some embodiments, an external contact layer may also be formed or placed on the substrate 13 . In some embodiments, the external contact layer includes a ball grid array (BGA). In other embodiments, the external contact layer includes, but is not limited to, an array such as a land grid array (LGA) or an array of pins (PGA). In some embodiments, the external contact layer includes solder balls 13b, which may or may not include leads (eg, include alloys such as gold and tin solder or alloys of silver and tin solder).

The semiconductor package device 1 is placed over the substrate 13 . The semiconductor package device 1 includes electronic components 11 a and 11 b and a package body 12 . Each electronic component 11a, 11b includes a plurality of semiconductor devices, such as, but not limited to, transistors, capacitors, and resistors, which are interconnected by die interconnect structures to form functional circuits to form integrated circuits. As can be appreciated by those skilled in the art, a semiconductor die includes an active portion having integrated circuits and interconnect structures. The electronic devices 11a, 11b may be any suitable integrated circuit device, which according to various embodiments may include, but are not limited to, microprocessors (single core or multi-core), memory devices, chipsets, display devices or application specific integrated circuits.

The package 12 is positioned to cover or encase the electronic components 11a, 11b. In some embodiments, the package body 12 includes epoxy with a filler dispersed therein, a molding compound (eg, epoxy molding compound or other molding compound), polyimide, phenolic compound material or material, material with polysiloxane, or a combination thereof.

The interposer 10 is placed between the semiconductor package device 1 and the substrate 13 to provide electrical connection between the semiconductor package device 1 and the substrate 13 . The electronic components 11a, 11b are electrically connected to conductive contacts (eg, micropads) 10b on the interposer 10 . The interposer 10 is electrically connected to the substrate 13 through conductive contacts (eg, controlled collapse chip connection, C4) 10b2. In some embodiments, the conductive contacts 10b1 , 10b2 may be covered or encapsulated by an underfill.

FIG. 1B illustrates an enlarged view of the portion of the semiconductor package 100 of FIG. 1A surrounded by box A in accordance with an embodiment of the present invention. The interposer 10 includes a redistribution layer (RDL), dielectric layers 10d, 10n, a silicon layer 10s, a passivation layer 10g, and a conductive pad 10p.

In some embodiments, the redistribution layer 10r includes stacked interlayer dielectrics (ILD) 10r1, 10r2 and conductive layers 10m1, 10m2 (eg, metal layers). The conductive layers 10m1 and 10m2 are integrated into the interlayer dielectrics 10r1 and 10r2 and are separated from each other. The conductive layers 10m1 and 10m2 are respectively coated or covered by the interlayer dielectrics 10r1 and 10r2. The conductive layers 10m1 and 10m2 are electrically connected to each other through a conductive interconnect structure (eg, via hole) 10v1. In some embodiments, the conductive layers 10m1 and 10m2 are sprayed on the surface by melting (or heating) the metal by thermal spraying technology. In some embodiments, the redistribution layer 10r may include any number of interlayer dielectric and conductive layers according to different embodiments. For example, the redistribution layer 10r may include N interlayer dielectric and conductive layers, where N is an integer. In some embodiments, the interlayer dielectric 10r2 includes a plurality of openings to expose a portion of the conductive layer 10m2. A conductive contact 10b1 is disposed on a surface (eg, second surface) 10r2 of the redistribution layer 10r and extends into the opening to make electrical contact with the exposed portion of the conductive layer 10m2.

The conductive pad 10p is placed on the surface (eg, the first surface) 101r of the redistribution layer 10r, and is electrically connected to the conductive layer 10m1 through a conductive interconnect structure (eg, via hole) 10v2. In some embodiments, the height of the conductive interconnect structure 10v2 is less than about 1 micrometer (μm). The conductive pad 10p includes a first portion 10p1 placed on the surface 101r of the redistribution layer 10r and a second portion 10p2 in contact with the first portion 10p1. The width D1 of the first portion 10p1 is greater than the width D2 of the second portion 10p2.

The dielectric layer 10d is placed on the surface 101r of the redistribution layer 10r to encapsulate or cover a portion of the sidewalls of the first portion 10p1 of the conductive pad 10p and the second portion 10p2 of the conductive pad 10p. In some embodiments, the dielectric layer 10d may include a molding compound, a pre-preg composite dimension (eg, pre-preg, pre-preg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride , silicon oxynitride, undoped silicon glass (UndopedSilicate Glass, USG) or any combination. In some embodiments, the molding compound may include, but is not limited to, an epoxy resin having a filler dispersed therein. In some embodiments, the prepreg may include, but is not limited to, a multi-layer structure formed by stacking or laminating a plurality of prepregs/sheets.

The dielectric layer 10n is placed on the dielectric layer 10d to wrap or cover the portion of the sidewall of the second portion 10p2 of the conductive pad 10p that is not covered by the dielectric layer 10d. In some embodiments, the surface 10n1 of the dielectric layer 10n is substantially coplanar with the surface 10p21 of the second portion 10p2 of the conductive pad 10p. In some embodiments, the dielectric layer 10n and the dielectric layer 10d are composed of different materials. For example, the dielectric layer 10n may be formed of silicon nitride, and the dielectric layer 10d may be formed of silicon oxide. In other embodiments, the dielectric layer 10n and the dielectric layer 10d may be composed of the same material.

The silicon layer 10s is placed on the surface 10n1 of the dielectric layer 10n. The silicon layer 10s includes openings to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p. In some embodiments, the thickness of the silicon layer 10s is about 10 μm to 30 μm.

A passivation layer 10g is placed on the silicon layer 10s and extends into the opening of the silicon layer 10s to cover a portion of the surface 10p21 of the second portion 10p2 of the conductive pad 10p. In some embodiments, the passivation layer 10g includes silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide.

A conductive layer (eg, under bump metallurgy, UBM) 10u is placed on the passivation layer 10g and extends into the opening of the silicon layer 10s to contact the surface 10p21 of the second portion 10p2 of the conductive pad 10p without the passivation layer 10g covered part. For example, the conductive layer 10u is in contact with the sidewall 10g1 of the passivation layer 10g and the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

Conductive contacts (eg, C4 pads) 10b2 are placed on the conductive layer 10u and extend into the recesses defined by the conductive layer 10u. In some embodiments, the conductive contact 10b2 is in electrical contact with the sidewall 10u1 and the bottom surface 10u2 of the recess defined by the conductive layer 10u.

As mentioned above, conventional through silicon via interposers increase the overall thickness of the semiconductor device. According to some embodiments of the present disclosure, the conductive contact 10b2 and the conductive contact 10b1 are electrically connected to each other by the conductive layers 10u, 10m1, 10m2, the conductive pad 10p, and the conductive interconnect structures 10v1, 10v2, so as to provide the semiconductor package device 1 and the substrate Electrical connection between bases 13 . Therefore, the overall thickness of the semiconductor package 100 will be reduced.

FIG. 1C illustrates an enlarged view of the portion of the semiconductor package 100 of FIG. 1A surrounded by box A in accordance with another embodiment of the present invention. The interposer 10 ′ of FIG. 1C is similar to the interposer 10 of FIG. 1B except that the interposer 10 ′ does not have the silicon layer 10s. In some embodiments, the passivation layer 10g is placed on the surface 10n1 of the dielectric layer 10n. The passivation layer 10g includes an opening to expose a portion of the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

2A, 2B, 2C, 2D, and 2E are cross-sectional views of a method of fabricating a semiconductor structure at various stages according to some embodiments of the present disclosure. Some of the drawings are simplified to facilitate a better understanding of embodiments of the present disclosure.

Referring to Figure 2A, a substrate 20 is provided. The substrate 20 includes a silicon carbide (SiC) substrate, a sapphire substrate, or a silicon substrate. The interconnect structure 21 is formed or placed on the surface (eg, the first surface) 201 of the substrate 20 . In some embodiments, interconnect structure 21 may include redistribution layer 10r, conductive pad 10p, dielectric layers 10d and 10n, and conductive contact 10b1 as shown in FIG. 1B .

Referring to FIG. 2B , electronic components 22 a , 22 b are formed or placed on the interconnect structure 21 and are electrically connected to the conductive contacts 10 b 1 of the interconnect structure 21 . Each electronic component 22a, 22b includes a plurality of semiconductor devices, such as, but not limited to, transistors, capacitors, and resistors, which are interconnected by die interconnect structures to form functional circuits to form integrated circuits. As can be appreciated by those skilled in the art, the device side of the semiconductor die includes an active portion having integrated circuits and interconnect structures. The electronic devices 22a, 22b may be any suitable integrated circuit devices, which according to various embodiments may include, but are not limited to, microprocessors (single core or multi-core), memory devices, chipsets, display devices, or application specific integrated circuits.

The underfill 22f is formed or placed to cover or encapsulate the active sides of the electronic components 22a, 22b and the conductive contacts 10b1 of the interconnect structure 21 . A reflow process can then be performed. The package 23 is then formed or placed to cover or encapsulate the electronic components 22a, 22b. In some embodiments, the package body 23 includes an epoxy resin having a filler dispersed therein, a molding compound (eg, epoxy molding compound or other molding compound), polyimide, phenolic compound, or material, material with polysiloxane, or a combination thereof.

Referring to FIG. 2C , the semiconductor structure of FIG. 2B is turned over, and a part of the substrate 20 is removed by applying a polishing process on the surface (eg, the second surface) 202 of the substrate 20 to reduce the thickness of the substrate 20 . In some embodiments, the thickness of the remaining portion of the substrate 20 is about 10 μm to 30 μm. The remainder of the substrate 20 may provide structural reinforcement to reduce structural bowing due to subsequent processing.

Openings 20h are formed in one or more predetermined positions of the substrate 20 to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p. The openings 20h may be formed by etching or other suitable processes. In some embodiments, the conductive pads 10p are completely covered by a dielectric layer. Since the substrate 20 and the dielectric layer are composed of different materials, two different etching processes must be performed to remove the substrate 20 and the dielectric layer respectively, which increases the manufacturing cost, time and difficulty. According to some embodiments of the present disclosure, since the surface 10p21 of the second portion 10p2 of the conductive pad 10p is not covered by the dielectric layer 10n, the conductive pad 10p can be exposed by performing a single etching process on the substrate 20 . In some embodiments, the substrate 20 may be completely removed to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

Referring to FIG. 2D, a conductive layer 20u (eg, UBM) is formed or placed within the opening 20h to contact the surface 10p21 of the second portion 10p2 of the conductive pad 10p. Next, conductive contacts 20b (eg, C4 pads) are formed or placed on the conductive layer 20u and extend into the openings 20h to form the semiconductor package device 2 .

Referring to FIG. 2E, the semiconductor structure of FIG. 2D is connected to a substrate 24 (eg, a BGA substrate). An underfill is formed or placed to cover or encapsulate the conductive contacts 20b, and a reflow process may then be performed. The support structures 24p are formed or placed along the edges of the substrate 24 to avoid cracking of the semiconductor structure device 2 due to other objects being placed thereon. In some embodiments, the process shown in FIGS. 2A-2E may be referred to as a "chip-first" process.

3A, 3B, and 3C are cross-sectional views of a method of fabricating a semiconductor structure at various stages according to some embodiments of the present disclosure. Some of the drawings are simplified to facilitate a better understanding of embodiments of the present disclosure. In some embodiments, the operations of FIG. 3A are performed subsequent to the operations of FIG. 2A.

Referring to FIG. 3A , the semiconductor structure shown in FIG. 2A is turned over, and the interconnect structure 21 is placed on the substrate 30 . The substrate 30 may be a glass substrate. The thickness of the substrate 20 is reduced by removing a portion of the substrate 20 by, eg, applying a grinding process on the surface of the substrate 20 . In some embodiments, the thickness of the remaining portion of the substrate 20 is about 10 μm to 30 μm. The remainder of the substrate 20 may provide structural reinforcement to reduce structural bowing due to subsequent processing.

Openings 20h are formed in one or more predetermined positions of the substrate 20 to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p. The openings 20h may be formed by etching or other suitable processes. As described above, since the surface 10p21 of the second portion 10p2 of the conductive pad 10p is not covered by the dielectric layer 10n, the conductive pad 10p can be exposed only by performing a single etching process on the substrate 20 . In some embodiments, the substrate 20 may be completely removed to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

Referring to FIG. 3B , the semiconductor structure of FIG. 3A is turned over and the substrate 30 is removed from the interconnect structure 21 . A conductive layer 20u (eg, UBM) is formed or placed within the opening 20h to contact the surface 10p21 of the second portion 10p2 of the conductive pad 10p. Next, conductive contacts 20b (eg, C4 pads) are formed or placed on the conductive layer 20u and extend into the openings 20h.

Referring to FIG. 3C, the semiconductor structure of FIG. 3B is turned upside down. The electronic components 22a, 22b are formed or placed on the interconnect structure 21 and are electrically connected to the conductive contacts 10b1 of the interconnect structure 21 . Each electronic component 22a, 22b includes a plurality of semiconductor devices, such as, but not limited to, transistors, capacitors, and resistors, which are interconnected by die interconnect structures to form functional circuits to form integrated circuits. As can be appreciated by those skilled in the art, the device side of the semiconductor die includes an active portion having integrated circuits and interconnect structures. The electronic devices 22a, 22b may be any suitable integrated circuit devices, which according to various embodiments may include, but are not limited to, microprocessors (single core or multi-core), memory devices, chipsets, display devices, or application specific integrated circuits.

The underfill 22f is formed or placed to cover or encapsulate the active sides of the electronic components 22a, 22b and the conductive contacts 10b1 of the interconnect structure 21 . A reflow process can then be performed. The package body 23 is then formed or placed to cover or encapsulate the electronic components 22a, 22b to form the semiconductor package device 2 as shown in Figure 3C. In some embodiments, the package body 23 includes an epoxy resin having a filler dispersed therein, a molding compound (eg, epoxy molding compound or other molding compound), polyimide, phenolic compound, or material, material with polysiloxane, or a combination thereof. In some embodiments, the process shown in FIGS. 3A-3C may be referred to as a "chip-last" process.

As used herein, the terms "substantially," "substantially," "approximately," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the term can refer to both instances in which the event or circumstance occurs explicitly as well as instances in which the event or circumstance occurs closely. For example, the term may mean less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1 %, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can mean that two surfaces are within a micrometer of difference along the same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm. When the terms "substantially", "about" and "about" are used in reference to an event or circumstance, it can mean that the event or circumstance occurs precisely or that the event or circumstance is an approximation.

The two surfaces may be considered coplanar or substantially coplanar if the displacement of the two planes is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, "conductive" and "electrical contact" may be considered the ability to transmit electrical current. Conductive materials generally mean that they do not interfere with the flow of current or cause little resistance. A unit of conductivity is Siemens/meter (S/m). Typically the conductive material has a conductivity greater than 10 ⁴ S/m, such as at least 10 ⁵ S/m or at least 10 ⁶ S/m. The conductivity of a material sometimes changes with temperature. Unless otherwise specified in this disclosure, the electrical conductivity of the material is measured at room temperature.

In the description of some embodiments, the "on" of an element being located on another element may include that the element is directly located on the other element (eg, in physical contact), or it may also mean that there is another element between the element and the other element. components.

While the invention has been described and illustrated with reference to specific embodiments of the invention, these descriptions and illustrations are not intended to limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to the manufacturing process and tolerances, differences may exist between the artistic representation in the present invention and the actual device. There may be other embodiments of the invention not specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the object, spirit and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to certain operations being performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims (14)

1. An intermediary layer comprising: a redistribution layer having a first surface and a second surface opposite the first surface; a conductive pad on the first surface of the redistribution layer, the conductive pad includes a first portion and a second portion; a dielectric layer on the first surface of the redistribution layer to cover the first portion of the conductive pad and expose the surface of the second portion of the conductive pad, wherein the conductive pad the surface of the second portion of the disk is substantially coplanar with the surface of the dielectric layer; a passivation layer on the surface of the dielectric layer, the passivation layer defining a recess to expose the surface of the second portion of the conductive pad; a first conductive contact located on the passivation layer and extending into the groove of the passivation layer, the redistribution layer includes a first interconnect layer including vias having a height of less than 1 micron; a conductive layer on the sidewall of the recess and the surface of the second portion of the conductive pad, wherein the first conductive contact is connected to the conductive pad by the conductive layer electrical connection; and a silicon layer between the passivation layer and the dielectric layer, wherein the silicon layer and the conductive layer are separated from each other in a direction substantially parallel to the surface of the dielectric layer. 2. The interposer of claim 1, wherein the width of the first portion of the conductive pad is greater than the width of the second portion of the conductive pad. 3. The interposer of claim 1, wherein: the dielectric layer further includes an oxide layer and a nitride layer, the oxide layer on the first surface of the redistribution layer and the nitride layer on the oxide layer; and The surface of the second portion of the conductive pad is substantially coplanar with a surface of the nitride layer. 4. The interposer of claim 1, wherein the via is electrically connected to the conductive pad. 5. The interposer of claim 4, further comprising a second conductive contact on the second surface of the redistribution layer and in electrical connection with the first interconnect layer. 6. The interposer of claim 1, wherein the conductive layer is placed between the passivation layer and the first conductive contact. 7. The interposer of claim 5, wherein the redistribution layer further comprises a second interconnect layer, and the second conductive contact is connected to the first interconnect through the second interconnect layer. Layer-by-layer electrical connection. 8. The interposer of claim 7, further comprising a die placed on the second surface of the redistribution layer and connected to the second conductive contact. 9. A semiconductor package comprising: a redistribution layer having a first surface and a second surface opposite the first surface; a conductive pad on the first surface of the redistribution layer; a dielectric layer on the first surface of the redistribution layer to cover a first portion of the conductive pad and expose a surface of a second portion of the conductive pad, wherein the The surface of the second portion is substantially coplanar with the surface of the dielectric layer; a silicon layer on the dielectric layer, the silicon layer defining a recess to expose the second portion of the conductive pad; conductive contacts placed on the silicon layer and extending into the grooves of the silicon layer; and a passivation layer on the silicon layer and extending into the recess to cover sidewalls of the recess and a portion of the second portion of the conductive pad, The redistribution layer includes a first interconnect layer including vias having a height of less than 1 micron. 10. The semiconductor package of claim 9, further comprising a conductive layer disposed between the conductive contact and the second portion of the conductive pad and the conductive contact and the conductive pad between passivation layers. 11. The semiconductor package of claim 9, wherein the width of the first portion of the conductive pad is greater than the width of the second portion of the conductive pad. 12. The semiconductor package of claim 9, wherein the dielectric layer further includes an oxide layer and a nitride layer, the oxide layer on the first surface of the redistribution layer and the nitride layer on the oxide layer; and The surface of the second portion of the conductive pad is substantially coplanar with a surface of the nitride layer. 13. The semiconductor package of claim 9, wherein the via is electrically connected to the conductive pad. 14. The semiconductor package of claim 10, wherein the passivation layer extends into a space between the silicon layer and the conductive layer.

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