CN107611042B - Fan-out type packaging method - Google Patents
Fan-out type packaging method Download PDFInfo
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- CN107611042B CN107611042B CN201710740363.2A CN201710740363A CN107611042B CN 107611042 B CN107611042 B CN 107611042B CN 201710740363 A CN201710740363 A CN 201710740363A CN 107611042 B CN107611042 B CN 107611042B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention discloses a fan-out type packaging method, which comprises the following steps: providing an intermediate board and a packaging substrate, wherein the intermediate board comprises a substrate and a wiring area positioned on one side of the substrate, a hole is formed in the substrate, a conductive layer is arranged in the hole, and the wiring area is electrically connected with one end of the conductive layer in the hole; the packaging substrate comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, wherein the bonding pad is arranged on one side of the silicon wafer base layer, the first rewiring layer is arranged on the other side of the silicon wafer base layer, and the bonding pad is electrically connected with the first rewiring layer; and electrically connecting a chip with the wiring area of the intermediate board, and electrically connecting the packaging substrate with the other end of the conductive layer, so that the chip is electrically connected with the bonding pad of the packaging substrate. Through the mode, the fan-shaped packaging precision can be improved, and the chips are prevented from being deviated.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out type packaging method.
Background
As the size of the chip is smaller and smaller along with the development of semiconductor technology, the density of I/O (input/output) pins on the surface of the chip is higher and higher, and fan-out type packaging has come to be used, which fans out the high density of I/O pins of the chip into low density of packaging pins.
At present, the existing fan-out packaging method includes the following procedures: providing a carrier plate, attaching a layer of double-sided adhesive film on the carrier plate, attaching the front side of the chip on the adhesive film, carrying out plastic packaging on the chip, stripping the adhesive film and the carrier plate, and forming a rewiring layer, ball planting and cutting on the front side of the chip.
The inventor of the invention discovers in the long-term research process that the fan-out type packaging method directly connects the chip to the packaging substrate, the node distance of the packaging substrate is larger, and the high-precision chip cannot be matched; secondly, due to the adoption of the glue film in the fan-out type packaging method, the glue film is stretched due to temperature change during plastic packaging of the chip, the chip is deviated during plastic packaging due to the conditions that the plastic packaging material, the chip and the carrier plate are warped due to different Coefficients of Thermal Expansion (CTE) and the like during plastic packaging, and the deviation of the chip causes difficulty in subsequent processes such as photoetching alignment.
Disclosure of Invention
The invention mainly solves the technical problem of providing a fan-out type packaging method and a packaging device, which can improve the fan-out type packaging precision and prevent chips from deviating.
In order to solve the technical problems, the invention adopts a technical scheme that: a fan-out packaging method is provided, the method comprising: providing an intermediate board and a packaging substrate, wherein the intermediate board comprises a substrate and a wiring area positioned on one side of the substrate, a hole is formed in the substrate, a conductive layer is arranged in the hole, and the wiring area is electrically connected with one end of the conductive layer in the hole; the packaging substrate comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, wherein the bonding pad is arranged on one side of the silicon wafer base layer, the first rewiring layer is arranged on the other side of the silicon wafer base layer, and the bonding pad is electrically connected with the first rewiring layer; and electrically connecting a chip with the wiring area of the intermediate board, and electrically connecting the packaging substrate with the other end of the conductive layer, so that the chip is electrically connected with the bonding pad of the packaging substrate.
The invention has the beneficial effects that: different from the situation of the prior art, the fan-out type packaging method adopted by the invention comprises the chip, the intermediate board and the packaging substrate, wherein the chip is connected with the packaging substrate through the intermediate board, the chip is connected with the wiring area of the intermediate board, the pitch of the nodes of the wiring area of the intermediate board is narrow, and the packaging precision can be improved; on the other hand, the chip is electrically connected with the wiring area of the intermediate board, so that the conditions that the temperature of the chip is changed during plastic package, the plastic film stretches due to the adoption of a packaging method of the plastic film, the chip is warped due to the difference of the Coefficient of Thermal Expansion (CTE) of the plastic package material, the chip and the carrier board during plastic package, and the like, which are caused by the adoption of the plastic film, are avoided; on the other hand, the packaging substrate comprises a silicon wafer base layer, and the silicon wafer base layer is good in thermal conductivity, so that heat dissipation of the fan-out type packaging device is facilitated.
Drawings
FIG. 1 is a schematic flow chart diagram of one embodiment of a fan-out packaging method of the present invention;
FIG. 2 is a schematic diagram of an embodiment of the interposer of FIG. 1;
FIG. 3 is a top view of one embodiment of a wafer in the field of semiconductor packaging;
FIG. 4 is a schematic structural diagram of one embodiment of a through-silicon-via formed in a silicon wafer substrate of the package substrate of FIG. 1;
FIG. 5 is a schematic flow chart diagram illustrating one embodiment of the package substrate provided in FIG. 1;
FIG. 6 is a schematic structural diagram of an embodiment of a package substrate corresponding to S201-S214 in FIG. 5;
FIG. 7 is a schematic flow chart diagram illustrating another embodiment of the package substrate provided in FIG. 1;
FIG. 8 is a schematic structural diagram of an embodiment of a package substrate corresponding to S301-S307 in FIG. 7;
FIG. 9 is a schematic flow chart diagram illustrating another embodiment of the package substrate provided in FIG. 1;
FIG. 10 is a schematic structural diagram of an embodiment of a package substrate corresponding to S407-S419 in FIG. 9;
FIG. 11 is a flow diagram of one embodiment of a fan-out package of the present invention;
FIG. 12 is a schematic diagram of a structure of one embodiment of a packaged device corresponding to S502-S506 in FIG. 11;
fig. 13 is a schematic structural diagram of another embodiment of a packaged device corresponding to step S506 in fig. 11;
FIG. 14 is a schematic structural diagram of one embodiment of a fan-out packaging method of the present invention;
FIG. 15 is a schematic diagram of the structure of one embodiment of a packaged device corresponding to steps S602-5606 in FIG. 14;
fig. 16 is a schematic structural diagram of another embodiment of a packaged device corresponding to step S606 in fig. 14;
FIG. 17 is a schematic structural diagram of one embodiment of a fan-out packaged device of the present invention;
FIG. 18 is a schematic structural diagram of another embodiment of a fan-out packaged device of the present invention;
FIG. 19 is a schematic structural diagram of another embodiment of a fan-out packaged device of the present invention;
FIG. 20 is a schematic structural diagram of another embodiment of a fan-out packaged device in accordance with the present invention.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a fan-out packaging method according to an embodiment of the present invention, the method including:
s101: providing an intermediate board and a packaging substrate, wherein the intermediate board comprises a substrate and a wiring area positioned on one side of the substrate, the substrate is provided with a hole, the hole comprises a conductive layer, and the wiring area is electrically connected with one end of the conductive layer in the hole; the packaging substrate comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, wherein the bonding pad is arranged on one side of the silicon wafer base layer, the first rewiring layer is arranged on the other side of the silicon wafer base layer, and the bonding pad is electrically connected with the first rewiring layer;
in one application scenario, as shown in fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the interposer in fig. 1. The intermediary boards used in the invention can be sold directly on the market. The interposer 1 includes a substrate 10 and a wiring region 12 on one side of the substrate 10; the substrate 10 is made of silicon, glass, ceramic and the like; the substrate 10 includes a hole 100, in this embodiment, the hole 100 penetrates through the substrate 10 (as shown in fig. 2 (a)), and in other embodiments, the hole may not penetrate through the substrate (as shown in fig. 2 (b)); the hole 100 includes a conductive layer 1000 therein, wherein the conductive layer 1000 is made of metal, such as gold, copper, platinum, etc., and can be formed by chemical vapor deposition; in other embodiments, the hole 100 may further include an insulating layer 1002 and a seed layer 1004, wherein the insulating layer 1002 is made of oxide, nitride or oxynitride, and the seed layer 1004 is made of aluminum, gold, copper, platinum, or the like; in another embodiment, the end of the via 100 contacting the wiring region 12 further includes a first metal pad 1006, and the first metal pad 1006 is electrically connected to the conductive layer 1000 in the via 100. The wiring region 12 includes an insulating layer 120 and a rewiring layer 122 located in the insulating layer 120; the insulating layer 12 is made of oxide, nitride or oxynitride; the redistribution layer 122 is made of metal, and the redistribution layer 122 is electrically connected with the conductive layer in the hole 100 and is made of copper, titanium, or the like; in other embodiments, the wiring region 12 further includes a second metal pad 124, the second metal pad 124 may be arranged more densely than the first metal pad 1006 or the hole 100, the second metal pad 124 may be electrically connected to the chip at a later time, and when the chip is electrically connected to the second metal pad 124, the packaging accuracy thereof may be improved.
In one application scenario, the silicon wafer substrate of the package substrate may be directly provided with the bonding pads, as shown in fig. 3, and fig. 3 is a top view of an embodiment of the wafer in the semiconductor packaging field. The wafer 20 includes a base layer 220 and a bonding pad 200, the base layer 220 has a front surface and a back surface, the bonding pad 200 is formed on the front surface of the base layer 220, and correspondingly, a first redistribution layer is formed on the back surface of the base layer 120; in this embodiment, the base layer 120 is made of silicon, and the thermal conductivity of silicon is better, so that the thermal dissipation performance of the subsequent fan-out package device can be enhanced.
Specifically, the step S101 of providing the package substrate includes: providing a silicon wafer substrate provided with bonding pads, namely providing a wafer 20 as shown in fig. 3; a first redistribution layer and a second redistribution layer are formed on two opposite sides of the silicon wafer base layer, the second redistribution layer is formed on the bonding pad and electrically connected with the bonding pad, that is, the second redistribution layer is formed on the bonding pad 200 on the front surface of the base layer 220 shown in fig. 3, and the first redistribution layer is formed on the back surface of the base layer 220.
Since the silicon wafer base layer itself is poor in conductivity, in order to achieve the purpose of electrically connecting the pad with the first redistribution layer, in one embodiment, the state including the silicon wafer base layer is set so that the side thereof having the pad is positioned below before the first redistribution layer is formed; and forming a through silicon via at a position, back to the bonding pad, of the silicon wafer base layer. Referring to fig. 4, one side of the silicon wafer base layer 30 having the bonding pad 33 faces downward, and a through silicon via 34 is formed at a position corresponding to the bonding pad 33 on a side of the silicon wafer base layer 30 opposite to the bonding pad 33 by plasma etching, in other embodiments, the through silicon via may be formed in other manners or the bonding pad may be electrically connected to the first redistribution layer in other manners; in one application scenario, the angle between the side a of the through-silicon via 34 and the side b of the silicon wafer base layer 30 is 60-80 ° (e.g., 60 °, 70 °, 80 °, etc.), and the aspect ratio of the through-silicon via 34 is less than 10:1, i.e., h/d < 10 (e.g., h/d ═ 0.5, 3, 5, 8, 9, etc.).
S102: electrically connecting the chip with the wiring region of the interposer, and electrically connecting the package substrate with the other end of the conductive layer, so that the chip is electrically connected with the bonding pad of the package substrate;
specifically, in one embodiment, the step S102 includes: the chip and the packaging substrate are positioned on the two opposite sides of the intermediate board, the chip is electrically connected with the wiring area of the intermediate board, and the second rewiring layer of the packaging substrate is electrically connected with the other end of the conductive layer in the hole of the intermediate board, so that the chip is electrically connected with the bonding pad of the packaging substrate; in one application scenario, the chip surface is provided with a metal bump, and the chip is reflow-soldered to the wiring region through the metal bump, for example, the chip is reflow-soldered to the second metal pad 124 (shown in fig. 2) of the wiring region 12 through the metal bump.
In another embodiment, the step S101 of providing the hole of the interposer through the substrate (as shown in fig. 2 (a)), and the step S102 of electrically connecting the package substrate to the other end of the conductive layer includes: and implanting a first solder ball on one side of the hole back to the wiring area to electrically connect the first solder ball with the packaging substrate, wherein in an application scene, the first solder ball is electrically connected with a second re-wiring layer of the packaging substrate.
In another embodiment, the step S101 of providing the hole of the interposer not penetrating through the substrate (as shown in fig. 2 (a)), and the step S102 of electrically connecting the package substrate to the other end of the conductive layer includes: grinding the substrate of the medium plate to expose the holes; and implanting a first solder ball on one side of the exposed hole back to the wiring area to electrically connect the first solder ball with the packaging substrate, wherein in an application scene, the first solder ball is electrically connected with a second re-wiring layer of the packaging substrate.
Next, the provision of the package substrate in the above-described packaging method will be described in detail with reference to several specific embodiments.
In a first embodiment, referring to fig. 5, fig. 5 is a schematic flow chart illustrating an embodiment of the package substrate provided in fig. 1; the method comprises the following steps:
s201: providing a silicon wafer base layer provided with a bonding pad; specifically, referring to fig. 6 (a), in an application scenario, the package substrate includes a silicon wafer substrate 40 directly provided with a bonding pad 42, i.e. a wafer directly accessible by a general packaging and testing factory;
s202: forming a first passivation layer on one side of the silicon wafer base layer, wherein the bonding pad is arranged on the first passivation layer, and arranging a first opening at a position, corresponding to the bonding pad, of the first passivation layer; specifically, referring to fig. 6 (b), in one embodiment, a passivation layer 44 is first coated on the surface of the silicon wafer substrate 40, and then a first opening 440 is formed at a position of the passivation layer 44 corresponding to the pad 42 by exposure, development or other means, so that the pad 42 is exposed; in another embodiment, a dielectric layer (not shown) may be further formed on the surface of the first passivation layer 44 opposite to the silicon wafer substrate 40, and an opening (not shown) is also formed on the dielectric layer at a position corresponding to the pad 44 to expose the pad 42.
S203: forming a first seed layer on the surface of the first passivation layer opposite to the silicon wafer base layer; specifically, referring to fig. 6 (c), in one embodiment, the material of the first seed layer 46 is one or a mixture of titanium, aluminum, copper, gold, and silver, and the process of forming the first seed layer 46 is a sputtering process or a physical vapor deposition process.
S204: forming a first mask layer on the surface of the first seed layer, which is opposite to the silicon wafer base layer, and arranging a second opening at the position, corresponding to the bonding pad, of the first mask layer; specifically, referring to fig. 6 (d), the material of the first mask layer 48 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in the embodiment, the material of the first mask layer 48 is photoresist, a second opening 480 penetrating through the first mask layer 48 is formed in the first mask layer 48 by using a photolithography process, and the second opening 480 is located above the pad 42.
S205: forming a second rewiring layer in the second opening; specifically, referring to fig. 6 (e), in one embodiment, a second redistribution layer 41 is formed in the second opening 480 by an electroplating process, and the material of the second redistribution layer 41 is copper or other suitable metal. In this embodiment, the height of the second rewiring layer 41 is lower than the depth of the second opening 480, and in other embodiments, the height of the second rewiring layer 41 may be the same as the depth of the second opening 480.
S206: removing the first seed layer except the first mask layer and the second rewiring layer; specifically, referring to fig. 6 (f), in one embodiment, the first mask layer 48 is removed by photolithography to expose a portion of the first seed layer 46; then, removing part of the exposed first seed layer 46 by using a wet etching process or a dry etching process, and only remaining the first seed layer 46 below the second rewiring layer 41; wherein, the bonding pad 42, the first seed layer 46 and the second rewiring layer 41 are electrically connected;
s207: grinding one side of the silicon wafer base layer, which is opposite to the bonding pad, so that the thickness of the silicon wafer base layer is smaller than or equal to a preset thickness; specifically, referring to fig. 6 (g), in an application scenario, the thickness of the silicon wafer substrate 40 of a wafer that is generally taken directly from an encapsulation factory is larger, so in this embodiment, the side of the silicon wafer substrate 40 opposite to the bonding pad 42 needs to be ground to make the thickness smaller than or equal to a predetermined thickness, for example, the predetermined thickness is 100um, and the thickness of the ground silicon wafer substrate 40 is 60, 80um, and so on.
S208: arranging the state of the silicon wafer base layer to enable one side with the bonding pad to be positioned below the bonding pad, and forming a silicon through hole in the position, back to the bonding pad, of the silicon wafer base layer; specifically, referring to fig. 6 (h), the manner of forming the through silicon via 400 is already mentioned in the above embodiments, and is not described herein again.
S209: forming a third mask layer on one side of the silicon wafer base layer, which is opposite to the bonding pad, and forming a fifth opening at the position, corresponding to the bonding pad, of the third mask layer; specifically, referring to fig. 6 (i), the material of the third mask layer 43 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in the embodiment, the material of the third mask layer 43 is photoresist, and a fifth opening 430 penetrating through the third mask layer 43 is formed in the third mask layer 43 by using a photolithography process, so as to expose the pad 42.
S210: forming a third sub-layer on the surface of the third mask layer, which is opposite to the surface of the silicon wafer base layer; specifically, referring to fig. 6 (j), in one embodiment, the material of the third sub-layer 45 is one or a mixture of titanium, aluminum, copper, gold, and silver, and the process of forming the third sub-layer 45 is a sputtering process or a physical vapor deposition process.
S211, forming a fourth mask layer on the surface of the third sub-layer opposite to the silicon wafer base layer, and forming a sixth opening on the fourth mask layer; specifically, referring to fig. 6 (k), the material of the fourth mask layer 47 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in this embodiment, the material of the fourth mask layer 47 is photoresist, and a sixth opening 470 penetrating through the fourth mask layer 47 is formed in the fourth mask layer 47 by using a photolithography process.
S212: forming a first rewiring layer in the sixth opening; specifically, referring to fig. 6 (l), in one embodiment, a first redistribution layer 49 is formed in the sixth opening 470 by an electroplating process, and the material of the first redistribution layer 49 is copper or other metal. In fig. 6 (l), the first redistribution layer 49 fills the sixth opening 470, and in other embodiments, the first redistribution layer 49 may also be filled with a layer in the sixth opening 470, and the thickness thereof may be designed according to practical situations, which is not limited by the invention.
S213: removing the fourth mask layer and the third sublayer except the first rewiring layer; specifically, referring to fig. 6 (m), in one embodiment, the fourth mask layer 47 is removed by a photolithography process to expose a portion of the third seed layer 45; then, removing the exposed part of the third sublayer 45 by using a wet etching process or a dry etching process, and only remaining the third sublayer 45 below the first redistribution layer 49; the first redistribution layer 49 and the third sublayer 45 are electrically connected to the pad 42.
S214: arranging a first blocking layer on the surface of the first rewiring layer opposite to the silicon wafer base layer, and forming a seventh opening on the first blocking layer; specifically, referring to fig. 6 (n), the material of the first blocking layer 411 has an insulating property, and in one embodiment, a seventh opening 4110 is formed on the first blocking layer 411 by photolithography or other etching methods.
In a second embodiment, referring to fig. 7, fig. 7 is a schematic flow chart illustrating another embodiment of the package substrate provided in fig. 1, the method mainly differs from the first embodiment in that the providing of the package substrate includes: the reinforcing plate is attached to one side, back to the bonding pad, of the silicon wafer base layer, and the specific flow is as follows:
s301: providing a silicon wafer base layer provided with a bonding pad, and attaching a reinforcing plate to one side of the silicon wafer base layer, which is back to the bonding pad; specifically, referring to fig. 8 (a), the silicon wafer substrate 50 with a thickness less than or equal to a predetermined thickness may be selected at the beginning according to actual requirements, for example, when the predetermined thickness is 80um, the silicon wafer substrate 50 with a thickness of 50, 60, 80um, etc. may be directly selected; in order to prevent the strength of the silicon wafer substrate 50 from being insufficient in the subsequent preparation process, in this embodiment, a reinforcing plate 54 is attached to a side of the silicon wafer substrate 50 opposite to the bonding pad 52, the reinforcing plate 54 may be made of glass, metal, silicon wafer, or the like, and the reinforcing plate 54 and the silicon wafer substrate 50 may be attached and fixed by a double-sided adhesive film.
S302-S306 are the same as S202-S206 in the above embodiments, and are not described herein, and their structures can be seen in FIGS. 8 (b) -8 (f).
S307: removing the reinforcing plate; specifically, as shown in fig. 8 (g), in one embodiment, the reinforcing plate 54 and the silicon wafer substrate 50 are adhered by a double-sided adhesive film, which can be directly peeled off, so as to remove the reinforcing plate 54.
S308-S314 are the same as S208-S214 in the above embodiments, and are not described herein, and their structures can be seen in FIGS. 6 (h) -6 (n).
In a third embodiment, please refer to fig. 9, fig. 9 is a schematic flow chart of another embodiment of the package substrate provided in fig. 1, the method mainly differs from the first embodiment in that a side of the silicon wafer base layer having the bonding pads can be subjected to multiple times of wiring, that is, at least one redistribution layer is formed on a side of the second redistribution layer opposite to the silicon wafer base layer, in this embodiment, the side of the silicon wafer base layer having the bonding pads includes two wiring layers, and the specific flow is as follows:
s401 to S406 are the same as S201 to S206 in the above embodiments, and are not described herein again, and the structure thereof can be seen in fig. 6 (a) -6 (f).
S407: forming a first dielectric layer on the surface of the second rewiring layer opposite to the silicon wafer base layer, and arranging a third opening on the first dielectric layer; specifically, referring to fig. 10 (a), in one embodiment, the first dielectric layer 60 is made of a photoresist, and after a layer of photoresist is coated on the surface of the second redistribution layer 41, a third opening 600 is formed on the first dielectric layer 60 by using a photolithography process.
S408: forming a second seed layer on the surface of the first dielectric layer opposite to the silicon wafer base layer; specifically, referring to fig. 10 (b), in one embodiment, a second seed layer 62 may be formed on a surface of the first dielectric layer 60 opposite to the silicon wafer base layer 40 by a sputtering process, and the material of the second seed layer 62 is copper, titanium, or other metal.
S409: forming a second mask layer on the surface of the second seed layer, which is opposite to the silicon wafer base layer, and arranging a fourth opening on the second mask layer; specifically, referring to fig. 10 (c), in one embodiment, the second mask layer 64 is made of a photoresist, and a photolithography process is used to form the fourth opening 640.
S410: forming a third rewiring layer in the fourth opening; specifically, referring to fig. 10 (d), an electroplating process may be used to form the third redistribution layer 66 in the fourth opening 640, and the material of the third redistribution layer 66 may be a metal such as copper; in fig. 10 (d), the third redistribution layer 66 fills the entire fourth opening 640, in other embodiments, the third redistribution layer 66 may only be fully laid in the fourth opening 640, and the thickness thereof may be set according to actual conditions.
S411: removing the second mask layer and the second seed layer except the third rewiring layer; specifically, referring to fig. 10 (e), after the second mask layer 64 is removed, the exposed second seed layer 62 is etched away; the second redistribution layer 41, the second seed layer 62, and the third redistribution layer 66 are electrically connected.
Steps S207 to S214 in the first embodiment are the same as steps S412 to S419, and are not described herein again, and the structure thereof can be seen in fig. 10 (f) to 10 (m).
The above illustration shows only three embodiments, and it is within the scope of the present invention to provide a fan-out package method involving rewiring of the silicon wafer substrate on the side opposite to the bond pads.
Next, the package substrate prepared in any of the above embodiments is packaged with an interposer and a chip.
Referring to fig. 11, fig. 11 is a schematic flow chart illustrating a fan-out packaging method according to an embodiment of the present invention, the method including:
s501: providing an interposer and a package substrate; specifically, in the present embodiment, the structure of the interposer is as shown in fig. 2 (a), and the holes of the interposer penetrate through the substrate and can be purchased directly from the market; in other embodiments, the interposer may be configured as shown in fig. 2 (b), that is, the holes of the interposer do not penetrate through the substrate, and the step of providing the interposer includes: grinding the substrate of the medium plate to expose the holes in the substrate; the structure of the package substrate can be found in any of the above embodiments, and in this embodiment, the structure of the package substrate is described by taking the structure in the first embodiment as an example.
S502: electrically connecting the chip with the wiring region of the interposer; specifically, referring to fig. 12 (a), a metal bump 700 is disposed on the surface of the chip 70, and the chip 70 is reflow-soldered to the wiring region 720 of the interposer 72 through the metal bump 700.
S503: plastically packaging the chip and one side of the medium plate, which is provided with the wiring area, so that the chip is positioned in the plastic packaging layer; specifically, see fig. 12 (b); in one embodiment, the surface of the interposer 72 where the wiring region 720 is disposed is filled with a liquid or powder resin, so that the chip 40 and the wiring region 720 are in the resin material and cured to form the molding layer 74.
S504: planting a first solder ball on one side of the hole back to the wiring area; specifically, referring to fig. 12 (c), a ball-planting machine may be used to plant the first solder balls 76 on the exposed holes 722, and the material of the first solder balls 76 may be tin, etc.
S505: electrically connecting the first solder balls with a second rewiring layer of the packaging substrate; specifically, referring to fig. 12 (d), in the present embodiment, the structure of the package substrate 78 is the same as that in the first embodiment, that is, the first solder balls 76 are electrically connected to the second redistribution layer 780 of the package substrate 78; in other embodiments, the structure of the package substrate 78 may be other structures, which is not limited in the present invention.
S506: arranging a second solder ball on one side of the first rewiring layer of the packaging substrate; specifically, referring to fig. 12 (e), the second solder balls 71 may be directly disposed at the seventh openings of the first barrier layer 784 on the first redistribution layer 782 side of the package substrate 78; in another embodiment, referring to fig. 13, the second solder balls may be disposed in a manner of forming an under-ball metal layer; specifically, a fourth sub-layer 80 is formed on the surface of the first barrier layer 784 opposite to the package substrate 78 (as shown in fig. 13 (a)), where the fourth sub-layer 80 is formed by sputtering a titanium layer and then a copper layer on the titanium layer; forming a fifth mask layer 82 on the surface of the fourth sub-layer opposite to the package substrate 78, and forming an eighth opening 820 on the fifth mask layer 82 corresponding to a seventh opening (not shown) of the first barrier layer 784 (as shown in fig. 13 (b)); forming an under-ball metal layer 84 in the eighth opening 820 (as shown in fig. 13 (c)), where the material of the under-ball metal layer 84 may be copper, and may be formed by electroplating; removing the fifth mask layer 82 and the fourth sub-layer 80 under the fifth mask layer 82 (as shown in fig. 13 (d)); forming second solder balls 86 on the positions corresponding to the under-ball metal layers 84, dropping the second solder balls 86 to the positions corresponding to the under-ball metal layers 84 by a ball-mounting machine, and reflowing (as shown in fig. 13 (e)); the second solder balls 86, the ubm layer 84, the fourth sub-layer 80, and the first redistribution layer 782 are electrically connected.
Referring to fig. 14, fig. 14 is a schematic structural diagram of an embodiment of a fan-out package method according to the present invention, the method including:
s601: providing an interposer and a package substrate; this step is the same as step S501, and is not described herein again.
S602: planting a first solder ball in the hole back-to-wiring area; specifically, this step is the same as step S504 in the above embodiment, and the structure thereof can be seen in fig. 15 (a).
S603: electrically connecting the first solder balls with a second rewiring layer of the packaging substrate; specifically, this step is the same as step S505 described above, and the structure thereof can be seen in fig. 15 (b).
S604: electrically connecting the chip with the wiring region of the interposer; specifically, this step is the same as step S502 described above, and the structure thereof can be seen in fig. 15 (c).
S605: plastically packaging one side of the chip and the packaging substrate, which is provided with the second rewiring layer, so that the chip and the middle plate are positioned in the plastic packaging layer; specifically, referring to fig. 15 (d), in one embodiment, a liquid or powder resin is filled into the side of the package substrate 94 where the second redistribution layer 940 is formed, so that the chip 40 and the second redistribution layer 940 are in the resin material and cured to form the molding layer 96, and the chip 98 and the interposer 90 are located inside the molding layer 96.
S606: arranging second solder balls on the first rewiring layer of the packaging substrate; specifically, this step is the same as step S507, and the structure thereof can be seen in fig. 15 (e) or fig. 16.
Referring to fig. 17, fig. 17 is a schematic structural diagram of a fan-out package device according to an embodiment of the present invention, where the device 11 includes an interposer 110, a package substrate 112, and a chip 114, where the interposer 110 includes a substrate 1100, a wiring region 1102 located at one side of the substrate 1100, the substrate 1100 has a hole 1104 formed therein, the hole 1104 includes a conductive layer 1106 therein, and the wiring region 1102 is electrically connected to one end of the conductive layer 1106 in the hole 1104; the package substrate 112 includes a silicon wafer base layer 1120, a pad 1122 and a first redistribution layer 1124, wherein the pad 1122 is disposed on one side of the silicon wafer base layer 1120, the first redistribution layer 1124 is disposed on the other side of the silicon wafer base layer 1120, and the pad 1122 and the first redistribution layer 1124 are electrically connected; in one embodiment, the chip 114 is electrically connected to the wiring region 1102 of the interposer 110, and the package substrate 112 is electrically connected to the other end of the conductive layer 1106, so that the chip 114 is electrically connected to the pad 1122 of the package substrate 112.
In an application scenario, a metal bump 1140 is disposed on the surface of the chip 114, and the chip 114 is electrically connected to the wiring region 1102 through the metal bump 1140; the package substrate 112 further includes a second redistribution layer 1126, and the second redistribution layer 1126 is disposed on the pads 1122 and electrically connected to the pads 1122. In the present embodiment, the second redistribution layer 1126 of the package substrate 112 is electrically connected to the conductive layer 1106 in the hole 1104 of the interposer 110; in one embodiment, the hole 1104 of the interposer 110 extends through the entire substrate 1100, the side of the hole 1104 facing the second redistribution layer 1126 is connected to the first solder ball 116, and the conductive layer 1106 in the hole 1104 is electrically connected to the second redistribution layer 1126 via the first solder ball 116.
In one application scenario, the thickness of the silicon wafer substrate 1120 is equal to or less than a predetermined thickness, for example, the predetermined thickness is 100um, and the thickness of the silicon wafer substrate 1120 may be 50, 70, 80um, etc. The silicon wafer substrate 1120 may be directly provided with bonding pads 1122, such as wafers that are typically directly accessible to a packaging and testing facility; the thickness of the silicon wafer substrate layer of the directly taken wafer may be directly less than or equal to the predetermined thickness, and may also exceed the predetermined thickness, and when the thickness of the silicon wafer substrate layer of the wafer exceeds the predetermined thickness, the back surface of the silicon wafer substrate layer 1120 needs to be ground, so that the thickness of the silicon wafer substrate layer in the fan-out package device provided by the invention is less than or equal to the predetermined thickness.
In another application scenario, due to poor conductivity of the silicon wafer substrate 1120, in order to electrically connect the pad 1122 and the first redistribution layer 1124 located on two opposite sides of the silicon wafer substrate 1120, a through-silicon via (not shown) is formed on a side of the silicon wafer substrate 1120 opposite to the pad 1122, and the position of the through-silicon via corresponds to the position of the pad 1122, so that the first redistribution layer 1124 is electrically connected to the pad 1122 through the through-silicon via.
The structure of the fan-out package device provided by the present invention will be further described with respect to several specific embodiments.
With continued reference to fig. 17, in one embodiment, the side of the silicon wafer substrate 1120 opposite the bonding pads 1122 includes, in addition to the first redistribution layer 1124, the device 11 further including: a third mask layer 1128 disposed between the first redistribution layer 1124 and a side of the silicon wafer substrate 1120 opposite to the pad 1122, and a fifth opening (not shown) is disposed at a position corresponding to the pad 1122; a third sub-layer 1121 disposed between the third mask layer 1128 and the first redistribution layer 1124; the first redistribution layer 1124, the third sub-layer 1121, and the pad 1122 are electrically connected; a first blocking layer 1123 disposed on a side of the first redistribution layer 1124 opposite to the silicon wafer base layer 1120, and a seventh opening (not shown) is formed on the first blocking layer 1123; the second solder balls 1125 are disposed in the seventh opening (not labeled) and electrically connected to the first redistribution layer 1124. The side of the silicon wafer base layer 1120 provided with the pads 1122 includes, in addition to the second re-wiring layer 1126, the device 11 further including: a first passivation layer 1127 disposed between the pad 1122 side of the silicon wafer base layer 1120 and the second redistribution layer 1126, and the first passivation layer 1127 has a first opening (not shown) corresponding to the pad 1122; a first seed layer 1129 disposed between the first passivation layer 1127 and the second rewiring layer 1126; the pad 1122, the first seed layer 1129, and the second redistribution layer 1126 are electrically connected. The molding compound layer 116, the molding compound layer 116 covers the chip 114 and the interposer 110 at the side where the wiring region 1102 is disposed.
Referring to fig. 18, fig. 18 is a schematic structural diagram of another embodiment of a fan-out package device according to the present invention; in this embodiment, the difference between the packaged device and the packaged device in fig. 17 is the molding compound 130, and in this embodiment, the molding compound 130 covers the side of the chip 132, the interposer 134 and the package substrate 136 where the second redistribution layer 1360 is disposed.
Referring to fig. 19, fig. 19 is a schematic structural diagram of another embodiment of a fan-out package device according to the present invention; in this embodiment, the difference between the packaged device and the packaged device in fig. 17 is that the solder balls are disposed on the side of the silicon wafer substrate opposite to the pads, and the under-ball metal layer is disposed in this embodiment. Specifically, the packaged device includes, in addition to the structure in fig. 17 described above, further: a fourth sub-layer 150 covering the seventh opening (not labeled) of the first barrier layer 152 and disposed on a side of the first barrier layer 152 opposite to the silicon wafer base layer 156; an under-ball metal layer 158 disposed on a side of the fourth sub-layer 150 opposite to the silicon wafer base layer 156; a second solder ball 151 disposed on a side of the ubm layer 158 opposite to the silicon wafer base layer 156; the second solder balls 151, the ubm layer 158, the fourth sub-layer 150, and the first redistribution layer 153 are electrically connected.
Referring to fig. 20, fig. 20 is a schematic structural diagram of a fan-out package device in accordance with another embodiment of the present invention; in this embodiment, the difference between the packaged device and the packaged device in fig. 17 is that rewiring may be performed several times on the side of the silicon wafer substrate on which the pads are disposed, and for example, twice on the side of the silicon wafer substrate on which the pads are disposed, that is, the side of the second rewiring layer 170 opposite to the side of the silicon wafer substrate 172 further includes a third rewiring layer 174. Specifically, the structure of the packaged device that is the same as that in fig. 17 is not described herein again, and the packaged device in this embodiment further includes: a first dielectric layer 176 disposed between the second redistribution layer 170 and the third redistribution layer 174, and a third opening (not shown) is disposed on the first dielectric layer 176; a second seed layer 178 disposed between the first dielectric layer 176 and the third re-wiring layer 174; wherein the second redistribution layer 170, the second seed layer 178, and the third redistribution layer 174 are electrically connected; the surface of the hole 1710 of the interposer 171 is provided with a first solder ball 173, and a conductive layer (not labeled) in the hole 1710 of the interposer 171 is reflow-soldered to the third redistribution layer 174 via the first solder ball 173.
In other embodiments, the package device may also have other structures, and the present invention is not limited thereto.
In summary, different from the situation of the prior art, the fan-out type packaging method adopted by the invention comprises a chip, an interposer and a packaging substrate, wherein the chip and the packaging substrate are connected through the interposer, the chip is connected with the wiring area of the interposer, and the pitch of the nodes of the wiring area of the interposer is narrow, so that the packaging precision can be improved; on the other hand, the chip is electrically connected with the wiring area of the intermediate board, so that the conditions that the temperature of the chip is changed during plastic package, the plastic film stretches due to the adoption of a packaging method of the plastic film, the chip is warped due to the difference of the Coefficient of Thermal Expansion (CTE) of the plastic package material, the chip and the carrier board during plastic package, and the like, which are caused by the adoption of the plastic film, are avoided; on the other hand, the packaging substrate comprises a silicon wafer base layer, and the silicon wafer base layer is good in thermal conductivity, so that heat dissipation of the fan-out type packaging device is facilitated.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A fan-out packaging method, the method comprising:
providing an intermediate board and a packaging substrate, wherein the intermediate board comprises a substrate and a wiring area positioned on one side of the substrate, a hole is formed in the substrate, a conductive layer is arranged in the hole, and the wiring area is electrically connected with one end of the conductive layer in the hole; the packaging substrate comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, wherein the bonding pad is arranged on one side of the silicon wafer base layer, the first rewiring layer is arranged on the other side of the silicon wafer base layer, and the bonding pad is electrically connected with the first rewiring layer;
electrically connecting a chip with the wiring region of the interposer, and electrically connecting the package substrate with the other end of the conductive layer, so that the chip is electrically connected with the bonding pad of the package substrate;
wherein the providing a package substrate comprises: providing the silicon wafer base layer provided with the bonding pad, and attaching a reinforcing plate to one side of the silicon wafer base layer, which is opposite to the bonding pad, wherein the thickness of the silicon wafer base layer is less than or equal to 80 um; forming a first passivation layer on one side of the silicon wafer base layer, where the bonding pad is arranged, and arranging a first opening at a position, corresponding to the bonding pad, of the first passivation layer; forming a first seed layer on the surface of the first passivation layer opposite to the silicon wafer base layer; forming a first mask layer on the surface of the first seed layer, which is opposite to the silicon wafer base layer, and arranging a second opening at the position, corresponding to the bonding pad, of the first mask layer; forming a second rewiring layer in the second opening; removing the first mask layer and the first seed layer except the second re-wiring layer; wherein the bonding pad, the first seed layer, and the second re-wiring layer are electrically connected; removing the reinforcing plate; setting the state of the silicon wafer substrate to enable one side with the bonding pad to be positioned below; forming a through silicon via at a position of the silicon wafer base layer, which is opposite to the bonding pad, wherein an included angle between the side edge of the through silicon via and the side edge of the silicon wafer base layer is 60-80 degrees, and the aspect ratio of the through silicon via is less than 10: 1; forming a third mask layer on one side, back to the bonding pad, of the silicon wafer base layer, and forming a fifth opening in a position, corresponding to the bonding pad, of the third mask layer; forming a third sub-layer on the surface of the third mask layer, which is opposite to the surface of the silicon wafer base layer; forming a fourth mask layer on the surface of the third seed layer opposite to the silicon wafer base layer, and forming a sixth opening on the fourth mask layer; forming the first redistribution layer within the sixth opening; removing the fourth mask layer and a third sublayer except the first rewiring layer; wherein the first redistribution layer and the third sublayer are electrically connected to the pad;
wherein the electrically connecting the chip with the wiring region of the interposer and the package substrate with the other end of the conductive layer comprises: electrically connecting the second rewiring layer of the package substrate to the conductive layer in the hole of the interposer; electrically connecting the chip with the wiring region of the interposer; and plastically packaging one side of the chip and the packaging substrate, which is provided with the second rewiring layer, so that the chip, the interposer and the second rewiring layer are positioned in a plastic packaging layer.
2. The method of claim 1, wherein electrically connecting the chip to the wiring region of the interposer and the package substrate to the other end of the conductive layer comprises:
the chip and the packaging substrate are positioned on two opposite sides of the intermediate board, the chip is electrically connected with the wiring area of the intermediate board, and the second rewiring layer of the packaging substrate is electrically connected with the other end of the conductive layer in the hole of the intermediate board.
3. The method of claim 1, wherein electrically connecting the chip to the wiring region of the interposer comprises:
and the surface of the chip is provided with metal bumps, and the chip is in reflow soldering with the wiring area through the metal bumps.
4. The method of claim 2, wherein the hole of the interposer penetrates through the substrate, and the electrically connecting the second re-routing layer of the package substrate with the conductive layer in the hole of the interposer comprises: and implanting a first solder ball on one side of the hole back to the wiring area, and electrically connecting the first solder ball with the second re-wiring layer.
5. The method of claim 1, further comprising:
forming a first dielectric layer on the surface of the second rewiring layer opposite to the silicon wafer base layer, and arranging a third opening on the first dielectric layer;
forming a second seed layer on the surface of the first dielectric layer, which is opposite to the silicon wafer base layer;
forming a second mask layer on the surface of the second seed layer, which is opposite to the silicon wafer base layer, and arranging a fourth opening on the second mask layer;
forming a third rewiring layer in the fourth opening;
removing the second mask layer and the second seed layer except the third re-wiring layer;
wherein the second re-wiring layer, the second seed layer, and the third re-wiring layer are electrically connected.
6. The method of claim 5, wherein electrically connecting the second redistribution layer of the package substrate to the conductive layer within the hole of the interposer comprises:
the third redistribution layer of the package substrate is electrically connected to the conductive layer in the hole of the interposer, thereby electrically connecting the second redistribution layer to the conductive layer.
7. The method of claim 1,
the forming the first rewiring layer on the side, opposite to the bonding pad, of the silicon wafer base layer comprises: arranging a first blocking layer on the surface, opposite to the silicon wafer base layer, of the first rewiring layer, and forming a seventh opening on the first blocking layer;
after the chip is electrically connected to the wiring region of the interposer and the second redistribution layer of the package substrate is electrically connected to the conductive layer in the hole of the interposer, the method includes: disposing a second solder ball in the seventh opening; the second solder balls and the first rewiring layer are electrically connected.
8. The method of claim 1,
the forming the first rewiring layer on the side, opposite to the bonding pad, of the silicon wafer base layer comprises: arranging a first blocking layer on the surface, opposite to the silicon wafer base layer, of the first rewiring layer, and forming a seventh opening on the first blocking layer; forming a fourth sub-layer on the surface of the first barrier layer opposite to the silicon wafer base layer; forming a fifth mask layer on the surface of the fourth sub-layer opposite to the silicon wafer base layer, and forming an eighth opening on the fifth mask layer corresponding to the seventh opening; forming an under-ball metal layer within the eighth opening; removing the fifth mask layer and the fourth sublayer except the metal layer under the ball;
after the chip is electrically connected to the wiring region of the interposer and the second redistribution layer of the package substrate is electrically connected to the conductive layer in the hole of the interposer, the method includes: forming a second welding ball at the corresponding position of the under-ball metal layer; the second solder balls, the under-ball metal layer, the fourth sub-layer and the first redistribution layer are electrically connected.
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| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| CN107424969A (en) * | 2016-04-22 | 2017-12-01 | 日月光半导体制造股份有限公司 | Semiconductor package device and method of manufacturing the same |
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| US8115292B2 (en) * | 2008-10-23 | 2012-02-14 | United Test And Assembly Center Ltd. | Interposer for semiconductor package |
| US8975183B2 (en) * | 2012-02-10 | 2015-03-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming semiconductor structure |
| US8963316B2 (en) * | 2012-02-15 | 2015-02-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and method for manufacturing the same |
| JP6029958B2 (en) * | 2012-12-04 | 2016-11-24 | 新光電気工業株式会社 | Wiring board manufacturing method |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| US9917043B2 (en) * | 2016-01-12 | 2018-03-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
| JP6648544B2 (en) * | 2016-02-08 | 2020-02-14 | 三菱電機株式会社 | Semiconductor device |
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| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| CN107424969A (en) * | 2016-04-22 | 2017-12-01 | 日月光半导体制造股份有限公司 | Semiconductor package device and method of manufacturing the same |
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