CN107424917A - A kind of process of optimization CIS UTS device white pixels - Google Patents

Abstract

The present invention proposes a kind of process of optimization CIS UTS device white pixels, comprises the following steps：Semiconductor substrate is provided；Pixel region silicon chip epitaxial layer is injected to by N-type substrate using ion implantation；Carry out active area processing procedure and subsequent technique processing procedure.The process of optimization CIS UTS device white pixels proposed by the present invention, for the higher situation of white pixel point under existing process, pixel region silicon chip epitaxial layer is injected to by N-type using ion implantation, increases pixel region device depth, so as to improve CIS device stabilities, white pixel point is reduced.Wafer EPI types can be changed by the way that ion implanting is simple and effective using the process of the present invention, be not related to other influences, while the present invention can effectively reduce the white pixel point of CIS devices, and do not influence other parameters.

Description

A Process Method for Optimizing White Pixels of CIS-UTS Devices

technical field

The present invention relates to the field of semiconductor integrated circuit manufacture, relate to the manufacturing process of IMP (Implant, ion implantation), and particularly relate to a kind of processing method of optimizing white pixel of CIS-UTS device.

Background technique

Since Bell Laboratories in the United States proposed the concept of solid-state imaging devices in the late 1960s, solid-state image sensors have developed rapidly and become an important branch of sensing technology. It is an indispensable peripheral for personal computer multimedia and a core device in monitoring equipment. In recent years, due to the improvement of integrated circuit design technology and process level, CIS (CMOS IMAGE SENSOR, Complementary Metal Oxide Semiconductor Image Sensor) has inherent advantages such as intra-pixel amplification, column parallel structure, high integration, single power supply and Features such as low-voltage power supply, low cost and low technical threshold have been more widely used. Moreover, the advantages of low cost, single chip, low power consumption and simple design make CIS stand out in the field of low-end pixel products such as security monitoring systems, videophones, camera phones, toys, automobiles and medical electronics.

WP (White Pixel) refers to the number of pixels with a DN value > 64 output by the CIS device under no light conditions. It is an important indicator for evaluating the performance of the CIS device and directly reflects the imaging quality of the device. Therefore, improving the WP performance of CIS devices, that is, reducing WP Count (white pixels) is a long-term goal of the CIS device manufacturing process.

UTS (Ultra thin stack, ultra-thin stacking technology) process is a more advanced process method for CIS devices. The logic device and pixel device are processed on two wafers, and finally the functional device is realized by combining the stacking method. . The advantage of this process is that the logic device and the pixel device do not affect each other, and the performance can be maximized to a higher degree.

In the existing process, the epitaxial layer of the wafer often uses a P-type substrate, and for the device in the pixel area, the deepest N-type implantation defines the depth of the device. In the original process, the median value of WP Count is around 620, and the high value of WP Wafer Edge (wafer edge) is likely to cause yield failure.

Contents of the invention

The invention proposes a process method for optimizing the white pixels of CIS-UTS devices. In view of the high white pixel points in the existing process, the epitaxial layer of the silicon wafer in the pixel area is implanted into an N-type by ion implantation method, so as to increase the size of the device in the pixel area. depth, thereby improving the stability of CIS devices and reducing white pixels.

In order to achieve the above object, the present invention proposes a kind of processing method of optimizing CIS-UTS device white pixel, comprises the following steps:

Provide semiconductor substrates;

The epitaxial layer of the silicon wafer in the pixel area is implanted into an N-type substrate by ion implantation;

Carry out the active area process and subsequent process.

Further, the ion implantation step includes:

Perform hard mask deposition;

Implanting N-type ions P;

The hard mask is removed using a wet process.

Further, the implantation energy of the N-type ions P is 2MKeV˜3MKeV.

Further, the implantation energy of the N-type ions P is 2.25MKeV.

Further, the subsequent process includes:

Perform deep N-well process;

Perform shallow trench isolation process;

The collector buried process is carried out.

The process method for optimizing the white pixels of the CIS-UTS device proposed by the present invention aims at the situation that the white pixels are relatively high under the existing process, and adopts the ion implantation method to implant the epitaxial layer of the silicon wafer in the pixel area into an N type, thereby increasing the device depth in the pixel area , thereby improving the stability of CIS devices and reducing white pixels. The process method of the present invention can simply and effectively change the EPI type of the wafer through ion implantation, without involving other influences, and at the same time, the present invention can effectively reduce the white pixels of the CIS device without affecting other parameters.

Description of drawings

Fig. 1 shows the flow chart of the process method for optimizing the white pixel of CIS-UTS device according to the preferred embodiment of the present invention.

detailed description

Provide the specific embodiment of the present invention below in conjunction with accompanying drawing, but the present invention is not limited to following embodiment. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that the drawings are all in a very simplified form and use imprecise ratios, which are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.

The invention discloses a process method for reducing white pixel points of a CIS device. Since CIS products are mainly used for imaging, white pixels are an important indicator of imaging quality. In the existing 55nm CIS-UTS process technology, P-type EPI (Epitaxy, epitaxial layer) is used as the substrate, and the pixel area product (Pixel Wafer) EPI is now transformed into an N-type substrate by ion implantation, and other processes remain unchanged. In order to achieve the purpose of reducing white pixels.

The application of the present invention in the 55 nanometer CIS-UTS Pixel process is now taken as a specific implementation case to illustrate the mechanism and specific process of the present invention.

Please refer to Fig. 1, Fig. 1 shows the process flow chart of optimizing the white pixel of CIS-UTS device of the preferred embodiment of the present invention. The present invention proposes a process method for optimizing white pixels of a CIS-UTS device, comprising the following steps:

Step S100: providing a semiconductor substrate;

Step S200: using ion implantation to implant the epitaxial layer of the silicon wafer in the pixel region into an N-type substrate;

Step S300: Perform active region manufacturing process and subsequent process manufacturing process.

According to a preferred embodiment of the present invention, the ion implantation step includes:

Perform hard mask deposition;

Implanting N-type ions P;

The hard mask is removed using a wet process.

According to a preferred embodiment of the present invention, the implantation energy of the N-type ions P is 2MKeV˜3MKeV. Further, the implantation energy of the N-type ions P is 2.25MKeV.

In the present invention, the hard mask plate is deposited before the AA process, followed by the implantation of N-type ions P, with an energy of 2.25M, to change the type of EPI and deepen the depth of the pixel device; then use a wet process to remove the hard mask plate ; Then carry out the AA process. The subsequent process is consistent with the original process.

Further, the subsequent process includes:

Perform deep N-well process;

Perform shallow trench isolation process;

The collector buried process is carried out.

In the original process, the definition of the active area (Active Area) is first. The AA process is an important step in defining the active area and the isolation area. It is mainly completed by steps such as deposition, photolithography, etching, and removal of photoresist; N-well process (ADNW) process.

The original data of the product yield test under the new process reflects that the median value of WP Count has decreased from 620 to 480, an increase of about 26%, the value of P97 has decreased from 960 to 500, and the uniformity has increased by about 40%.

In summary, the process method for optimizing the white pixels of the CIS-UTS device proposed by the present invention aims at the high white pixel points in the existing process, and uses ion implantation to implant the epitaxial layer of the silicon wafer in the pixel area into an N-type, increasing The device depth of the large pixel area improves the stability of the CIS device and reduces the white pixels. The process method of the present invention can simply and effectively change the EPI type of the wafer through ion implantation, without involving other influences, and at the same time, the present invention can effectively reduce the white pixels of the CIS device without affecting other parameters.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (5)

1. a process method for optimizing CIS-UTS device white pixel, is characterized in that, comprises the following steps: Provide semiconductor substrates; The epitaxial layer of the silicon wafer in the pixel area is implanted into an N-type substrate by ion implantation; Carry out the active area process and subsequent process. 2. the processing method of optimizing CIS-UTS device white pixel according to claim 1, is characterized in that, described ion implantation step comprises: Perform hard mask deposition; Implanting N-type ions P; The hard mask is removed using a wet process. 3 . The process method for optimizing white pixels of a CIS-UTS device according to claim 1 , wherein the implantation energy of the N-type ions P is 2MKeV˜3MKeV. 4. The process method for optimizing white pixels of a CIS-UTS device according to claim 3, wherein the implantation energy of the N-type ions P is 2.25MKeV. 5. the process method of optimizing CIS-UTS device white pixel according to claim 1, is characterized in that, described follow-up process comprises: Perform deep N-well process; Perform shallow trench isolation process; The collector buried process is carried out.