CN107403764B

CN107403764B - Electronic package

Info

Publication number: CN107403764B
Application number: CN201610375786.4A
Authority: CN
Inventors: 林长甫; 姚进财; 余国华; 黄富堂
Original assignee: Siliconware Precision Industries Co Ltd
Current assignee: Siliconware Precision Industries Co Ltd
Priority date: 2016-05-18
Filing date: 2016-05-31
Publication date: 2020-02-21
Anticipated expiration: 2036-05-31
Also published as: TW201742199A; TWI573232B; CN107403764A

Abstract

An electronic package, comprising: the electronic package comprises a package body, a plurality of conductive elements which are combined with the package body and have an electrical function, and a dummy block which is combined with the package body and has no electrical function, so that the stress of the electronic package is dispersed by the dummy block, the problem of stress concentration of the electronic package can be solved, and the problem of delamination of the electronic package during thermal cycling can be avoided.

Description

Electronic package

Technical Field

The present invention relates to a semiconductor package, and more particularly, to an electronic package capable of increasing the yield of products.

Background

With the rapid development of the electronic industry, electronic products are also gradually moving toward multi-function and high-performance. In order to meet the requirement of miniaturization (miniature) of semiconductor packages, Wafer Level Packaging (WLP) technology is developed.

As shown in fig. 1, the conventional wafer level semiconductor package 1 includes a semiconductor chip 12, a molding compound 13, and a plurality of solder balls 16. The semiconductor chip 12 has an active surface 12a and an inactive surface 12b opposite to each other, the active surface 12a has a plurality of electrode pads 120 thereon and forms a circuit redistribution structure 14, the circuit redistribution structure 14 is electrically connected to the electrode pads 120, and the circuit redistribution structure 14 has an insulating protection layer 15 exposing a portion of the surface of the circuit redistribution structure 14 for bonding the solder balls 16 to the portion of the surface of the circuit redistribution structure 14. The encapsulant 13 is formed on the insulating protection layer 15 of the circuit redistribution structure 14 and the side surface of the semiconductor chip 12.

In addition, the surface of the semiconductor package 1 is defined with a wiring area a and a free area B adjacent to each other, so that the solder balls 16 are located in the wiring area a, and the semiconductor package 1 is soldered to the contacts 90 of a circuit board 9 by the solder balls 16 during the subsequent product assembly.

However, in the semiconductor package 1, the solder balls 16 are located in the wiring area a, so that during thermal cycling (thermal cycling), stress is concentrated in the idle area B, which causes the semiconductor chip 12 (or the redistribution structure 14) to separate from the encapsulant 13, resulting in delamination (delaminating) problem, which results in the semiconductor chip 12 not being electrically connected to the circuit board 9 effectively or the semiconductor package 1 failing to pass reliability test, resulting in poor yield of the product.

Therefore, how to overcome the above-mentioned problems of the prior art has become an issue to be solved.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides an electronic package that can avoid delamination of the electronic package during thermal cycling.

The electronic package of the present invention includes: a package body; a plurality of conductive elements which are combined with the packaging piece body and have an electrical function; and at least one dummy block which is combined with the packaging body and has no electrical function.

In the foregoing electronic package, the package body defines a wiring area and an idle area adjacent to each other, so that the conductive elements are located in the wiring area, and the dummy block is located in the idle area.

In the foregoing electronic package, the dummy block is located outside the package body.

In the electronic package, the conductive element includes a metal bump and/or a solder material.

In the electronic package, the dummy block is a metal block.

In the electronic package, the top plan profile of the dummy block is formed by a straight line, a curved line or a combination of both.

In the electronic package, the package body includes at least one electronic component and a package layer covering the electronic component. The packaging body also comprises a circuit structure arranged on the electronic element and electrically connected with the electronic element and the conductive elements, and the packaging layer also covers the circuit structure and enables the dummy block to be arranged on the packaging layer and the circuit structure. Alternatively, the dummy block is embedded in the package layer and contacts the electronic device, or protrudes from the package layer.

Therefore, in the electronic package of the present invention, the design of the dummy block is mainly used to disperse the stress of the idle area of the electronic package, so that the electronic package can eliminate the stress concentration problem, and avoid the delamination problem, thereby improving the product yield.

Drawings

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package;

fig. 2 is a schematic cross-sectional view of a first embodiment of an electronic package according to the present invention;

FIG. 2' is a schematic view of another embodiment corresponding to FIG. 2;

FIGS. 2A-2C are partial top views of different embodiments of the dummy block of FIG. 2;

FIG. 3A is a schematic cross-sectional view of an electronic package according to a second embodiment of the present invention;

FIG. 3B is a schematic diagram of another embodiment of FIG. 3A;

fig. 4A is a schematic cross-sectional view of an electronic package according to a third embodiment of the invention; and

fig. 4B is a schematic diagram of another embodiment corresponding to fig. 4A.

Description of the symbols

1 semiconductor package 12 semiconductor chip

12a,32a

active side

12b,32b inactive side

120,320 electrode pad 13 packaging colloid

14

line redistribution structure

15,35 insulation protective layer

16

solder ball

2,2 ', 3,3 ', 4,4 ' electronic package

20,30,40 package body 20a surface

21,21 ', 21a,21b,21c dummy blocks 26, 26' conductive elements

260 metal bump 261 solder material

32 electronic component 320', 420 dummy pad

33 encapsulation layer 34 circuit structure

340 dielectric layer 341 line redistribution layer

341' dummy line 9 Circuit Board

90 contact A wiring area

B, B' idle area.

Detailed Description

The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.

It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the present disclosure, and are not used for limiting the conditions of the present disclosure, which will not be technically significant, and any structural modifications, ratio changes or size adjustments should be made within the scope of the present disclosure without affecting the function and the achievable purpose of the present disclosure. In addition, the terms "above" and "an" are used in the present specification for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be made without substantial technical changes.

Fig. 2 is a cross-sectional view of a first embodiment of an electronic package 2 according to the present invention. As shown in fig. 2, the electronic package 2 includes a package body 20, a plurality of conductive elements 26 combined with the package body 20, and at least one dummy block (dummy bump)21 combined with the package body 20.

The Package body 20 is a structure formed by a semiconductor packaging process, such as a Wafer Level Chip Scale Package (WLCSP), a Direct Chip attached Package (DCA), a Multi-Chip Module (MCM), or a three-dimensional integrated circuit (3DIC) Chip stack Package Module.

In the present embodiment, the surface 20a of the package body 20 defines a wiring region a and a dummy region B' adjacent to each other.

The conductive element 26 is disposed on the surface 20a of the package body 20, located in the wiring region a, and electrically connected to the package body 20 to have an electrical function.

In the present embodiment, the conductive element 26 includes a solder material 261 and/or a metal bump 260, for example, the metal bump 260 is a copper bump. In other embodiments, such as the electronic package 2 ' shown in fig. 2 ', the conductive elements 26 ' may also be solder balls.

The dummy block 21 is located in the free area B' and is not electrically connected to the package body 20 (i.e., has no electrical function).

In the present embodiment, the dummy block 21 is located outside the surface 20a of the package body 20.

In addition, the dummy block 21 is a metal block, such as a copper block, and the material of the dummy block 21 and the material of the conductive element 26 may be the same or different.

As shown in fig. 2A to 2C, the top plan profile of the dummy blocks 21a,21B,21C is formed by a straight line (a rectangle as shown in fig. 2B), a curved line (a circle as shown in fig. 2A), or a combination of both, and as shown in fig. 2C, the shape of the dummy block B' (or the dummy block 21C) is not particularly limited.

The electronic package 2,2 'of the present invention disperses the stress generated by the electronic package 2, 2' in the packaging process by the design of the dummy block 21, so that the electronic package 2,2 'can eliminate the problem of stress concentration in the idle region B', thereby avoiding the problem of delamination of the electronic package 2,2 'during thermal cycling, and even if delamination occurs, the dummy block 21 can prevent delamination from spreading or extending, thereby improving the reliability of the electronic package 2, 2' and further improving the product yield.

In addition, the dummy block 21 is located in the idle region B' of the package body 20, so that the dummy block 21 does not occupy the originally predetermined functional area (e.g., the area for routing circuits or disposing electronic components) of the package body 20, and the originally predetermined available area and performance of the package body 20 are not affected.

Fig. 3A and 3B are schematic cross-sectional views of electronic packages 3, 3' according to a second embodiment of the present invention. The difference between the present embodiment and the first embodiment is the structure of the package body 30, so only the differences will be described below, and the description of the same parts will be omitted.

As shown in fig. 3A, the package body 30 is a micro WLCSP including an electronic component 32 and a package layer 33 covering the electronic component 32.

The electronic component 32 is embedded in the package layer 33, and the inactive surface 32b of the electronic component 32 is exposed out of the package layer 33.

In the present embodiment, the electronic component 32 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the electronic component 32 is a semiconductor wafer having an active surface 32a and an inactive surface 32b facing each other, and the active surface 32a has a plurality of electrode pads 320.

In addition, the conductive elements 26 include a solder material 261 and/or a metal bump 260, for example, the metal bump 260 is a copper bump, and the metal bump 260 is disposed on the active surface 32a of the electronic component 32 and protrudes from the package layer 33 to combine with the solder material 261.

The material of the package layer 33 is Polyimide (PI), dry film (dry film), epoxy resin (epoxy) or a package material.

In the present embodiment, the dummy blocks 21 are located in the package body 30, such as embedded in the package layer 33, and the dummy blocks 21 contact the active surface 32a of the electronic component 32. In other embodiments, such as the electronic package 3 'shown in fig. 3B, the dummy block 21' protrudes beyond the package layer 33.

In addition, the dummy blocks 21' and the metal bumps 260 can be fabricated together. As shown in fig. 3B, the active surface 32a of the electronic device 32 has at least one dummy pad 320 '(i.e., an electrode pad without electrical connection or electrical function), and the dummy block 21' and the metal bumps 260 are formed, followed by forming the package layer 33.

The electronic packages 3,3 'of the present invention are designed by the dummy blocks 21, 21' to disperse the stress generated by the electronic packages 3,3 'when forming the package layer 33, so that the stress concentration problem of the electronic packages 3, 3' in the idle region B 'can be solved, thereby avoiding the delamination problem between the package layer 33 and the electronic component 32, so that the circuit board can maintain normal electrical connection with the electronic component 32, and the electronic packages 3, 3' can pass the reliability test, thereby improving the product yield.

In addition, the dummy blocks 21,21 ' are located in the idle area B ' of the package body 30, so that the dummy blocks 21,21 ' do not occupy the originally predetermined functional area (e.g., the wiring area of the electronic device 32) of the package body 30, and the originally predetermined available area and performance of the package body 30 are not affected, i.e., the area where the electronic device 32 is disposed is not affected.

Fig. 4A and 4B are schematic cross-sectional views of electronic packages 4, 4' according to a third embodiment of the present invention. The difference between the present embodiment and the second embodiment is that the package body 40 is additionally provided with the structure of the circuit structure 34, so that only the differences will be described below, and the description of the same parts will be omitted.

As shown in fig. 4A, the circuit structure 34 is disposed on the active surface 32a of the electronic component 32, and the dummy block 21 is disposed on the circuit structure 34.

In the present embodiment, the circuit structure 34 has at least one dielectric layer 340 and a Redistribution layer (RDL) 341 disposed on the dielectric layer 340, and the RDL 341 is electrically connected to the electrode pad 320.

In addition, an insulating passivation layer 35, such as solder mask, may be optionally formed on the circuit structure 34, and a portion of the surface of the redistribution layer 341 is exposed for bonding the conductive elements 26 ', so that the dummy block 21 is disposed on the insulating passivation layer 35, and the electronic package 4 is soldered to a contact of an external device, such as a circuit board (not shown), by the conductive elements 26'.

In the present embodiment, the material of the encapsulation layer 33 and the insulating protection layer 35 may be the same or different.

In addition, as shown in fig. 4B, the active surface 32a may have a plurality of dummy pads 420 (i.e., electrode pads without electrical connection or electrical function), and a dummy line 341 ' (i.e., a line without electrical connection or electrical function) is disposed on the dielectric layer 340 of the circuit structure 34, and then the dummy block 21 ' and the conductive element 26 ' are formed, and then the package layer 33 is formed.

The electronic package 4,4 'of the present invention disperses the stress generated by the thermal cycle (thermal cycle) of the electronic package 4, 4' after the formation of the package layer 33 by the design of the dummy blocks 21,21 ', so that the problem of stress concentration in the idle region B' of the electronic package 4,4 'is eliminated, thereby avoiding the delamination between the package layer 33 and the circuit structure 34 (or the insulating protection layer 35), so that the circuit board can be normally electrically connected to the electronic component 32, and the electronic package 4, 4' can pass the reliability test, thereby improving the yield of products.

In addition, the dummy blocks 21,21 ' are located in the idle region B ' of the package body 40, so the dummy blocks 21,21 ' do not occupy the originally predetermined functional region of the package body 40 (e.g. the region where the circuit structure 34 is disposed or the region where the electronic component 32 is disposed), so that the originally predetermined usable area and performance of the package body 40 are not affected, i.e. the circuit layout space of the package body 40 or the region where the electronic component 32 is disposed is not affected.

In summary, the electronic package of the present invention eliminates the problem of stress concentration by the dummy block, so as to improve the yield of the product, and the originally available area and performance of the electronic package are not affected.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims

1. An electronic package, characterized in that the electronic package comprises:

the packaging piece body is defined with a wiring area and an idle area which are adjacent, and the wiring area surrounds the idle area, wherein the packaging piece body comprises at least one electronic element and a packaging layer for coating the electronic element, the packaging piece body comprises a circuit structure arranged on the electronic element, and the packaging layer also coats the circuit structure;

a plurality of conductive elements, which are combined with the packaging body and have an electrical function, wherein the conductive elements are positioned in the wiring area, and the circuit structure is electrically connected with the electronic element and the conductive elements; and

and at least one dummy block which is combined with the package body and has no electric function, wherein the dummy block is positioned in the idle area.

2. The electronic package of claim 1 wherein the dummy block is located outside the package body.

3. The electronic package according to claim 1, wherein the conductive elements comprise metal bumps and/or solder material.

4. The electronic package of claim 1, wherein the dummy block is a metal block.

5. The electronic package of claim 1, wherein the upper planar profile of the dummy block is formed by straight lines, curved lines, or a combination thereof.

6. The electronic package of claim 1, wherein the dummy block is disposed on the package layer and the circuit structure.

7. The electronic package of claim 1, wherein the dummy block is embedded in the package layer.

8. The electronic package according to claim 7, wherein said dummy block contacts said electronic component.

9. The electronic package of claim 7, wherein the dummy block protrudes through the encapsulation layer.