TWI605544B - Substrate structure and method of fabrication - Google Patents

Description

Substrate structure and its preparation method

The present invention relates to a substrate structure, and more particularly to a semiconductor substrate structure and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. Currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (MCM) ) A flip-chip type package module.

1 is a schematic cross-sectional view of a conventional flip chip type semiconductor package 1. As shown in FIG. 1, a Twisting Interposer (TSI) 10 is provided. The cymbal interposer 10 has a crystallizing side 10a and a transfer side 10b, and a connection between the crystallizing side 10a and the transfer. A plurality of conductive-silicon vias (TSVs) 100 on the side 10b, and a plurality of redistribution layers (RDLs) 101 on the transfer side 10b for the semiconductor wafers 19 having a small pitch The electrode pad 190 is electrically coupled to the crystallizing side 10a by a plurality of solder bumps 102 Then, the solder bumps 102 are coated with the primer 192, and the encapsulant 18 is formed on the germane interposer 10 to cover the semiconductor wafer 19, and the plurality of solder layers 101 are soldered on the circuit redistribution layer 101. The conductive element 103 of the ball is electrically coupled to the pad 170 of the package substrate 17 having a larger pitch, and the conductive elements 103 are covered with the primer 172.

However, in the conventional semiconductor package 1, the crystallizing side 10a and the switching side 10b of the germanium interposer 10 are externally connected to other components (ie, the semiconductor) by a solder structure (ie, the solder bumps 102 and the conductive member 103). The wafer 19 and the package substrate 17), when the solder structure is reflowed to form a sphere, if the pitch between the spheres is too small, bridging may occur, causing a short circuit, causing the cymbal interposer 10 The pitch cannot be reduced, which makes the semiconductor package 1 difficult to meet the requirements of lightness and thinness, and thus the electronic product cannot be miniaturized.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a substrate structure, comprising: a substrate body having opposite first and second surfaces, and having at least one of the first surface in the substrate body a conductive pillar, and the conductive pillar protrudes from the second surface; an insulating layer is formed on the second surface of the substrate body and the conductive pillar, and a portion of the conductive pillar is exposed to the insulating layer; and the electrical conductor And formed on a portion of the area of the conductive pillar that exposes the insulating layer.

In the foregoing substrate structure, the insulating layer is formed with an opening to enable the guiding A portion of the area of the electric column is exposed to the opening. For example, the aperture of the aperture is less than the width of the end face of the conductive post.

In the above substrate structure, the conductive pillar protrudes from the insulating layer to expose an end portion of the conductive pillar to the insulating layer.

The present invention provides a substrate structure, comprising: providing a substrate body having a first surface and a second surface; wherein the substrate body has at least one conductive pillar connected to the first surface, and the conductive The pillar protrudes from the second surface; forming an insulating layer on the second surface of the substrate body and the conductive pillar; forming an opening on the insulating layer to expose a part of the area of the conductive pillar to the opening; and forming A conductive bump is disposed in the opening to electrically connect the conductive bump to the conductive pillar.

In the above method, the aperture of the opening is smaller than the width of the end surface of the conductive post.

The invention further provides a substrate structure, comprising: providing a substrate body having a first surface and a second surface; wherein the substrate body has at least one conductive pillar connected to the first surface, and the conductive The pillar protrudes from the second surface; forming an insulating layer on the second surface of the substrate body and the conductive pillar; removing a portion of the material of the insulating layer to cause the conductive pillar to protrude from the insulating layer; and forming a conductive layer thereon A conductive post protrudes from a portion of the insulating layer to electrically connect the conductive layer to the conductive pillar.

In the above substrate structure and its manufacturing method, the substrate system is a semiconductor plate body.

In the above substrate structure and method of manufacturing the same, a line portion is formed on the first surface of the substrate body.

In the above substrate structure and the manufacturing method thereof, the conductive system is a solder bump or a solder layer, that is, the conductive bump is a solder bump, and the conductive layer is a solder layer.

It can be seen from the above that the substrate structure of the present invention and the manufacturing method thereof mainly protrude from the second surface by the conductive pillar as an external contact of the substrate structure, and the conductive pillars are not bridged during reflowing. The problem is that the spacing between the conductive pillars can be reduced, thereby reducing the volume of the substrate structure to meet the requirements of lightness and thinness.

1‧‧‧Semiconductor package

10‧‧‧矽Intermediary board

10a‧‧‧The crystal side

10b‧‧‧Transfer side

100‧‧‧ Conductive piercing

101,211‧‧‧Line redistribution

102‧‧‧ solder bumps

103‧‧‧Conductive components

17‧‧‧Package substrate

170‧‧‧ solder pads

172,192‧‧‧ 底胶

18‧‧‧Package colloid

19‧‧‧Semiconductor wafer

190‧‧‧electrode pads

2,3‧‧‧Substrate structure

20‧‧‧Substrate body

20a‧‧‧ first surface

20b, 20b’‧‧‧ second surface

200‧‧‧conductive column

200a‧‧‧ end

201‧‧‧Mats

21‧‧‧Line Department

210‧‧‧Dielectric layer

22a‧‧‧First insulation

22b‧‧‧Second insulation

220‧‧‧ openings

23‧‧‧ seed layer

24‧‧‧Electrical bumps

24'‧‧‧ solder balls

30‧‧‧resist

34‧‧‧ Conductive layer

4‧‧‧Electronic devices

40‧‧‧Contacts

9‧‧‧Loading board

91‧‧‧Combination layer

D‧‧‧ aperture

R‧‧‧ face width

1 is a schematic cross-sectional view of a conventional semiconductor package; FIGS. 2A to 2E are schematic cross-sectional views showing a first embodiment of a substrate structure of the present invention; and FIGS. 3A to 3E are substrate structures of the present invention; A schematic cross-sectional view of a second embodiment of the method of manufacture.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. Technology disclosed by the invention The content can be covered. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes.

2A to 2E are schematic cross-sectional views showing a first embodiment of the method of fabricating the substrate structure 2 of the present invention.

As shown in FIG. 2A, a substrate body 20 having a first surface 20a and a second surface 20b opposite to each other is provided, and a conductive pillar 200 having a plurality of first surfaces 20a connected to the substrate body 20 is provided.

In the present embodiment, the substrate body 20 is a semiconductor plate body, such as a Si interposer type.

In addition, the conductive pillars 200 are formed by a through-hole copper plating process to form a through-silicon via (TSV), and the first surface 20a of the substrate body 20 is electrically connected to one of the conductive pillars 200. The circuit portion 21 includes at least one dielectric layer 210 and at least one redistribution layer (RDL) 211 disposed on the dielectric layer 210.

Moreover, the conductive post 200 has a pad portion 201 on the first surface 20a for electrically connecting the redistribution wiring layer 211.

In addition, the substrate body 20 is bonded to the bonding layer 91 of a carrier board 9 with its wiring portion 21.

As shown in FIG. 2B, a portion of the material of the second surface 20b of the substrate body 20 is removed by etching to make the end portion 200a of each of the conductive pillars 200 convex. The second surface 20b' of the substrate body 20 is exited.

As shown in FIG. 2C, a first insulating layer 22a and a second insulating layer 22b are formed on the second surface 20b' of the substrate body 20 and the conductive pillar 200. Then, a plurality of openings 220 are formed on the first and second insulating layers 22a, 22b such that the end portions 200a of the conductive posts 200 are correspondingly exposed to the openings 220.

In the present embodiment, the material of the first insulating layer 22a is tantalum nitride or tantalum oxide, and the material forming the second insulating layer 22b is tetraethyl orthosilicate (TEOS).

Moreover, the aperture D of the opening 220 is smaller than the end surface width R of the conductive post 200.

As shown in FIG. 2D, a seed layer 23 is formed on the second insulating layer 22b and the opening 220 to form a plurality of conductive bumps 24 in each of the openings 220, and each of the conductive layers is formed. The bumps 24 are electrically connected to the conductive pillars 200. In this embodiment, the conductive bumps 24 are solder bumps. As shown in FIG. 2E, the portion of the seed layer 23 that is not covered by the conductive bumps 24 is removed. Thereafter, the conductive bumps 24 can be reflowed to form solder balls 24' for bonding to an electronic device (not shown).

In this embodiment, in the subsequent process, the carrier board 9 and the bonding layer 91 can be removed as needed.

In the manufacturing method of the present invention, the second surface 20b' of the substrate body 20 is protruded by the conductive pillar 200, and the aperture D of the opening 220 is smaller than the end surface width R of the conductive pillar 200, so that the conductive pillar 200 is exposed. The portion of the opening 220 serves as an external contact of the substrate structure 2, and the conductive bump 24 is reflowed. When the conductive pillars 200 are not deformed, the problem of bridging does not occur, so that the spacing between the conductive pillars 200 can be reduced as needed to reduce the volume of the substrate structure 2, thereby meeting the requirements of lightness and shortness. Make electronic products to achieve the goal of miniaturization.

3A to 3E are schematic cross-sectional views showing a second embodiment of the method of fabricating the substrate structure 3 of the present invention. The difference between this embodiment and the first embodiment lies in the manner in which the conductive pillars are exposed to the insulating layer, and other processes and structures are substantially the same, so only the differences will be described below.

As shown in FIG. 3A, the process of FIG. 2B is continued to form a first insulating layer 22a and a second insulating layer 22b on the second surface 20b' of the substrate body 20 and the conductive pillar 200. Next, a resist layer 30 is formed on the second insulating layer 22b.

As shown in FIG. 3B, a portion of the material of the resist layer 30, a portion of the material of the first insulating layer 22a, and a portion of the material of the second insulating layer 22b are removed by, for example, etching, so that the ends of the conductive pillars 200 are formed. The resist layer 30 and the first and second insulating layers 22a, 22b are both protruded from 200a.

The resist layer 30 is removed as shown in FIG. 3C.

As shown in FIG. 3D, a plurality of conductive layers 34 are formed on the exposed end portions 200a of the conductive pillars 200, for example, by coating, that is, the portions of the first and second insulating layers 22a and 22b protrude from the conductive pillars 200. The conductive layer 34 is electrically connected to each of the conductive pillars 200.

In this embodiment, the conductive layer 34 is a solder layer for the subsequent connection process (the carrier plate 9 and the bonding layer 91 can be removed as needed), and the substrate structure 3 is made of the conductive layer 34. Directly coupled to an electronic device 4 The contact 40 is as shown in Fig. 3E.

In the manufacturing method of the substrate structure 3 of the present invention, the first and second insulating layers 22a, 22b are protruded by the conductive pillars 200, so that the exposed end portions 200a of the conductive pillars 200 serve as external contacts of the substrate structure 2. When the conductive layer 34 is reflowed, the exposed end portion 200a of the conductive post 200 is not deformed, so that the problem of bridging does not occur, so the spacing between the conductive posts 200 can be reduced as needed to reduce the The volume of the substrate structure 3 meets the requirements of lightness and thinness, thereby enabling the electronic product to achieve miniaturization.

The present invention further provides a substrate structure 2, 3 comprising: a substrate body 20, a first and second insulating layers 22a, 22b, and a plurality of electrical conductors (ie, the conductive bumps 24 or the conductive layers 34).

The substrate body 20 has a first surface 20a and a second surface 20b opposite to each other, and has a plurality of conductive pillars 200 connected to the first surface 20a in the substrate body 20, and the conductive pillars 200 protrude from the first surface 20a. Two surfaces 20b'.

The first and second insulating layers 22a, 22b are formed on the second surface 20b' of the substrate body 20 and the conductive pillars 200, and the first area of each of the conductive pillars 200 is exposed. Second insulating layers 22a, 22b.

The conductive system is formed on a portion of the area of each of the conductive pillars 200 exposing the first and second insulating layers 22a, 22b.

In one embodiment, the substrate body 20 is a semiconductor body.

In an embodiment, a line portion 21 is formed on the first surface 20a of the substrate body 20.

In one embodiment, the first and second insulating layers 22a, 22b are formed with a plurality of openings 220 to expose the end portions 200a of the conductive posts 200. In each of the openings 220, the aperture D of the opening 220 is smaller than the end face width R of the conductive post 200.

In one embodiment, each of the conductive pillars 200 protrudes from the first and second insulating layers 22a, 22b such that the end portions 200a of the conductive pillars 200 are exposed to the first and second insulating layers 22a, 22b.

In summary, the substrate structure of the present invention is formed by the conductive pillar protruding from the second surface of the substrate structure as an external contact of the substrate structure, and each of the conductive pillars is reflowed. The problem of bridging does not occur, so that when the substrate structure is fabricated, the spacing between the conductive pillars can be reduced, and the volume of the substrate structure can be reduced to meet the requirements of lightness and thinness.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Substrate structure

20‧‧‧Substrate body

20a‧‧‧ first surface

20b’‧‧‧ second surface

200‧‧‧conductive column

21‧‧‧Line Department

22a‧‧‧First insulation

22b‧‧‧Second insulation

220‧‧‧ openings

23‧‧‧ seed layer

24'‧‧‧ solder balls

Claims (16)

A substrate structure includes: a substrate body having opposite first and second surfaces, and having at least one conductive pillar connected to the first surface in the substrate body, wherein the conductive pillar protrudes from the second surface An insulating layer formed on the second surface of the substrate body and the conductive pillar, and exposing the insulating layer to a portion of the conductive pillar; and the electrical conductor is formed on the conductive pillar exposing the insulating layer Part of the area. The substrate structure according to claim 1, wherein the substrate system is a semiconductor plate body. The substrate structure of claim 1, wherein the first surface of the substrate body is formed with a line portion. The substrate structure of claim 1, wherein the conductive system is a solder bump or a solder layer. The substrate structure of claim 1, wherein the insulating layer is formed with an opening to expose a portion of the area of the conductive pillar to the opening. The substrate structure of claim 5, wherein the aperture of the aperture is smaller than the width of the end surface of the conductive pillar. The substrate structure of claim 1, wherein the conductive pillar protrudes from the insulating layer to expose an end of the conductive pillar to the insulating layer. A substrate structure is provided, comprising: providing a substrate body having a first surface and a second surface; wherein the substrate body has at least one conductive pillar connected to the first surface, and the conductive pillar protrudes a second surface; an insulating layer is formed on the second surface of the substrate body and the conductive pillar; an opening is formed in the insulating layer to expose a portion of the conductive pillar to the opening; and the conductive bump is formed The opening is configured to electrically connect the conductive bump to the conductive post. The method of fabricating a substrate structure according to claim 8, wherein the substrate system is a semiconductor plate body. The method of fabricating a substrate structure according to claim 8, wherein a line portion is formed on the first surface of the substrate body. The method of fabricating a substrate structure according to claim 8, wherein the conductive bump is a solder bump. The method of fabricating a substrate structure according to claim 8, wherein the aperture of the opening is smaller than the width of the end surface of the conductive post. A substrate structure is provided, comprising: providing a substrate body having a first surface and a second surface; wherein the substrate body has at least one conductive pillar connected to the first surface, and the conductive pillar protrudes a second surface; forming an insulating layer on the second surface of the substrate body and the conductive pillar; Removing a portion of the material of the insulating layer to cause the conductive pillar to protrude from the insulating layer; and forming a conductive layer on a portion of the conductive pillar protruding from the insulating layer to electrically connect the conductive layer to the conductive pillar. The method of fabricating a substrate structure according to claim 13, wherein the substrate system is a semiconductor plate body. The method of fabricating a substrate structure according to claim 13, wherein a line portion is formed on the first surface of the substrate body. The method of fabricating a substrate structure according to claim 13, wherein the conductive layer is a solder layer.