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CN107369679A - 多重堆叠层叠式封装结构的形成方法 - Google Patents

多重堆叠层叠式封装结构的形成方法 Download PDF

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Publication number
CN107369679A
CN107369679A CN201610621524.1A CN201610621524A CN107369679A CN 107369679 A CN107369679 A CN 107369679A CN 201610621524 A CN201610621524 A CN 201610621524A CN 107369679 A CN107369679 A CN 107369679A
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package
integrated circuit
stack
layer
chip
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李其融
苏安治
陈宪伟
黄立贤
陈威宇
杨天中
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种多重堆叠层叠式封装结构的形成方法。在方法中，形成第一堆叠半导体组件于第一承载晶片上。单体化第一堆叠半导体组件。胶合第一堆叠半导体组件于第二承载晶片。贴合第二半导体组件于第一堆叠半导体组件上。密封第一堆叠半导体组件及第二半导体组件。将电性连接形成于并电性耦接于第一堆叠半导体组件及第二半导体组件。本发明提供的方法，在中间工艺步骤单体化多重堆叠封装并接着再次将其贴合于载板以进一步进行工艺，可减缓最终多重堆叠封装内的翘曲应力。

Description

多重堆叠层叠式封装结构的形成方法
技术领域
本发明实施例是关于一种层叠式封装(package on package，POP)结构，且特别是有关于一种多重堆叠层叠式封装结构的形成方法。
背景技术
在传统整合扇出(Integrated Fan-Out，InFO)工艺中，其中接合了第一组件芯片的顶封装接合于底封装。底封装也可具有封装于其内的组件芯片。通过采用整合扇出工艺，封装的整合度提升。
在现行的整合扇出工艺中，先形成底封装，其包括密封封装胶体于组件芯片及复数穿透成形通孔(through-molding via)。形成重布线路(redistribution lines)以连接组件芯片及穿透成形通孔。接着，通过焊接点接合顶封装于底封装，所述顶封装可包括接合于附加的封装基板的组件芯片。
发明内容
本发明提供一种多重堆叠层叠式封装结构的形成方法，可减缓多重堆叠封装内的翘曲应力、可增加多重堆叠封装的良率且可降低组件封装的高度。
根据本发明的一些实施例，一种方法包括以下步骤。形成第一堆叠半导体组件于第一承载晶片上。单体化第一堆叠半导体组件。胶合第一堆叠半导体组件于第二承载晶片。贴合第二半导体组件于第一堆叠半导体组件上。密封第一堆叠半导体组件及第二半导体组件。将电性连接形成于并电性耦接于第一堆叠半导体组件及第二半导体组件。
基于上述，在中间工艺步骤单体化多重堆叠封装并接着再次将其贴合于载板以进一步进行工艺，可减缓中间多重堆叠封装内的翘曲应力，其可减缓最终多重堆叠封装内的翘曲应力。中间多重堆叠封装的功能也可被测试，使得仅已知良好多重堆叠封装进一部进行工艺。此种测试可增加最终多重堆叠封装的良率。形成半导体组件的承载基板并将其薄化以取代将其移除，可通过避免分离步骤而进一步增加良率。多重堆叠封装可降低最终组件封装的高度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1至图12是根据一实施例所示出的具有多重堆叠芯片的封装的形成的中间阶段的剖面图；
图13是根据另一实施例所示出的具有多重堆叠芯片的封装的剖面图；
图14是根据另一实施例所示出的具有多重堆叠芯片的封装的剖面图；
图15是根据另一实施例所示出的具有多重堆叠芯片的封装的剖面图；
图16至图26是根据一实施例所示出的具有多重堆叠芯片的封装的形成的中间阶段的剖面图；
图27是根据另一实施例所示出的具有多重堆叠芯片的封装的剖面图；
图28是根据一些实施例所示出的具有多重堆叠芯片的封装的平面图。
附图标记说明：
100、204、214、232、304、404、504、604、614、634：集成电路芯片；
102：基板；
104：内连线；
106、206、216、606、616：芯片连接结构；
108：介电材料；
200：第一封装结构；
200a、600a：第一封装区域；
200b、600b：第二封装区域；
202、230、602、632、702：承载基板；
208、218、234、608、618、636：封装体；
210、220、610、620：介电层；
212、222、224、612、622、624：导通孔；
226、242、628、644：切割；
228、302、402、502、630、704、708：多重堆叠封装；
236、638、706、710：重布线结构；
238、640：接垫；
240、642、712：导通连接结构；
300：第二封装结构；
400：第三封装结构；
500：第四封装结构；
600：第五封装结构；
626：薄化工艺；
700：第六封装结构。
具体实施方式
以下发明内容提供用于实施所提供的发明的不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本发明为目的。当然，这些仅仅为实例而非用以限制。举例来说，在以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且也可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明在各种实例中可使用相同的组件符号和/或字母来指代相同或类似的部件。组件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例和/或配置本身之间的关系。
另外，为了易于描述附图中所示出的一个构件或特征与另一组件或特征的关系，本文中可使用例如“在。。。下”、“在。。。下方”、“下部”、“在…上”、“在…上方”、“上部”及类似术语的空间相对术语。除了附图中所示出的定向之外，所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
根据各种实施例提供多重堆叠(multi-stack，MUST)封装及形成此封装的方法。讨论一些实施例的一些差异。在各种视图及所说明的实施例中，“多重堆叠封装”是指其中二或多层级的组件芯片，各密封于一密封材料中，且其间不具有焊接区域。再者，在本文中，组件芯片的具有连接结构的表面是指各组件芯片的前表面，且相对于所述前表面的表面是后表面。根据一些实施例，后表面也是各组件芯片的半导体基板的表面。可根据堆叠以形成封装的芯片层的数量来量测多重堆叠封装。举例来说，具有两芯片层的多重堆叠封装可指称为两层(two-layer，2L)多重堆叠封装。多重堆叠封装的各层包括并列配置的一或多个芯片。
根据本发明的实施例，通过堆叠数层半导体组件而形成最终多重堆叠封装。半导体组件可以是预先形成且在中间工艺步骤中被单体化的较小的多重堆叠封装。在此种实施例中，可通过在垂直方向堆叠数个较小的多重堆叠封装而形成最终多重堆叠封装。举例来说，可通过堆叠两层多重堆叠封装及一层(one-layer，1L)多重堆叠封装而形成三层(three-layer，3L)多重堆叠封装。相较于由单一、整体堆叠工艺形成的多重堆叠封装，由数个较小多重堆叠封装形成最终多重堆叠封装可产出具有较低翘曲的最终封装。较小的多重堆叠封装的形成及单体化可减缓较小的多重堆叠封装中的翘曲，并降低最终封装中的整体翘曲。在一些实施例中，在组装较小的多重堆叠封装及组装仅包括已知良好芯片的已知良好封装之前，先测试较小的多重堆叠封装的功能。在中间阶段测试封装，可通过提供停止不良封装的工艺或重工不良封装的机会以提升整体良率。由数个较小的多重堆叠封装形成最终多重堆叠封装也可降低最终封装的脚位面积(footprint)尺寸，此因一层及两层封装各别的封装布线相较于三层封装的封装布线可较小且较简化。据此，实施例可降低组件封装的扇出率(fan-out ratio)，例如，组件芯片所占据面积相较于扇出芯片所占据面积的比率。
图1是根据一些实施例所示出的集成电路芯片100的剖面图。集成电路芯片100包括基板102、内连线104、芯片连接结构106及介电材料108。集成电路芯片100可以是内存组件，如静态随机存取内存(Static Random Access Memory，SRAM)组件、动态随机存取内存(Dynamic Random Access Memory，DRAM)组件、闪存(flash memory)组件等。集成电路芯片100可以是处理组件，如系统芯片(system-on-chip，SoC)、微控制器(microcontroller)、处理器(processor)等。
基板102具有前表面(如图1中朝上的表面，有时指称为主动侧)及后表面(如图1中朝下的表面，有时指称为被动侧)。基板102可以是半导体(如掺质或未掺质的硅)或绝缘层上有硅(semiconductor-on-insulator，SOI)基板的主动层。基板102可包括其他半导体材料，如锗(germanium)，如包括碳化硅(silicon carbide)、砷化镓(gallium arsenic)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)和/或锑化铟(indium antimonide)的化合物半导体，如包括硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)和/或砷化磷镓铟(GaInAsP)的合金半导体，或如上述的组合。也可采用其他基板，如多层或梯度(gradient)基板。晶体管、二极管、电容、电阻等组件可形成于基板102内和/或基板102上，且可通过内连线104而相连接，所述内连线104例如由基板102上的一或多个介电层内的金属化图案所形成，以形成集成电路。
根据一些实施例，穿孔不延伸穿过基板102。在此种实施例中，用以使集成电路芯片100的导通特征(如内连线104)相互连接的电性连接，可仅位于集成电路芯片100的前表面上。据此，穿孔不需形成于基板102内，从而降低集成电路芯片100的制造成本。
芯片连接结构106可以是导通柱(如包括铜、铝、钨、镍或上述的合金)，并物理且电性地耦接于内连线104。芯片连接结构106例如可由镀层(plating)等而形成。芯片连接结构106电性耦接集成电路芯片100的各集成电路。
介电材料108位于集成电路芯片100的主动侧上，如位于内连线104上。介电材料108侧向地密封芯片连接结构106，且介电材料108侧向地与集成电路芯片100相接。介电材料108可以是聚苯并恶唑纤维(polybenzoxazole，PBO)、聚乙酰胺(polyimide)、苯并环丁烯(Benzocyclobutene，BCB)等聚合物，可以是氮化硅(silicon nitride)等氮化物，可以是氧化硅(silicon oxide)、磷硅酸盐玻璃(PhosphoSilicate Glass，PSG)、硼硅玻璃(BoroSilicate Glass，BSG)、硼磷硅玻璃(Boron-doped PhosphoSilicate Glass，BPSG)等氧化物，或可以是所述的组合，且例如可通过旋转涂布(spin coating)、叠层(lamination)、化学气相沉积法(Chemical Vapor Deposition，CVD)等形成。
图2至图12是根据一些实施例所示出的第一封装结构的形成的中间阶段的剖面图。示出用以分别形成第一封装及第二封装的第一封装区域200a及第二封装区域200b。
在图2中，贴合集成电路芯片204于承载基板202。胶合具有芯片连接结构206的两集成电路芯片204于第一封装区域200a及第二封装区域200b内。在其他实施例中，可胶合更多或更少的集成电路芯片204于各区域。
承载基板202可以是玻璃载板、陶瓷载板等。承载基板202可以是具有圆形上视形状的晶片，以使多个封装能够同时形成于承载基板202上。
集成电路芯片204可相似于集成电路芯片100。在一些实施例中，各集成电路芯片204是单一芯片，如内存芯片。在一些实施例中，各集成电路芯片204是多重堆叠组件，其包括多个芯片，如多个内存芯片。可通过胶(未示出)而胶合集成电路芯片204于承载基板202。所述胶可以是任何适当胶，如环氧化物(epoxy)、晶粒贴合膜(die attach film，DAF)等。所述胶可施加至集成电路芯片204的背侧(如各半导体晶片的背侧)，或可施加至承载基板202的表面上。集成电路芯片204例如通过切割(sawing or dicing)而单体化，且例如利用取放(pick-and-place)工具通过胶而胶合于承载基板202。芯片连接结构206可相似于集成电路芯片100的芯片连接结构106。
在图3中，封装体(encapsulant)208形成于承载基板202上且围绕集成电路芯片204。接着，形成介电层210于集成电路芯片204及封装体208上。接着，导通孔212形成并接触集成电路芯片204的芯片连接结构206。
封装体208可以是封装胶体(molding compound)、环氧化物(epoxy)等，且可通过压缩成型(compression molding)、转注成型(transfer molding)等施加。在固化后，封装体208可经由研磨工艺而暴露集成电路芯片204的芯片连接结构206。在研磨工艺之后，集成电路芯片204及封装体208的顶表面共面。在一些实施例中，可省略研磨，例如若集成电路芯片204已被暴露。
接着，形成介电层210于集成电路芯片204及封装体208上。介电层210可由相同于介电材料108的材料形成。介电层210可通过任何可行的沉积工艺而形成，如旋转涂布、化学气相沉积、叠层等或上述的组合。接着，形成开口(未标示)于介电层210内，以暴露集成电路芯片204的芯片连接结构206。
导通孔212被形成为延伸远离介电层210。作为形成导通孔212的一例，形成种子层(未示出)于介电层210及集成电路芯片204的被暴露的芯片连接结构206上。在一些实施例中，种子层是金属层，其可以是单层或包括由不同材料形成的复数子层的复合层。在一些实施例中，种子层包括钛层及位于钛层上的铜层。例如可利用物理气相沈积(Physical VaporDeposition，PVD)等形成种子层。形成并图案化光刻胶(未示出)于种子层上。光刻胶可通过旋转涂布等形成且可曝光以图案化。光刻胶的图案对应于集成电路芯片204的被暴露的芯片连接结构206。所述图案化通过光刻胶形成开口以暴露种子层。形成导通材料于光刻胶的开口内及种子层的被暴露部分上。导通材料可通过电镀或无电电镀等镀层而形成。导通材料可包括铜、钛、钨、铝等金属。其上未形成导通材料的光刻胶及部分种子层被移除。可通过可行的灰化(ashing)或剥离(stripping)工艺移除光刻胶，如利用氧电浆(oxygen plasma)等。当移除光刻胶，种子层被暴露的部分被移除，如利用可行的蚀刻(etching)工艺，如湿式或干式蚀刻。种子层剩下的部分及导通材料形成导通孔212。
在图4中，贴合具有芯片连接结构216的集成电路芯片214于介电层210。接着，形成封装体218于介电层210上，所数封装体218围绕导通孔212及集成电路芯片214。
例如利用取放工具通过胶(未示出)而胶合集成电路芯片214于介电层210。集成电路芯片214可利用相似于集成电路芯片204的技术及胶来胶合，或可利用不同的技术及胶。置放集成电路芯片214以使各第一封装区域200a及第二封装区域200b包括两个集成电路芯片214。置放集成电路芯片214于第一封装区域200a及第二封装区域200b的各集成电路芯片204的导通孔212之间。换言之，配置各第一封装区域200a及第二封装区域200b以使导通孔212的位置更接近封装区域的侧向边缘并围绕集成电路芯片214。如同集成电路芯片204，集成电路芯片214以相似于集成电路芯片100的方式形成，且可以是内存组件或处理组件。
封装体218可相似于封装体208，且可利用相似或不同的技术形成。在固化后，封装体218可经由研磨工艺以暴露导通孔212及集成电路芯片214。在研磨之后，导通孔212延伸穿过封装体218。此种通孔可指称为穿透成型通孔(through mold vias)。由于穿透成型通孔式形成于封装体内，故其不需形成为穿过基板，如集成电路芯片214。形成穿过基板的通孔比形成穿透成型通孔更昂贵。
在图5中，形成介电层220于集成电路芯片214及封装体218上。接着，形成导通孔222及224为延伸远离介电层220。
可利用相同于介电层210的材料及技术来形成介电层220。接着，形成开口(未示出)于介电层220内，以暴露导通孔212及集成电路芯片214的芯片连接结构216。
形成导通孔222为接触集成电路芯片214的芯片连接结构216。形成导通孔224为接触导通孔212。可通过如镀层工艺形成导通孔222及导通孔224，且其可于同一工艺或不同工艺形成。在实施例中，于同一工艺形成导通孔222及导通孔224，其可以相似于导通孔212的形成方式来形成。在此种实施例中，光刻胶(如上所述)通过对应于导通孔212及集成电路芯片214的芯片连接结构216的图案而在种子层上被图案化。接着，镀层工艺(如上所述)铜时形成导通孔222及导通孔224。
当形成导通孔222及224，可对第一封装区域200a及第二封装区域200b内的芯片进行功能性测试。进行功能性测试以验证通过导通孔212、222及224至集成电路芯片204及214的导通性。进行功能性测试也可验证集成电路芯片204及214的一些功能。通过在工艺中对集成电路芯片204及214进行功能性测试，仅已知良好封装可进一步进行制作。未通过功能性测试的封装可重工或不使用。据此，通过避免第一封装区域200a和/或第二封装区域200b的进一步工艺可节省成本。
在图6中，进行承载基板的移除以将承载基板202从第一封装结构的背侧分离(de-bond)。所述分离可通过如插入于承载基板202与第一封装区域200a及第二封装区域200b之间的离型层(未示出)而完成。在一些实施例中，所述分离包括投射如激光或紫外光的光至离型层以使离型层在热或光之下分解，且可移除承载基板202。在一些实施例中，可在进行所述分离之前翻转第一封装结构并将其置于切割胶带(dicing tape)上。
继续参考图6，通过沿切割线区域的切割226进行单体化工艺，所述切割线区域例如位于相邻的区域(如第一封装区域200a及第二封装区域200b)之间。
图7示出中间的单体化封装，其可来自于第一封装区域200a或第二封装区域200b其中之一。单体化封装也可指多重堆叠封装228。在图2至图7所示例中，多重堆叠封装228包括两芯片层(如集成电路芯片204及214)。相应地，多重堆叠封装228是两层(2L)多重堆叠封装。由于多重堆叠封装228形成为不具有中间焊接层，其相较于传统整合扇出(IntegratedFan-Out，InFO)封装可具有较低的高度。举例来说，多重堆叠封装228可具有小于约150μm的高度h1。
在图8中，再次贴合(re-attach)多重堆叠封装228于承载基板230。胶合多重堆叠封装228的其中一个于各第一封装区域200a及第二封装区域200b。如上所述，多重堆叠封装228是在单体化之前或之后由功能性测试所判断的已知良好封装。
承载基板230可相似于承载基板202。在一些实施例中，承载基板230是承载基板202，例如，承载基板202于后续工艺再利用。可利用例如取放工具通过胶(未示出)而胶合多重堆叠封装228于承载基板230。在一些实施例中，相较于集成电路芯片204置放于承载基板202上，多重堆叠封装228置放为较靠近承载基板230上的另一个。
在图9中，贴合集成电路芯片232于多重堆叠封装228。可利用例如取放工具通过胶(未示出)而胶合集成电路芯片232于介电层220且使集成电路芯片232位于多重堆叠封装228的导通孔222之间。
相较于多重堆叠封装228内的集成电路芯片204及214，集成电路芯片232可以是不同种类的集成电路芯片。举例来说，在一些实施例中集成电路芯片232可以是处理组件，而集成电路芯片204及214可以是内存组件。在一些实施例中集成电路芯片232可以是具有二、三或四层的多重堆叠封装。在此种实施例中，集成电路芯片232可进行功能性测试以确认其是已知良好芯片。
在图10中，封装体234形成于承载基板230上且覆盖多重堆叠封装228及集成电路芯片232。接着，形成前侧重布线结构236于封装体234上，且形成接垫238于前侧重布线结构236上。接着，形成导通连接结构240于接垫238上。
封装体234可以是封装胶体，且可形成为覆盖多重堆叠封装228及集成电路芯片232。在固化之后，封装体234可经由研磨工艺而暴露集成电路芯片232的芯片连接结构及多重堆叠封装228的导通孔(如导通孔222及224)。在研磨工艺之后，集成电路芯片232及封装体234的顶表面共面。在一些实施例中，可省略研磨，例如若集成电路芯片232及导通孔222与224已被暴露。
形成前侧重布线结构236以电性耦接多重堆叠封装228及集成电路芯片232于外部连接结构，如接垫238。应理解，所有图中的前侧重布线结构236是示意。举例来说，前侧重布线结构236实际上可图案化为通过各介电层而彼此分离的复数部分。前侧重布线结构236例如可以是重布线层(redistribution layers，RDLs)，且例如可包括金属走线(或金属线路)及位于下方并连接金属走线的通孔。根据本发明的一些实施例，通过镀层工艺形成重布线层，其中各重布线层包括种子层(未示出)及种子层上的镀层金属材料。可以相同材料或不同材料来形成种子层及镀层金属材料。
形成接垫238于前侧重布线结构236的外侧。接垫238用以耦接导通连接结构240，且可指称为球下金属(under bump metallurgies，UBMs)。在所示的实施例中，通过前侧重布线结构236的介电层内的开口形成接垫238以接触前侧重布线结构236内的金属图案。作为形成接垫238的一例，形成种子层(未示出)于前侧重布线结构236上。在一些实施例中，种子层是金属层，其可以是单层或包括由不同材料形成的复数子层的复合层。在一些实施例中，种子层包括钛层及在钛层上的铜层。可利用例如物理气相沉积法等形成种子层。接着，光刻胶形成并图案化于种子层上。光刻胶可通过旋转涂布等形成且可曝光以图案化。光刻胶的图案对应于前侧重布线结构236的被暴露的金属图案。所述图案化通过光刻胶形成开口以暴露种子层。导通材料可包括铜、钛、钨、铝等金属。接着，其上未形成导通材料的光刻胶及部分种子层被移除。可通过可行的灰化(ashing)或剥离(stripping)工艺移除光刻胶，如利用氧电浆(oxygen plasma)等。当移除光刻胶，种子层被暴露的部分被移除，如利用可行的蚀刻(etching)工艺，如湿式或干式蚀刻。种子层剩下的部分及导通材料形成接垫238。在不同地形成接垫238的实施例中，可采用更多光刻胶及图案化步骤。
形成导通连接结构240于接垫238上。导通连接结构240可以是球栅数组封装(ballgrid array，BGA)连接结构、焊球、金属柱、受控塌陷芯片连接(controlled collapse chipconnection，C4)凸块、微凸块(micro bumps)，化镍钯浸金(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。导通连接结构240可包括导通材料，如焊料、铜、铝、金、镍、银钯钛等，或所述的组合。在一些实施例中，可例如以一般所采用的方法，如蒸镀(evaporation)、电镀(electroplating)、印刷(printing)、焊料转移(solder transfer)、植球(ball placement)等，通过初始形成焊层以形成导通连接结构240。当一层焊料形成于结构上时，可进行回焊以使材料成为所需的凸块形状。在其他实施例中，导通连接结构240是金属柱(如铜柱)，其通过溅镀(sputtering)、印刷、电镀、无电电镀、化学气相沉积等形成。金属柱可以是无焊料且具有实质上垂直的侧壁。在一些实施例中，形成金属覆盖层(未示出)于导通连接结构240顶部。金属覆盖层可包括镍、钛、钛铅、金、银、钯、铟、镍钯金、镍金等，或所述的组合，且可通过镀层工艺形成。
在图11中，进行承载基板的分离以从第一封装结构的背侧分离承载基板230。所述分离可通过所述离型层(未示出)而完成。通过沿切割线区域的切割242进行单体化工艺，所述切割线区域例如位于相邻的区域(如第一封装区域200a及第二封装区域200b)之间。
图12示出单体化后所产生的第一封装结构200，其可来自于第一封装区域200a或第二封装区域200b其中之一。所产生的第一封装结构200是由两层多重堆叠封装(如多重堆叠封装228的其中一个)及另一芯片层(如集成电路芯片232)形成，此两者皆封装为另一多重堆叠封装。从而所产生的封装指称为三层多重堆叠封装，因其包括两层多重堆叠封装及第三组件层。
图13是根据一些实施例示出的第二封装结构300的剖面图。由两层多重堆叠封装302及一个集成电路芯片304形成第二封装结构300。据此第二封装结构300在垂直方向上具有三层芯片，且其因此指称为三层多重堆叠封装。
图14是根据一些实施例示出的第三封装结构400的剖面图。由四个两层多重堆叠封装402及一个集成电路芯片404形成第三封装结构400。据此第三封装结构400在垂直方向上具有五层芯片，且其因此指称为五层多重堆叠封装。
图15是根据一些实施例示出的第四封装结构500的剖面图。由两个两层多重堆叠封装502及附加的两层集成电路芯片504形成第四封装结构500。据此第四封装结构500在垂直方向上具有四层芯片，且其因此指称为四层(four-layer，4L)多重堆叠封装。
应理解，在实施例封装结构中可有附加的层及导通孔。举例来说，重布线层可附加于不同的堆叠芯片层之间。重布线层可形成于例如介电层210和/或介电层220。在此种实施例中，重布线层可连接于芯片的背侧的导通接触或特征。相似于导通孔212、222及224的导通孔也可连接重布线层于外部组件。
也应理解，可形成不同数量的半导体组件于实施例的封装结构内的各堆叠层。举例来说，在图2至图12所示实施例中第一封装结构200的第一层级具有两集成电路芯片204，且第一封装结构200的第二层级具有两集成电路芯片214。在一些实施例中，所述第一层级可包括更多或更少半导体组件。同样地，所述第二层级可包括更多或更少半导体组件。并且，如图13至图15所示，半导体组件可以是多重堆叠封装。可使用任何数量及种类的半导体组件来形成实施例的封装结构的各层级。也应理解，在示出各种封装结构的剖面图中，封装结构的各层级可包括更多的多重堆叠封装或芯片于平面视图。
图16至图26是根据一些实施例示出的第五封装结构的中间阶段信息的剖面图。示出用以分别形成第一封装及第二封装的第一封装区域600a及第二封装区域600b。除了第一封装区域600a及第二封装区域600b使用不同的承载基板材料作为附加的支撑，第一封装区域600a及第二封装区域600b分别相似于前述第一封装区域200a及第二封装区域200b。此实施例的相似于前述实施例的细节将不于此重述。
在图16中，具有芯片连接结构606的集成电路芯片604贴合于承载基板602。承载基板602可以是半导体基板。承载基板602例如可以是基体硅晶片(bulk silicon wafer)、基体锗晶片(bulk germanium wafer)、绝缘层上有硅基板或应变型绝缘层上有硅(strainedsemiconductor-on-insulator，SSOI)基板。
在图17中，封装体608形成于承载基板602上且围绕集成电路芯片604。接着，形成介电层610于集成电路芯片604及封装体608上。接着，导通孔612形成并接触集成电路芯片604的芯片连接结构606。
在图18中，具有芯片连接结构616的集成电路芯片614贴合于介电层610。接着，封装体618形成于介电层610上且围绕导通孔612及集成电路芯片614。
在图19中，形成介电层620于集成电路芯片614及封装体618上。接着，导通孔622及624形成为分别接触芯片连接结构616及导通孔612。可对第一封装区域600a及第二封装区域600b内的芯片进行功能性测试，以验证区域内的芯片的导通性及功能。
在图20中，通过薄化工艺626薄化承载基板602。薄化工艺626例如是背侧研磨。进行薄化工艺626以取代移除承载基板602。接着，通过沿切割线区域的切割628进行单体化工艺，所述切割线区域例如位于相邻的区域(如第一封装区域600a及第二封装区域600b)之间。
图21示出中间单体化封装，其可来自第一封装区域600a或第二封装区域600b。单体化封装也可指称为多重堆叠封装630。在图16-21所示例中，多重堆叠封装630是两层多重堆叠封装。多重堆叠封装630可包括更多层堆叠芯片，使其可为例如三层多重堆叠封装。
在图22中，再次贴合多重堆叠封装630于承载基板632。贴合多重堆叠封装630的其中一个于各第一封装区域600a及第二封装区域600b。如上所述，多重堆叠封装630是经由单体化之前的功能性测试所判断的已知良好封装。承载基板632例如是玻璃。
在图23中，贴合集成电路芯片634于多重堆叠封装630。例如利用取放工具通过胶(未示出)而胶合集成电路芯片634于介电层620，且使集成电路芯片634位于多重堆叠封装630的导通孔622之间。
在图24中，封装体636形成于承载基板632上且覆盖多重堆叠封装630及集成电路芯片634。接着，形成前侧重布线结构638于封装体636上，且形成接垫640于前侧重布线结构638上。接着，形成导通连接结构642于接垫640上。
在图25中，进行承载基板的分离以从第五封装结构的背侧分离承载基板632。所述分离可通过例如所述离型层(未示出)而完成。通过沿切割线区域的切割644进行单体化工艺，所述切割线区域例如位于相邻的区域(如第一封装区域600a及第二封装区域600b)之间。
图26示出单体化后所产生的第五封装结构600，其可来自于第一封装区域600a或第二封装区域600b。所产生的第五封装结构600是由堆叠两层多重堆叠封装(多重堆叠封装630)及第三芯片层(集成电路芯片634)而形成的三层多重堆叠封装。第三芯片层可以是多重堆叠封装，如单层或两层多重堆叠封装。
图27是根据一些实施例示出的第六封装结构700。第六封装结构700包括承载基板702、第一多重堆叠封装704、第一重布线结构706、第二多重堆叠封装708、第二重布线结构710及导通连接结构712。第六封装结构700是利用前述多重堆叠封装技术形成，故具体细节将不再重述。
第一多重堆叠封装704利用相似于图16至图21所示的技术而形成。举例来说，形成第一多重堆叠封装704于硅承载基板上，所述硅承载基板被薄化以取代被移除。由两层级芯片形成第一多重堆叠封装704，其密封并单体化以降低第一多重堆叠封装704内的翘曲应力。第一多重堆叠封装704的第一层级包括两芯片，且第一多重堆叠封装704的第二层级包括两芯片。相应地，第一多重堆叠封装704是两层多重堆叠封装。
第二多重堆叠封装708是利用相似于图2至图7所示的技术而形成。举例来说，形成第二多重堆叠封装708于玻璃承载基板上，所述玻璃承载基板随后被移除。由两层级芯片形成第二多重堆叠封装708，其密封并单体化以降低第二多重堆叠封装708内的翘曲应力。第二多重堆叠封装708的第一层级包括两芯片，且第二多重堆叠封装708的第二层级包括一芯片。相应地，第一多重堆叠封装704是两层多重堆叠封装。形成穿透成型通孔于第二多重堆叠封装708的封装体内，其形成第二重布线结构710及第一多重堆叠封装704和/或第一重布线结构706之间的电性连接。
图28是展示第五封装结构600的扇出率的量测的平面图。扇出率是主动半导体组件所占据面积相较于半导体组件的扇出连接结构所占据面积的比率。使用图27的维度，扇出率依据f＝AB/CD决定。在多重堆叠封装是由多各中间多重堆叠封装产生的实施例中，各个中间多重堆叠封装可具有不同扇出率。
实施例可达成优点。在中间工艺步骤单体化多重堆叠封装并接着再次将其贴合于载板以进一步进行工艺，可减缓中间多重堆叠封装内的翘曲应力，其可减缓最终多重堆叠封装内的翘曲应力。中间多重堆叠封装的功能也可被测试，使得仅已知良好多重堆叠封装进一部进行工艺。此种测试可增加最终多重堆叠封装的良率。形成半导体组件的承载基板并将其薄化以取代将其移除，可通过避免分离步骤而进一步增加良率。多重堆叠封装可降低最终组件封装的高度。举例来说，四层多重堆叠封装可具有约450μm的高度。
根据一实施例，一种方法包括以下步骤。形成第一堆叠半导体组件于第一承载晶片，单体化第一堆叠半导体组件，胶合第一堆叠半导体组件于第二承载晶片，贴合第二半导体组件于第一堆叠半导体组件，密封第二半导体组件及第一堆叠半导体组件，且将电性连接形成于并电性耦接于第一堆叠半导体组件及第二半导体组件。
根据一实施例，一种方法包括以下步骤。胶合复数第一芯片于第一基板的组件区域。形成复数第一穿孔，第一穿孔与第一芯片电性连接。贴合复数第二芯片于第一芯片上，第一穿孔围绕第二芯片。单体化组件区域以形成堆叠组件。贴合堆叠组件于第二基板。提供第三芯片于堆叠组件上。沉积封装体于堆叠组件及第三芯片上。形成重布线层于封装体上，重布线层电性耦接于第一芯片、第二芯片及第三芯片。
根据一实施例，一种组件包括第一堆叠半导体组件、第二堆叠半导体组件、封装体、重布线层及导通孔。第一堆叠半导体组件位于第二堆叠半导体组件上，第一堆叠半导体组件包括复数集成电路芯片。封装体围绕且位于第一堆叠半导体组件及第二堆叠半导体组件上。重布线层位于第一堆叠半导体组件及第二堆叠半导体组件上。导通孔从重布线层延伸至第一堆叠半导体组件及第二堆叠半导体组件。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (1)

1.一种多重堆叠层叠式封装结构的形成方法，包括：
形成第一堆叠半导体组件于第一承载晶片上；
单体化所述第一堆叠半导体组件；
胶合所述第一堆叠半导体组件于第二承载晶片；
贴合第二半导体组件于所述第一堆叠半导体组件上；
密封所述第二半导体组件及所述第一堆叠半导体组件；以及
将电性连接形成于并电性耦接于所述第一堆叠半导体组件及所述第二半导体组件。
CN201610621524.1A 2016-05-12 2016-08-01 多重堆叠层叠式封装结构的形成方法 Pending CN107369679A (zh)

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