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CN113658944B - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN113658944B
CN113658944B CN202110690696.5A CN202110690696A CN113658944B CN 113658944 B CN113658944 B CN 113658944B CN 202110690696 A CN202110690696 A CN 202110690696A CN 113658944 B CN113658944 B CN 113658944B
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China
Prior art keywords
die
package
package assembly
semiconductor
encapsulant
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CN113658944A (zh
Inventor
张丰愿
黄博祥
鲁立忠
李志纯
卢以谦
陈又豪
张克正
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体封装件包括第一封装组件，该第一封装组件包括：第一半导体管芯；第一密封剂，位于第一半导体管芯周围；以及第一再分布结构，电连接至第一半导体管芯。半导体封装件还包括接合至第一封装组件的第二封装组件，其中，第二封装组件包括：第二半导体管芯；散热器，位于第一半导体管芯和第二封装组件之间；以及第二密封剂，位于第一封装组件和第二封装组件之间，其中，第二密封剂具有比散热器低的热导率。本申请的实施例还涉及形成半导体封装件的方法。

Description

半导体封装件及其形成方法
技术领域
本申请的实施例涉及半导体封装件及其形成方法。
背景技术
由于各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速的增长。在大多数情况下，迭代减小最小部件尺寸可以提高集成密度，从而可以将更多组件集成至给定区域中。随着对缩小电子器件的需求的增长，已经出现了对更小且更具创造性的半导体管芯封装技术的需求。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部，以提供高水平的集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上生产增强功能且小的覆盖区的半导体器件。
发明内容
本申请的一些实施例提供了一种半导体封装件，包括：第一封装组件，包括：第一半导体管芯；第一密封剂，位于所述第一半导体管芯周围；以及第一再分布结构，电连接至所述第一半导体管芯；第二封装组件，接合至所述第一封装组件，其中，所述第二封装组件包括第二半导体管芯；散热器，位于所述第一半导体管芯和所述第二封装组件之间；以及第二密封剂，位于所述第一封装组件和所述第二封装组件之间，其中，所述第二密封剂具有比所述散热器低的热导率。
本申请的另一些实施例提供了一种半导体封装件，包括：第一封装组件，包括：第一半导体管芯，包括第一半导体衬底；第一密封剂，位于所述第一半导体管芯周围；以及第一再分布结构，电连接至所述半导体管芯；第二封装组件，接合至所述第一封装组件，其中，所述第二封装组件包括第二半导体衬底上的第二半导体管芯，并且其中，所述第一半导体衬底通过膜直接附接至所述第二半导体衬底；以及第二密封剂，位于所述第一封装组件和所述第二封装组件之间。
本申请的又一些实施例提供了一种形成所述半导体封装件的方法，包括：形成再分布结构，其中，所述再分布结构包括绝缘层中的第一接触焊盘和第二接触焊盘；在所述第二接触焊盘上形成通孔；将第一管芯接合至所述再分布结构，其中，所述第一管芯的介电层接触所述绝缘层，并且其中，所述第一管芯的第三接触焊盘接触所述第一接触焊盘；将散热器附接至所述第一管芯的与所述再分布结构相对的表面；以及将包括第二管芯的封装组件接合至所述通孔，其中，所述散热器位于所述第一管芯和所述封装组件之间。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的集成电路管芯的截面图。
图2至图13示出了根据一些实施例的在用于形成半导体封装件的工艺期间的中间步骤的截面图。
图14A、图14B和图14C示出了根据一些实施例的半导体封装件的截面图。
图15至图19示出了根据一些实施例的在用于形成半导体封装件的工艺期间的中间步骤的截面图。
图20示出了根据一些实施例的半导体封装件的截面图。
图21至图29示出了根据一些实施例的在用于形成封装组件的工艺期间的中间步骤和实现器件堆叠件的截面图。
图30示出了根据一些实施例的半导体封装件的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，封装件包括接合至包括一个或多个IC管芯的集成电路(IC)封装组件的存储器封装组件。在一些实施例中，具有相对较高热导率的散热器设置在存储器封装组件和IC封装组件之间，用于改善散热。例如，散热器可以附接至IC管芯的背侧，并且散热器可以从IC管芯延伸至存储器封装件。在其它实施例中，IC管芯可以直接附接至存储器封装件用于改善散热。因此，在实施例半导体封装件中，热量可以通过散热器或通过将IC管芯直接附接至存储器封装件来有效地从IC管芯散发至散热器。
图1示出了根据一些实施例的集成电路管芯50的截面图。将在随后处理中封装集成电路管芯50以形成集成电路封装件。集成电路管芯50可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。
可以在晶圆中形成集成电路管芯50，该晶圆可以包括在随后步骤中被分割以形成多个集成电路管芯的不同的器件区域。可以根据适用的制造工艺处理集成电路管芯50，以形成集成电路。例如，集成电路管芯50包括半导体衬底52(诸如掺杂或未掺杂的硅)或绝缘体上半导体(SOI)衬底的有源层。半导体衬底52可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用其它衬底，诸如多层或梯度衬底。半导体衬底52具有有时称为前侧的有源表面(例如，在图1中面向上的表面)和有时称为背侧的无源表面(例如，在图1中面向下的表面)。
可以在半导体衬底52的正面处形成器件(由晶体管表示)54。器件54可以是有源器件(例如，晶体管、二极管等)、电容器、电阻器等。层间电介质(ILD)56位于半导体衬底52的正面上方。ILD 56围绕并且可以覆盖器件54。ILD 56可以包括由诸如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等材料形成的一个或多个介电层。
导电插塞58延伸穿过ILD 56以电和物理耦接器件54。例如，当器件54是晶体管时，导电插塞58可以耦接晶体管的栅极和源极/漏极区域。导电插塞58可以由钨、钴、镍、铜、银、金、铝等或它们的组合形成。互连结构60位于ILD 56和导电插塞58上方。互连结构60互连器件54以形成集成电路。互连结构60可以由例如ILD 56上的介电层中的金属化图案形成。金属化图案包括形成在一个或多个低k介电层中的金属线和通孔。互连结构60的金属化图案通过导电插塞58电耦接至器件54。
集成电路管芯50还包括制成与外部连接的焊盘62，诸如铝焊盘。焊盘62位于集成电路管芯50的有源侧上，诸如位于互连结构60中和/或上。一个或多个钝化膜64位于集成电路管芯50上，诸如位于互连结构60和焊盘62的部分上。开口穿过钝化膜64延伸至焊盘62。诸如导电柱(例如，由诸如铜的金属形成)的管芯连接件66延伸穿过钝化膜64中的开口，并且物理和电耦接至相应焊盘62。管芯连接件66可以通过例如镀等形成。管芯连接件66电耦接集成电路管芯50的相应集成电路。
可选地，焊料区域(例如，焊料球或焊料凸块)可以设置在焊盘62上。焊料球可以用于对集成电路管芯50实施芯片探针(CP)测试。可以对集成电路管芯50实施CP测试，以确定集成电路管芯50是否是已知的良好管芯(KGD)。因此，仅封装经过随后处理的是KGD的集成电路管芯50，并且不封装未通过CP测试的管芯。在测试之后，可以在随后处理步骤中去除焊料区域。
介电层68可以(也可以不)位于集成电路管芯50的有源侧上，诸如位于钝化膜64和管芯连接件66上。介电层68横向密封管芯连接件66，并且介电层68与集成电路管芯50横向共末端。最初，介电层68可以掩埋管芯连接件66，从而使得介电层68的最顶面位于管芯连接件66的最顶面之上。在焊料区域设置在管芯连接件66上的一些实施例中，介电层68也可以掩埋焊料区域。可选地，可以在形成介电层68之前去除焊料区域。
介电层68可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等或它们的组合。介电层68可以例如通过旋涂、层压、化学汽相沉积(CVD)等形成。在一些实施例中，在形成集成电路管芯50期间，管芯连接件66通过介电层68暴露。在一些实施例中，管芯连接件66在用于封装集成电路管芯50的随后工艺期间保持掩埋和暴露。暴露管芯连接件66可以去除管芯连接件66上可能存在的任何焊料区域。
在一些实施例中，集成电路管芯50是包括多个半导体衬底52的堆叠器件。例如，集成电路管芯50可以是包括多个存储器管芯的存储器器件，诸如混合存储器多维数据集(HMC)模块、高带宽存储器(HBM)模块等。在这样的实施例中，集成电路管芯50包括通过衬底通孔(TSV)互连的多个半导体衬底52。半导体衬底52的每个可以(或者可以不)具有互连结构60。
图2至图13示出了根据一些实施例的制造具有改善的散热的集成电路封装件的截面图。在图2中，提供载体衬底102，并且在载体衬底102上形成释放层104。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底102可以是晶圆，从而使得可以在载体衬底102上同时形成多个封装件。例如，示出了第一封装区域100A和第二封装区域100B，并且封装一个或更多个集成电路管芯50以在封装区域100A和100B的每个中形成集成电路封装件。完成的集成电路封装件也可以称为集成扇出(InFO)封装件。
释放层104可以由基于聚合物的材料形成，该材料可以与载体衬底102一起从将在随后步骤中形成的上面的结构去除。在一些实施例中，释放层104是基于环氧树脂的热释放材料，当加热时失去其粘合性，诸如光热转换(LTHC)释放涂覆。在其它实施例中，释放层104可以是紫外(UV)胶，当暴露于UV光时其失去粘合性。释放层104可以作为液体分配并且固化，可以是层压在载体衬底102上的层压膜，或者可以是类似物。释放层104的顶面可以是水平的并且可以具有高度的平面性。
在图3中，在释放层104上形成前侧再分布结构122。前侧再分布结构122包括介电层124、128、132和136；以及金属化图案126、130、134和110(包括导电焊盘110A和110B)。金属化图案126、130和134也可以称为再分布层或再分布线。前侧再分布结构122示出为具有四个金属化图案层的实例。可以在前侧再分布结构122中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
作为形成再分布结构122的实例，在释放层104上沉积介电层124。在一些实施例中，介电层124由可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料形成。介电层124可以通过旋涂、层压、CVD等或它们的组合来形成。
然后在介电层124上形成金属化图案126。作为形成金属化图案126的实例，在介电层124上方形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。晶种层可以使用例如PVD等形成。然后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案126。图案化形成穿过光刻胶的开口以暴露晶种层。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀(诸如电镀、化学镀等)来形成。导电材料可以包括金属，如铜、钛、钨、铝等。导电材料和晶种层的下面部分的组合形成金属化图案126。去除光刻胶和晶种层的其上未形成导电材料的部分。光刻胶可以通过可接受的灰化或剥离工艺去除，诸如使用氧等离子体等。一旦去除光刻胶，去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿蚀刻或干蚀刻。
然后可以在金属化图案126和介电层124上沉积介电层128。介电层128可以以类似于介电层124的方式形成，并且可以由与介电层124类似的材料形成。然后可以通过介电层124图案化开口，以暴露下面的金属化图案126。图案化可以通过可接受的工艺来形成，诸如当介电层124是感光材料时通过将介电层124暴露于光或通过使用例如各向异性蚀刻来蚀刻。如果介电层124是感光材料，则可以在曝光之后显影介电层124。
然后形成金属化图案130。金属化图案130包括位于介电层128的主表面上并且沿介电层128的主表面延伸的部分以及延伸穿过介电层128以物理和电耦接金属化图案126的部分。金属化图案130可以以与金属化图案126类似的方式并且由与金属化图案126类似的材料形成。在一些实施例中，金属化图案130具有与金属化图案126不同的尺寸。例如，金属化图案130的导线和/或通孔可以比金属化图案126的导线宽或厚。此外，金属化图案130可以形成为比金属化图案126大的间距。
在金属化图案130和介电层128上沉积介电层132，并且可以图案化介电层132以暴露金属化图案130。介电层132可以以类似于介电层124的方式形成并且图案化，并且可以由与介电层124类似的材料形成。
然后形成金属化图案134。金属化图案134包括位于介电层132的主表面上并且沿介电层132的主表面延伸的部分以及延伸穿过介电层132以物理和电耦接金属化图案130的部分。金属化图案134可以以与金属化图案126类似的方式并且由与金属化图案126类似的材料形成。在一些实施例中，金属化图案134具有与金属化图案126和130不同的尺寸。例如，金属化图案134的导线和/或通孔可以比金属化图案126和130的导线和/或通孔宽或厚。此外，金属化图案134可以形成为比金属化图案130大的间距。
在金属化图案134和介电层132上沉积介电层136，并且可以图案化介电层136以暴露金属化图案134。介电层136可以以类似于介电层124的方式形成，并且可以由与介电层124相同的材料形成。
然后在介电层136的开口中形成金属化图案110。金属化图案110包括延伸穿过介电层136以物理和电耦接至下面的金属化图案134、130和126的导电焊盘110A和110B。
如图3进一步所示，在金属化图案110的导电焊盘110A上形成通孔116。通孔116可以远离再分布结构122的最顶部介电层(例如，介电层136)延伸。作为形成通孔116的实例，在前侧再分布结构122上方(例如，在介电层136和金属化图案110上)形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和钛层上方的铜层。晶种层可以使用例如PVD等形成。可选地，在通孔116不比下面的导电焊盘110A宽的实施例中，可以省略不同的晶种层，并且导电焊盘110A可以用作晶种层。
在晶种层(如果存在)和前侧再分布结构122上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔116。图案化形成穿过光刻胶的开口，以暴露晶种层或导电焊盘110A。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀(诸如电镀、化学镀等)来形成。导电材料可以包括金属，如铜、钛、钨、铝等。去除光刻胶和晶种层的其上未形成导电材料的部分。光刻胶可以通过可接受的灰化或剥离工艺去除，诸如使用氧等离子体等。一旦去除光刻胶，去除晶种层的暴露部分(如果存在)，诸如通过使用可接受的蚀刻工艺，诸如通过湿蚀刻或干蚀刻。晶种层和导电材料的剩余部分形成通孔116。
在图4中，在封装区域100A和100B的每个中接合集成电路管芯50(例如，第一集成电路管芯50A和第二集成电路管芯50B)。在所示的实施例中，多个集成电路管芯50彼此相邻地接合，包括第一封装区域100A和第二封装区域100B的每个中的第一集成电路管芯50A和第二集成电路管芯50B。第一集成电路管芯50A可以是逻辑器件，诸如中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等。第二集成电路管芯50B可以是存储器器件，诸如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储器多维数据集(HMC)模块、高带宽存储器(HBM)模块等。在一些实施例中，集成电路管芯50A和50B可以是相同类型的管芯，诸如SoC管芯。第一集成电路管芯50A和第二集成电路管芯50B可以在相同技术节点的工艺中形成，或者可以在不同技术节点的工艺中形成。例如，第一集成电路管芯50A可以是比第二集成电路管芯50B高级的工艺节点。集成电路管芯50A和50B可以具有不同的尺寸(例如，不同的高度和/或表面积)，或者可以具有相同的尺寸(例如，相同的高度和/或表面积)。虽然两个集成电路管芯50示出为放置在封装区域的每个中，但是更少(例如，一个)或更多数量的集成电路管芯可以设置在衬底102上的封装区域的每个中。
管芯50设置为面向下，从而使得管芯50的前侧面向导电焊盘110B，并且管芯50的背侧背离导电焊盘110B。在一些实施例中，集成电路管芯50以混合接合配置接合至金属化图案110的导电焊盘110B。例如，管芯50的钝化层68可以直接接合至介电层136，并且管芯50的接触焊盘66可以直接接合至导电焊盘110B。在实施例中，钝化层68和介电层136之间的接合可以是氧化物至氧化物接合等。混合接合工艺还通过直接金属至金属接合将管芯50的接触焊盘66直接接合至导电焊盘110B。因此，通过接触焊盘66至接触焊盘110B的物理连接来提供管芯50和前侧再分布结构122之间的电连接。
作为实例，混合接合工艺可以通过对前侧再分布结构122的介电层136和/或管芯50的钝化层68施加表面处理开始。表面处理可以包括等离子体处理。等离子体处理可以在真空环境中实施。在等离子体处理之后，表面处理可以进一步包括可以施加至介电层136和/或管芯50的钝化层68的清洁工艺(例如，利用去离子水冲洗等)。然后，混合接合工艺可以继续以将接触焊盘66与接触焊盘110B对准。下一步，混合接合包括预接合步骤，在该步骤期间，使接触焊盘66与接触焊盘110B物理接触。预接合可以在室温下(例如，在约21℃和约25℃之间)实施。混合接合工艺继续实施退火，例如，在约150℃和约400℃的温度下进行约0.5小时和约3小时之间的持续时间，使得接触焊盘66中的金属(例如，铜)和接触焊盘110B的金属(例如，铜)彼此相互扩散，因此形成直接金属至金属接合。退火可以进一步在钝化层68和介电层136之间形成共价接合。在其它实施例中，其它接合参数和/或方法(例如，焊料接合)也是可能的。
如图4进一步所示，在各个组件上和周围形成密封剂120。在形成之后，密封剂120密封通孔116和集成电路管芯50。密封剂120可以是模塑料、环氧树脂等。可以通过压缩模制、传递模制等施加并且可以在载体衬底102上方形成密封剂120，从而使得掩埋或覆盖通孔116和/或集成电路管芯50。在集成电路管芯50之间的间隙区域中进一步形成密封剂120。可以以液体或半液体形式施加并且然后随后固化密封剂120。
在图5中，对密封剂120实施平坦化工艺以暴露通孔116和管芯50。平坦化工艺也可去除通孔116的材料。在平坦化工艺之后，通孔116、管芯50和密封剂120的顶面在工艺变化内基本共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果已经暴露通孔116和管芯50，则可以省略平坦化。
在图6中，散热器170通过膜168附接至管芯50。散热器170可以由具有相对高热导率的导电材料形成，诸如至少约149W/m*K或至少约380W/m*K。例如，在一些实施例中，散热器170由铜、金刚石、砷化硼、银、硅等制成。已经观察到，当散热器170由具有小于约380W/m*K的热导率的材料形成时，所得封装件中散热不足。散热器170可以使用膜168附接至管芯50的衬底52的背侧。衬底52的背侧可以指与在其上形成有源器件的表面相对的侧。膜168可以是高k聚合物(例如，高k DAF)、通过回流工艺附接的金属(例如，In、Sn等)、热界面材料(TIM)、焊膏等。在所示的实施例中，散热器170的每个具有与管芯50中的相应一个相同的宽度并且与管芯50中的相应一个共末端。在其它实施例中，散热器170可以比管芯50宽或窄，和/或散热器170的侧壁可以从管芯150偏移(见例如图14A至图14C)。此外，多个物理分隔的散热器170可以附接至管芯50的每个(见例如图14A至图14C)。
如图6进一步所示，可以在通孔116上形成金属化图案190。金属化图案190可以使用与上面关于接触焊盘110B所描述的类似的工艺和类似的材料来形成。在各个实施例中，可以在散热器170附接至管芯50之前或之后形成金属化图案190。
因此，在封装区域100A和100B的每个中形成第一封装组件100。第一封装组件100包括集成电路管芯50、密封剂120、通孔116、前侧再分布结构122和金属化图案190。在第一封装组件100的集成电路管芯50上形成散热器170。
在图7中，第二封装组件200通过导电连接件152耦接至第一封装组件100。第二封装组件200中的一个在封装区域100A和100B的每个中耦接以在封装区域的每个上形成集成电路器件堆叠件。在一些实施例中，第二封装组件200可以物理接触散热器170。例如，散热器170可以跨越管芯50和第二封装组件200之间的距离。以这种方式，散热器170可以提供从管芯50至第二封装组件200的散热路径。在其它实施例中，中间层可以设置在散热器170和第二封装组件200之间。例如，导热膜(未明确示出)可以用作散热器170的每个和相应的第二封装组件200之间的缓冲层。在一些实施例中，导热膜可以包括高k聚合物(例如，高kDAF)、通过回流工艺附接的金属(例如，In、Sn等)、TIM、焊膏等。
第二封装组件200包括例如衬底202和耦接至衬底202的一个或多个堆叠的管芯210(例如，210A和210B)。虽然示出了一组堆叠的管芯210(210A和210B)，但是在其它实施例中，多个堆叠的管芯210(每个具有一个或多个堆叠的管芯)可以设置为并排耦接至衬底202的相同表面。衬底202可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用化合物材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化铟镓、这些的组合等。此外，衬底202可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个可选实施例中，衬底202基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。用于芯材料的可选材料包括双马来酰亚胺三嗪(BT)树脂，或者可选地，其它印刷电路板(PCB)材料或膜。诸如味之素积聚膜(ABF)或其它层压板的积聚膜可以用于衬底202。
衬底202可以包括有源和无源器件(未示出)。诸如晶体管、电容器、电阻器、这些的组合等的各种各样的器件可以用于生成用于第二封装组件200的设计的结构和功能要求。器件可以使用任何合适的方法来形成。
衬底202也可以包括金属化层(未示出)和导电通孔208。可以在有源和无源器件上方形成旨在连接各个器件以形成功能电路的金属化层。金属化层可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，具有互连导电材料层的通孔，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双重镶嵌等)形成。在一些实施例中，衬底202基本没有有源和无源器件。
衬底202可以在衬底202的第一侧上具有接合焊盘204，以耦接至堆叠的管芯210，并且可以在衬底202的第二侧上具有接合焊盘206，第二侧与衬底202的第一侧相对，以耦接至导电连接件152。在一些实施例中，接合焊盘204和206通过在衬底202的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成。凹槽可以形成为允许接合焊盘204和206嵌入至介电层中。在其它实施例中，因为可以在介电层上形成接合焊盘204和206，所以省略凹槽。在一些实施例中，接合焊盘204和206包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘204和206的导电材料。导电材料可以通过电化学镀工艺、化学镀工艺、CVD、原子层沉积(ALD)、PVD等或它们的组合来形成。在实施例中，接合焊盘204和206的导电材料是铜、钨、铝、银、金等或它们的组合。
在一些实施例中，接合焊盘204和接合焊盘206是包括三个导电材料层的UBM，诸如钛层、铜层和镍层。材料和层的其它布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置，可以用于形成焊盘204和206。可以用于接合焊盘204和206的任何合适的材料或材料层完全意图包括在本申请的范围内。在一些实施例中，导电通孔208延伸穿过衬底202，并且将接合焊盘204中的至少一个耦接至接合焊盘206中的至少一个。
在所示的实施例中，堆叠的管芯210通过引线接合212耦接至衬底202，但是可以使用其它连接，诸如导电凸块。在实施例中，堆叠的管芯210是堆叠的存储器管芯。例如，堆叠的管芯210可以是存储器管芯，诸如低功率(LP)双倍数据速率(DDR)存储器模块，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或相似的存储器模块。
堆叠的管芯210和引线接合212可以由模制材料214密封。例如，模制材料214可以例如使用压缩模制在堆叠的管芯210和引线接合212上模制。在一些实施例中，模制材料214是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化工艺以固化模制材料214；固化工艺可以是热固化、UV固化等或它们的组合。
在一些实施例中，堆叠的管芯210和引线接合212被掩埋在模制材料214中，并且在固化模制材料214之后，实施诸如研磨的平坦化步骤以去除模制材料214的过量部分，并且为第二封装组件200提供基本平坦的表面。
在形成第二封装组件200之后，第二封装组件200通过导电连接件152、接合焊盘206和金属化图案190机械和电接合至第一封装组件100。在一些实施例中，堆叠的管芯210可以通过引线接合212、接合焊盘204和206、导电通孔208、导电连接件152、金属化图案190、通孔116和前侧再分布结构122耦接至集成电路管芯50A和50B。
在一些实施例中，在衬底202的与堆叠的管芯210相对的侧上形成阻焊剂(未示出)。导电连接件152可以设置在阻焊剂中的开口中，以电和机械耦接至衬底202中的导电部件(例如，接合焊盘206)。阻焊剂可以用于保护衬底202的区域免受外部损坏。
在一些实施例中，导电连接件152在其上形成有环氧树脂焊剂(未示出)，然后回流在第二封装组件200附接至第一封装组件100之后剩余环氧树脂焊剂的至少一些环氧树脂部分。
在图8中，在第一封装组件100和第二封装组件200之间形成围绕导电连接件152和散热器170的密封剂250。可以在第二封装组件200周围进一步形成密封剂250，并且可以在第一封装组件100周围形成密封剂250(未明确示出)。密封剂250可以是模塑料、环氧树脂、模制底部填充物等。在一些实施例中，密封剂250可以具有比散热器170低的热导率。例如，密封剂250可以具有小于约10W/m*K的热导率。因此，散热器170允许穿过密封剂250改善从集成电路管芯50至第二封装组件200的散热。例如，通过包括穿过密封剂250的散热器170，已经观察到工作温度降低约22％或更多。
可以通过压缩模制、传递模制等施加并且可以在第二封装组件200上方形成密封剂250，直至掩埋或覆盖第二封装组件200。在第二封装组件200和下面的第一封装组件100之间的间隙区域中进一步形成密封剂250。可以以液体或半液体形式施加并且然后随后固化密封剂250。在形成密封剂250之后，可以对密封剂250施加平坦化工艺(例如，CMP、研磨等)，直至暴露第二封装组件200。在平坦化工艺之后，第二封装组件200和密封剂250的顶面可以齐平。
在图9中，框架252附接至第二封装组件200。例如，框架252附接至第二封装组件200的与第一封装组件100相对的表面。
在图10中，实施载体衬底剥离以将载体衬底102从前侧再分布结构122(例如，介电层124)脱离(或“剥离”)。根据一些实施例，剥离包括将诸如激光或UV光的光投射在释放层104上，使得释放层104在光的热量下分解，并且可以去除载体衬底102。然后将结构翻转过来。
在图11中，形成用于至前侧再分布结构122的外部连接的UBM 138和导电连接件150。UBM 138具有位于介电层124的主表面上并且沿介电层124的主表面延伸的凸块部分，并且具有延伸穿过介电层124以物理和电耦接金属化图案126的通孔部分。因此，UBM 138电耦接至通孔116和集成电路管芯50。UBM 138可以由与金属化图案126相同的材料并且以相同的工艺形成。在一些实施例中，UBM 138具有与金属化图案110、126、130和134不同的尺寸。
在图11中，在UBM 138上形成导电连接件150。导电连接件150可以是球栅阵列(BGA)连接件、焊料球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件150可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等的或它们的组合。在一些实施例中，导电连接件150通过首先通过蒸发、电镀、印刷、焊料转移、球放置等形成焊料层来形成。一旦在结构上已经形成焊料层，可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件150包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属帽层。金属帽层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
在图12中，通过沿例如第一封装区域100A和第二封装区域100B之间的划线区域锯切来实施分割工艺。锯切将第一封装区域100A与第二封装区域100B分割。所得的、分割的器件堆叠件来自第一封装区域100A或第二封装区域100B中的一个。在一些实施例中，在第二封装组件200耦接至第一封装组件100之后实施分割工艺。在其它实施例中(未示出)，在第二封装组件200耦接至第一封装组件100之前实施分割工艺。
在图13中，然后可以使用导电连接件150将每个分割的第一封装组件100安装至封装衬底300。封装衬底300包括衬底芯302和衬底芯302上方的接合焊盘304。衬底芯302可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用复合材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化铟镓、这些的组合等。此外，衬底芯302可以是SOI衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合。在一个可选实施例中，衬底芯302基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。用于芯材料的可选材料包括双马来酰亚胺三嗪(BT)树脂，或者可选地，其它PCB材料或膜。诸如ABF或其它层压板的积聚膜可以用于衬底芯302。
衬底芯302可以包括有源和无源器件(未示出)。诸如晶体管、电容器、电阻器、这些的组合等的各种各样的器件可以用于生成用于器件堆叠件的设计的结构和功能要求。器件可以使用任何合适的方法来形成。
衬底芯302也可以包括金属化层和通孔(未示出)，接合焊盘304物理和/或电耦接至金属化层和通孔。可以在有源和无源器件上方形成旨在连接各个器件以形成功能电路的金属化层。金属化层可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，具有互连导电材料层的通孔，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双重镶嵌等)形成。在一些实施例中，衬底芯302基本没有有源和无源器件。
在一些实施例中，回流导电连接件150以将第一封装组件100附接至接合焊盘304。导电连接件150将包括衬底芯302中的金属化层的封装衬底300电和/或物理耦接至第一封装组件100。在一些实施例中，在衬底芯302上形成阻焊剂306。导电连接件150可以设置在阻焊剂306中的开口中，以电和机械耦接至接合焊盘304。阻焊剂306可以用于保护衬底202的区域免受外部损坏。
导电连接件150在其上形成有环氧树脂焊剂(未示出)，然后回流在第一封装组件100附接至封装衬底300之后剩余环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物，以减小应力并且保护由回流导电连接件150产生的接头。在一些实施例中，可以在第一封装组件100和封装衬底300之间形成围绕导电连接件150的底部填充物308。底部填充物308可以在附接第一封装组件100之后通过毛细管流动工艺形成，或者可以在附接第一封装组件100之前通过合适的沉积方法形成。
在一些实施例中，无源器件(例如，表面安装器件(SMD)，未示出)也可以附接至第一封装组件100(例如，UBM 138)或附接至封装衬底300(例如，附接至接合焊盘304)。例如，无源器件可以接合至第一封装组件100或封装衬底300的与导电连接件150相同的表面。无源器件可以在将第一封装组件100安装在封装衬底300上之前附接至封装组件100，或者可以在将第一封装组件100安装在封装衬底300上之前或之后附接至封装衬底300。
也可以包括其它部件和工艺。例如，可以包括测试结构以帮助对3D封装或3DIC器件进行验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，它允许测试3D封装或3DIC、使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上实施。此外，本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法共同使用，以增加良率并且降低成本。
因此，形成包括接合至第二封装件组件200和第三封装件组件300的第一封装件组件100的半导体封装件400。一个或多个散热器170设置在第一封装组件100和第二封装组件200之间，以改善从第一封装组件100的管芯50至第二封装组件200的散热。散热器170可以具有相对高热导率，例如，高于第一封装组件100和第二封装组件200之间的密封剂250的热导率。因此，可以在半导体封装件400中实现改善的散热和器件性能。例如，通过包括散热器170，半导体封装件400中的工作温度可以降低22％或更多。
图14A、图14B和图14C分别示出了半导体封装件420、430和440的截面图。半导体封装件420、430和440的每个可以类似于半导体封装件400并且彼此类似，其中相同的参考标号指示使用相同的工艺形成的相同的元件。但是，半导体封装件420、430和440的每个中的第二封装组件200可以进一步包括附接至第二封装组件200的衬底202的散热盖254。散热盖254可以由具有相对高热导率的导电材料制成，诸如铜等，并且散热盖254可以通过粘合剂、热界面材料(TIM)等附接至衬底202的顶面。衬底202将散热器170热连接至散热盖254。因此，热量可以通过散热器170和衬底202从管芯50散发至散热盖254。此外，在封装件420、430和440中，可以仅在第一封装组件100和第二封装组件200之间形成密封剂250，并且密封剂250可以不沿第二封装组件200的侧壁延伸。
图14A的封装件420示出了散热器170具有与管芯50相同的宽度并且与管芯50共末端的实施例。此外，封装件320中的散热器170可以接触衬底202，并且散热器170可以跨越管芯50和衬底202之间的整个距离。
图14B的封装件430示出了散热器170比管芯50窄并且从管芯50偏移的实施例，并且多个散热器170附接至管芯50的每个。例如，在封装件430中，散热器170可以与管芯50的侧壁重叠。此外，封装件330中的散热器170可以接触衬底202，并且散热器170可以跨越管芯50和衬底202之间的整个距离。
图14C的封装件340示出了散热器170具有与管芯50相同的宽度并且与管芯50共末端的实施例。此外，封装件320中的散热器170可以通过密封剂250与衬底202物理分隔开。例如，散热器170可以不附接至封装件200，并且可以在散热器170的顶面和衬底202的底面之间形成密封剂250。虽然散热器170不接触衬底202，但是在密封剂250中包括散热器170仍然改善了第一封装组件100和第二封装组件200之间的散热。
图15至图19示出了根据一些其它实施例的形成半导体封装件450的截面图。封装件450可以类似于图12的封装件400，其中相同的参考标号指示由相同的工艺形成的相同的元件。图15示出了在与上面图4类似的工艺阶段但在形成密封剂120之前的截面图。例如，在图15中，在载体衬底102上形成前侧再分布结构122，在前侧再分布结构122的接触焊盘110A上形成通孔116，并且管芯50接合至前侧再分布结构122的接触焊盘110B。但是，在图15的结构中，管芯50可以比通孔116高并且延伸得更高。
在图16中，在各个组件上和周围形成密封剂120。在形成之后，密封剂120沿通孔116和集成电路管芯50的侧壁延伸。密封剂120可以是模塑料、环氧树脂等。可以通过压缩模制、传递模制等施加并且可以在载体衬底102上方形成密封剂120，从而使得通孔116和/或集成电路管芯50设置在密封剂120中。可以以液体或半液体形式施加并且然后随后固化密封剂120。
在集成电路管芯50之间的间隙区域中形成密封剂120。但是，密封剂120可以沉积为不覆盖通孔116的顶面。例如，在沉积密封剂120之后，通孔116的顶面可以保持暴露，而不对密封剂120施加任何图案化或平坦化工艺。可选地，密封剂120可以沉积为掩埋通孔116，并且可以施加回蚀工艺以暴露通孔116的顶面。在这样的实施例中，回蚀工艺可以是各向同性的。
在一些实施例中，密封剂120可以进一步包括沿管芯50的侧壁的至少上部的圆角。虽然图16示出了密封剂120的顶面处于与通孔116的顶面相同的水平，但是在其它实施例中，密封剂120也可以具有比通孔116的顶面低的顶面。
在图17中，第二封装组件200耦接至第一封装组件100。第二封装组件200中的一个在封装区域100A和100B的每个中耦接，以在第一封装组件100的每个区域中形成集成电路器件堆叠件。例如，第二封装组件200可以通过回流导电连接件152而直接接合至通孔116。第二封装组件200可以类似于上面在图7中描述的那些，并且为简洁起见，省略了第二封装组件200的额外细节。
在封装件450中，管芯50可以通过膜154直接附接至第二封装组件200。膜154可以是高k聚合物(例如，高k DAF)、金属(例如，In、Sn等)、TIM、焊膏等。例如，管芯50的衬底52可以通过膜154附接至第二封装组件200的衬底202。因为衬底52包括半导体材料(例如，具有相对高热导率)，所以通过将它放置在第二封装组件200附近可以促进散热。通过使用具有相对高热导率的材料(例如，膜154)作为管芯50和衬底202之间的界面材料，可以进一步改善散热。例如，已经观察到，通过利用相对高热导率的材料将管芯50直接附接至第二封装组件200，完成的封装件中的工作温度可以降低至少18％。
在图18中，在第一封装组件100和第二封装组件200之间形成围绕导电连接件152的密封剂250。密封剂250可以以与上面在图8中描述的类似的方式并且由与上面在图8中描述的类似的材料形成。密封剂250可以具有比管芯50的衬底52低的热导率。因为管芯50通过膜154直接附接至第二封装组件200，所以密封剂250可以不在管芯50的顶面和衬底202的底面之间直接垂直于管芯50的顶面延伸。因此，可以改善散热。
在图19中，可以实施类似于上面关于图9至图13描述的处理的额外的处理，以分割并且将第一封装组件100和第二封装组件200接合至第三封装组件300。因此，形成包括接合至第二封装组件200和第三封装组件300的第一封装组件100的半导体封装件450。第一封装组件100的管芯50的衬底52直接附接至第二封装组件200的衬底202，以改善从第一封装组件100的管芯50至第二封装组件200的散热。管芯50的衬底52可以具有相对高热导率，例如，高于第一封装组件100和第二封装组件200之间的密封剂250的热导率。因此，可以在半导体封装件450中实现改善的散热和器件性能。例如，半导体封装件450中的工作温度可以降低18％。
图20示出了半导体封装件460的截面图。半导体封装件460可以类似于半导体封装件450，其中相同的参考标号指示使用相同的工艺形成的相同的元件。但是，半导体封装件460中的第二封装组件200可以进一步包括附接至第二封装组件200的衬底202的散热盖254。散热盖254可以由具有高热导率的导电材料制成，诸如铜等，并且散热盖254可以通过粘合剂、热界面材料(TIM)等附接至衬底202的顶面。衬底202将管芯50热连接至散热盖254。此外，在半导体封装件460中，可以仅在第一封装组件100和第二封装组件200之间形成密封剂250，并且密封剂250可以不沿第二封装组件200的侧壁延伸。
图21至图29示出了根据一些其它实施例的形成半导体封装件470的截面图。封装件470可以类似于图12的封装件400，其中相同的参考标号指示由相同的工艺形成的相同的元件。
在图21中，提供载体衬底102，并且在载体衬底102上形成释放层104。可以在释放层104上形成背侧再分布结构106。在所示的实施例中，背侧再分布结构106包括介电层108、金属化图案111(有时称为再分布层或再分布线)、金属化图案110和介电层112。金属化图案110和111可以由与上面描述的金属化图案136类似的工艺和类似的材料形成。背侧再分布结构106是可选的。在一些实施例中，在释放层104上形成没有金属化图案的介电层来代替背侧再分布结构106。
在图22中，通过背侧再分布结构106图案化开口113。例如，可以使用光刻和蚀刻的组合来图案化开口113。开口可以暴露释放层104。
在图23中，在开口113中形成散热器170。散热器170可以例如以与金属化图案110和111类似的方式形成。散热器170可以包括具有相对高热导率的导电材料，诸如铜等。在一些实施例中，散热器170可以具有至少约380W/m*K的热导率。在一些实施例中，散热器170可以形成为覆盖介电层112的顶面，并且平坦化工艺可以用于去除散热器170的过量部分并且暴露金属化图案110。
在图24中，在金属化图案110上形成通孔116。通孔116可以远离背侧再分布结构106的最顶部介电层(例如，介电层112)延伸。通孔116可以使用与上面图3中描述的类似的工艺和类似的材料来形成。
在图24中，集成电路管芯50(例如，第一集成电路管芯50A和第二集成电路管芯50B)通过粘合剂118粘合至散热器170。在封装区域100A和100B的每个中粘合期望类型和数量的集成电路管芯50。在所示的实施例中，多个集成电路管芯50彼此相邻地粘合，包括第一封装区域100A和第二封装区域100B的每个中的第一集成电路管芯50A和第二集成电路管芯50B。第一集成电路管芯50A可以是逻辑器件，诸如中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等。第二集成电路管芯50B可以是存储器器件，诸如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储器多维数据集(HMC)模块、高带宽存储器(HBM)模块等。在一些实施例中，集成电路管芯50A和50B可以是相同类型的管芯，诸如SoC管芯。第一集成电路管芯50A和第二集成电路管芯50B可以在相同技术节点的工艺中形成，或者可以在不同技术节点的工艺中形成。例如，第一集成电路管芯50A可以是比第二集成电路管芯50B高级的工艺节点。集成电路管芯50A和50B可以具有不同的尺寸(例如，不同的高度和/或表面积)，或者可以具有相同的尺寸(例如，相同的高度和/或表面积)。第一封装区域100A和第二封装区域100B中可用于通孔116的间隔可能受到限制，特别是当集成电路管芯50包括具有大覆盖区的器件(诸如SoC)时。当第一封装区域100A和第二封装区域100B具有可用于通孔116的有限间隔时，使用背侧再分布结构106允许改善的互连布置。
粘合剂118位于集成电路管芯50的背侧上，并且将集成电路管芯50粘合至散热器170。粘合剂118可以是高k聚合物(例如，高k DAF)、通过回流工艺附接的金属(例如，In、Sn等)、热界面材料(TIM)、焊膏等。可以将粘合剂118施加至集成电路管芯50的背侧，或者可以施加至背侧再分布结构106的上表面。例如，可以在分割以分隔集成电路管芯50之前将粘合剂118施加至集成电路管芯50的背侧。粘合剂118可以具有相对高热导率，以促进从管芯50至散热器170的散热。
在图25中，在各个组件上和周围形成密封剂120。在形成之后，密封剂120密封通孔116和集成电路管芯50。密封剂120可以是模塑料、环氧树脂等。可以通过压缩模制、传递模制等施加并且可以在载体衬底102上方形成密封剂120，从而使得掩埋或覆盖通孔116和/或集成电路管芯50。在集成电路管芯50之间的间隙区域中进一步形成密封剂120。可以以液体或半液体形式施加并且然后随后固化密封剂120。
对密封剂120实施平坦化工艺以暴露通孔116和管芯连接件66。平坦化工艺也可去除通孔116、介电层68和/或管芯连接件66的材料，直至暴露管芯连接件66和通孔116。在平坦化工艺之后，通孔116、管芯连接件66、介电层68和密封剂120的顶面在工艺变化内基本共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果已经暴露通孔116和/或管芯连接件66，则可以省略平坦化。
在图26中，在密封剂120、通孔116和集成电路管芯50上方形成前侧再分布结构122。前侧再分布结构122包括介电层124、128、132和136；以及金属化图案126、130和134。金属化图案也可以称为再分布层或再分布线。前侧再分布结构122示出为具有三个金属化图案层的实例。可以在前侧再分布结构122中形成更多或更少的介电层和金属化图案。前侧再分布结构122可以使用图3中描述的工艺和/或材料来形成。
在图27中，形成UBM 138和导电连接件150用于至前侧再分布结构122的外部连接。UBM 138具有位于介电层136的主表面上并且沿介电层136的主表面延伸的凸块部分，并且具有延伸穿过介电层136以物理和电耦接金属化图案134的通孔部分。因此，UBM 138电耦接至通孔116和集成电路管芯50。UBM 138可以由与金属化图案126相同的材料形成。在一些实施例中，UBM 138具有与金属化图案126、130和134不同的尺寸。
在UBM 138上形成导电连接件150。导电连接件150可以是球栅阵列(BGA)连接件、焊料球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件150可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等的或它们的组合。在一些实施例中，导电连接件150通过首先通过蒸发、电镀、印刷、焊料转移、球放置等形成焊料层来形成。一旦在结构上已经形成焊料层，可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件150包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属帽层。金属帽层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。因此，形成包括背侧再分布结构106、散热器170、通孔116、管芯50、密封剂120、前侧再分布结构122、UBM 138和导电连接件150的第一封装组件100。
在图28中，实施载体衬底剥离以将载体衬底102从背侧再分布结构106(例如，介电层108)脱离(或“剥离”)。根据一些实施例，剥离包括将诸如激光或UV光的光投射在释放层104上，使得释放层104在光的热量下分解，并且可以去除载体衬底102。
进一步在图28中，穿过介电层108形成开口115，以暴露金属化图案111的部分。开口115可以例如使用激光钻孔、蚀刻等形成。
随后，第二封装组件200以与上面关于图7描述的类似的方式附接至第一封装组件100。例如，导电连接件延伸穿过介电层108中的开口，以将第一封装组件100的金属化图案111电连接至第二封装组件200。散热器170可以设置在第一封装件100的管芯50和第二封装组件200的衬底202之间，以改善从管芯50至第二封装组件200的散热。
可以实施额外的处理(例如，类似于关于图8、图12和图13描述的处理)以到达图29的封装件470。封装件470可以包括形成在第一封装组件100的背侧再分布结构106内的散热器170。通过将散热器170放置在管芯50和第二封装组件200之间，可以改善散热和器件性能。
图30示出了根据一些可选实施例的半导体封装件480的截面图。半导体封装件480类似于半导体封装件400，其中相同的参考标号指示由相同的工艺形成的相同的元件。但是，半导体封装件480中的管芯50以堆叠配置彼此直接接合。在一些实施例中，管芯50A可以通过上面描述的混合接合工艺直接接合至管芯50B。例如，管芯50A的钝化层68A可以利用电介质至电介质接合直接接合至管芯50B的钝化层68B，并且管芯50A的管芯连接件66A可以利用金属至金属接合直接接合至管芯50B的管芯连接件66B。此外，管芯50B可以包括延伸穿过管芯50B的衬底52的衬底通孔(TSV)70。例如，TSV 70可以使用混合接合配置直接接合至前侧再分布层122的接触焊盘110B。
管芯50A和50B热连接至封装件480中的散热器170。例如，散热器170可以通过膜168直接附接至管芯50A的衬底52A。此外，可以在管芯50B的导电连接件66B上形成热通孔172，并且热通孔172可以将管芯50B热连接至散热器170。在一些实施例中，热通孔172由与通孔116类似的材料并且以类似的工艺形成。在一些实施例中，热通孔172可以是不电连接至管芯50A和50B中的任何有源器件的伪通孔。因此，可以通过热连接至管芯50A和50B的散热器170在封装件480中实现散热。热量也可以通过前侧再分布结构122从管芯50B消散。
根据一些实施例，封装件包括接合至包括一个或多个IC管芯的集成电路(IC)封装组件的存储器封装组件。在一些实施例中，具有相对较高热导率的散热器设置在存储器封装组件和IC封装组件之间，用于改善散热。例如，散热器可以附接至IC管芯的背侧，并且散热器可以从IC管芯延伸至存储器封装件。在其它实施例中，IC管芯可以直接附接至存储器封装件用于改善散热。因此，在实施例半导体封装件中，热量可以通过散热器或通过将IC管芯直接附接至存储器封装件来有效地从IC管芯散发至散热器。
在一些实施例中，半导体封装件包括第一封装组件，该第一封装组件包括：第一半导体管芯；第一密封剂，位于第一半导体管芯周围；以及第一再分布结构，电连接至第一半导体管芯。半导体封装件还包括接合至第一封装组件的第二封装组件，其中，第二封装组件包括：第二半导体管芯；散热器，位于第一半导体管芯和第二封装组件之间；以及第二密封剂，位于第一封装组件和第二封装组件之间，其中，第二密封剂具有比散热器低的热导率。可选地，在一些实施例中，散热器具有至少149W/m*K的热导率。可选地，在一些实施例中，散热器接触第二封装组件的衬底。可选地，在一些实施例中，第二密封剂在散热器的顶面和第二封装组件的衬底的底面之间延伸。可选地，在一些实施例中，散热器通过膜附接至第一半导体管芯的半导体衬底。可选地，在一些实施例中，膜包括高k聚合物、铟、锡、热界面材料(TIM)或焊膏。可选地，在一些实施例中，第二散热器设置在第一半导体管芯和第二封装组件之间，并且其中，第二密封剂位于散热器和第二散热器之间。可选地，在一些实施例中，半导体封装件还包括：散热盖，附接至第二封装组件的衬底的顶面，其中，第一封装组件附接至第二封装组件的衬底的底面。可选地，在一些实施例中，第二密封剂设置为沿第二封装组件的侧壁。
在一些实施例中，半导体封装件包括第一封装组件，该第一封装组件包括：第一半导体管芯，包括第一半导体衬底；第一密封剂，位于第一半导体管芯周围；以及第一再分布结构，电连接至半导体管芯。半导体封装件还包括：第二封装组件，接合至第一封装组件，其中，第二封装组件包括第二半导体衬底上的第二半导体管芯，并且其中，第一半导体衬底通过膜直接附接至第二半导体衬底；以及第二密封剂，位于第一封装组件和第二封装组件之间。可选地，在一些实施例中，第二密封剂具有比第一半导体衬底低的热导率。可选地，在一些实施例中，膜包括高k聚合物、铟、锡、热界面材料(TIM)或焊膏。可选地，在一些实施例中，半导体封装件还包括：导电通孔，位于第一密封剂中，其中，第一半导体管芯比通孔延伸得更高。可选地，在一些实施例中，第二密封剂在第一半导体管芯的顶面下方延伸。
在一些实施例中，方法包括：形成再分布结构，其中，再分布结构包括绝缘层中的第一接触焊盘和第二接触焊盘；在第二接触焊盘上形成通孔；将第一管芯接合至再分布结构，其中，第一管芯的介电层接触绝缘层，并且其中，第一管芯的第三接触焊盘接触第一接触焊盘；将散热器附接至第一管芯的与再分布结构相对的表面；以及将包括第二管芯的封装组件接合至通孔，其中，散热器位于第一管芯和封装组件之间。可选地，在一些实施例中，方法还包括：在第一密封剂中密封通孔和第一管芯。可选地，在一些实施例中，方法还包括：在散热器周围以及在第一管芯和封装组件之间分配第二密封剂，其中，散热器具有比第二密封剂高的热导率。可选地，在一些实施例中，方法还包括：在散热器的顶面和封装组件的底面之间分配第二密封剂。可选地，在一些实施例中，接合封装组件包括使散热器与封装组件接触。可选地，在一些实施例中，将散热器附接至第一管芯的与再分布结构相对的表面包括：利用膜将散热器附接至第一管芯的表面，并且其中，膜包括高k聚合物、铟、锡、热界面材料(TIM)或焊膏。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体封装件，包括：
第一封装组件，包括：
第一半导体管芯；
第一密封剂，位于所述第一半导体管芯周围；
第一再分布结构，电连接至所述第一半导体管芯；以及
接触焊盘，位于所述第一密封剂与所述第一再分布结构相对的表面上；
第二封装组件，接合至所述第一封装组件，其中，所述第二封装组件包括第二半导体管芯，其中，所述第二封装组件直接接合至所述接触焊盘；散热器，位于所述第一半导体管芯和所述第二封装组件之间，其中，所述散热器通过膜附接至所述第一半导体管芯的半导体衬底；以及
第二密封剂，位于所述第一封装组件和所述第二封装组件之间，其中，所述第二密封剂具有比所述散热器低的热导率，其中，所述第一半导体管芯的半导体衬底与所述膜之间的界面与所述接触焊盘和所述第一密封剂之间的界面齐平。
2.根据权利要求1所述的半导体封装件，其中，所述散热器具有至少149W/m*K的热导率。
3.根据权利要求1所述的半导体封装件，其中，所述散热器接触所述第二封装组件的衬底。
4.根据权利要求1所述的半导体封装件，其中，所述第二密封剂在所述散热器的顶面和所述第二封装组件的衬底的底面之间延伸。
5.根据权利要求1所述的半导体封装件，其中，所述散热器与所述膜之间的界面比所述第二密封剂与所述第一密封剂之间的界面更靠近所述第二封装组件。
6.根据权利要求5所述的半导体封装件，其中，所述膜包括高k聚合物、铟、锡、热界面材料或焊膏。
7.根据权利要求5所述的半导体封装件，其中，第二散热器设置在所述第一半导体管芯和所述第二封装组件之间，并且其中，所述第二密封剂位于所述散热器和所述第二散热器之间。
8.根据权利要求1所述的半导体封装件，还包括：散热盖，附接至所述第二封装组件的衬底的顶面，其中，所述第一封装组件附接至所述第二封装组件的所述衬底的底面。
9.根据权利要求1所述的半导体封装件，其中，所述第二密封剂设置为沿所述第二封装组件的侧壁。
10.一种半导体封装件，包括：
第一封装组件，包括：
第一半导体管芯，包括第一半导体衬底；
第一密封剂，位于所述第一半导体管芯周围；以及
第一再分布结构，电连接至所述半导体管芯；
第二封装组件，接合至所述第一封装组件，其中，所述第二封装组件包括第二半导体衬底上的第二半导体管芯，并且其中，所述第一半导体衬底通过膜直接附接至所述第二半导体衬底；以及
第二密封剂，位于所述第一封装组件和所述第二封装组件之间；以及
导电通孔，完全穿过所述第一密封剂延伸，其中，所述第一密封剂的面向所述第二封装组件的表面包括弯曲部分，所述弯曲部分从所述半导体衬底的顶表面的第一水平连续延伸至所述导电通孔的顶表面的第二水平，所述第一水平高于所述第二水平。
11.根据权利要求10所述的半导体封装件，其中，所述第二密封剂具有比所述第一半导体衬底低的热导率。
12.根据权利要求10所述的半导体封装件，其中，所述膜包括高k聚合物、铟、锡、热界面材料或焊膏。
13.根据权利要求10所述的半导体封装件，还包括：导电通孔，位于所述第一密封剂中，其中，所述第一半导体管芯比所述通孔延伸得更高。
14.根据权利要求10所述的半导体封装件，其中，所述第二密封剂在所述第一半导体管芯的顶面下方延伸。
15.一种形成半导体封装件的方法，包括：
形成再分布结构，其中，所述再分布结构包括绝缘层中的第一接触焊盘和第二接触焊盘；
在所述第二接触焊盘上形成通孔；
将第一管芯接合至所述再分布结构，其中，所述第一管芯的介电层接触所述绝缘层，并且其中，所述第一管芯的第三接触焊盘接触所述第一接触焊盘；
在第一密封剂中密封所述通孔和所述第一管芯；
在所述通孔上方形成接触焊盘；
将散热器通过膜附接至所述第一管芯的与所述再分布结构相对的表面；以及
将包括第二管芯的封装组件接合至所述通孔上方的所述接触焊盘，其中，所述散热器位于所述第一管芯和所述封装组件之间，其中，所述第一管芯的顶表面和所述膜的底表面之间的界面与所述接触焊盘的底表面和所述第一密封剂的顶表面之间的界面齐平。
16.根据权利要求15所述的方法，还包括：在形成所述通孔和接合所述第一管芯之后，在第一密封剂中密封所述通孔和所述第一管芯。
17.根据权利要求15所述的方法，还包括：在所述散热器周围以及在所述第一管芯和所述封装组件之间分配第二密封剂，其中，所述散热器具有比所述第二密封剂高的热导率。
18.根据权利要求17所述的方法，还包括：在所述散热器的顶面和所述封装组件的底面之间分配所述第二密封剂。
19.根据权利要求15所述的方法，其中，接合所述封装组件包括使所述散热器与所述封装组件接触。
20.根据权利要求15所述的方法，其中，将所述散热器附接至所述第一管芯的与所述再分布结构相对的表面包括：利用膜将所述散热器附接至所述第一管芯的表面，并且其中，所述膜包括高k聚合物、铟、锡、热界面材料或焊膏。
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