CN107294888B - Equalization enhancement module, demodulation system and equalization enhancement method - Google Patents
Equalization enhancement module, demodulation system and equalization enhancement method Download PDFInfo
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Abstract
本发明涉及一种等化增强模块,包含有一乘法单元,用来将多个等化信号乘以一缩放系数,以取得多个缩放信号;一判断单元,耦接于该乘法单元,用来判断该多个缩放信号是否位于一特定区域,产生多个判断结果;一比例计算单元,耦接于该判断单元,用来根据该多个判断结果,计算一区内比例,其中该区内比例相关于该多个缩放信号位于该特定区域的一比例;以及一系数计算单元,耦接于该比例计算单元,用来根据该区内比例,计算该缩放系数。
The present invention relates to an equalization enhancement module, comprising a multiplication unit, for multiplying a plurality of equalization signals by a scaling coefficient to obtain a plurality of scaling signals; a determination unit, coupled to the multiplication unit, for determining whether the plurality of scaling signals are located in a specific area, and generating a plurality of determination results; a ratio calculation unit, coupled to the determination unit, for calculating an intra-area ratio according to the plurality of determination results, wherein the intra-area ratio is related to a ratio of the plurality of scaling signals located in the specific area; and a coefficient calculation unit, coupled to the ratio calculation unit, for calculating the scaling coefficient according to the intra-area ratio.
Description
技术领域technical field
本发明涉及一种等化增强模块、解调制系统以及等化增强方法,尤指一种可改善最小均方差均衡器的等化增强模块、解调制系统以及等化增强方法。The present invention relates to an equalization enhancement module, a demodulation system and an equalization enhancement method, in particular to an equalization enhancement module, a demodulation system and an equalization enhancement method which can improve the minimum mean square error equalizer.
背景技术Background technique
数字通讯系统已广泛地应用于手机、数字视频转换盒(Set-Top Box,STB)、数字电视棒、无线网卡等数字通讯装置中。一般来说,数字通讯系统包含调制(Modulation)系统以及解调制(Demodulation)系统,调制系统将欲传输的位(Bits)调制成为传送符元并传送至通道中再由解调制系统接收接收信号以进行解调制;解调制系统所接收的一接收信号y可表示为y=hs+n,其中s代表调制系统产生的传送符元,h代表信道响应,n代表噪声。解调制系统接收道接收信号后,利用包含于解调制系统的一均衡器以消除通道对传送符元的影响。Digital communication systems have been widely used in digital communication devices such as mobile phones, digital video converter boxes (Set-Top Box, STB), digital TV sticks, and wireless network cards. Generally speaking, a digital communication system includes a modulation (Modulation) system and a demodulation (Demodulation) system. The modulation system modulates the bits to be transmitted into transmitted symbols and transmits them to the channel, and then the demodulation system receives the received signal to Perform demodulation; a received signal y received by the demodulation system can be expressed as y=hs+n, where s represents the transmitted symbol generated by the modulation system, h represents the channel response, and n represents the noise. After the demodulation system receives the channel received signal, an equalizer included in the demodulation system is used to eliminate the influence of the channel on the transmitted symbols.
在已知技术中,强制归零均衡器(Zero Forcing Equalizer)为复杂度低的均衡器,其将接收信号y乘以信道响应的倒数(记为h-1),强制归零均衡器的输出信号xZF可表示为xZF=h-1y=s+h-1n,如此一来,强制归零均衡器即可消除通道对传送符元的影响。然而,当通道响应小时,强制归零均衡器具有噪声增强(Noise Enhancement)的问题。为了避免强制归零均衡器所造成噪声增强的效应,最小均方差均衡器(Minimum Mean Square ErrorEqualizer,MMSE Equalizer)已成为解调制系统中常见的解决方案,最小均方差均衡器系将接收信号y乘以其中及分别代表传送符元及噪声的能量,而最小均方差均衡器的输出信号xMMSE可表示为如此一来,无论通道响应或强或弱,当接收信噪比(Received Signal-to-Noise Ratio,Received SNR)够高,即接收信号能量远大于噪声能量时,可近似于h-1,最小均方差均衡器可近似于强制归零均衡器。In the known technology, a zero-forcing equalizer (Zero Forcing Equalizer) is a low-complexity equalizer, which multiplies the received signal y by the inverse of the channel response (denoted as h -1 ), and the output of the forcing-to-zero equalizer is The signal x ZF can be expressed as x ZF =h -1 y = s+h -1 n, so that the forced-to-zero equalizer can eliminate the effect of the channel on the transmitted symbols. However, when the channel response is small, the forced-zero equalizer has the problem of noise enhancement. In order to avoid the effect of noise enhancement caused by the forced-to-zero equalizer, Minimum Mean Square Error Equalizer (MMSE Equalizer) has become a common solution in demodulation systems. The minimum mean square error equalizer multiplies the received signal y by by in and represent the energy of transmitted symbols and noise, respectively, and the output signal x MMSE of the minimum mean square error equalizer can be expressed as In this way, no matter whether the channel response is strong or weak, when the received signal-to-noise ratio (Received Signal-to-Noise Ratio, Received SNR) is high enough, the received signal energy is much larger than the noise energy hour, can be approximated by h -1 , the minimum mean square error equalizer can be approximated by a forced-zero equalizer.
然而,当噪声能量较强时,最小均方差均衡器会造成其输出信号xMMSE的能量减小,反而降低解调制系统的符元判断精准度,即最小均方差均衡器的输出信号xMMSE的能量减小会导致解调制系统的符元错误率(Symbol Error Rate,SER)及相应的位错误率(BitError Rate,BER)上升,反而降低解调制系统的系统效能。However, when the noise energy When it is strong, the minimum mean square error equalizer will cause the energy of its output signal x MMSE to decrease, but it will reduce the symbol judgment accuracy of the demodulation system, that is, the reduction of the energy of the output signal x MMSE of the minimum mean square error equalizer will lead to The symbol error rate (SER) of the demodulation system and the corresponding bit error rate (BitError Rate, BER) of the demodulation system increase, which reduces the system performance of the demodulation system.
因此,已知技术实有改善的必要。Therefore, there is a need for improvement in the known technology.
发明内容SUMMARY OF THE INVENTION
因此,本发明的主要目的即在于提供一种等化增强模块、解调制系统以及等化增强方法,以改善已知技术的缺点。Therefore, the main purpose of the present invention is to provide an equalization enhancement module, a demodulation system and an equalization enhancement method, so as to improve the shortcomings of the known technology.
本发明揭示一种等化增强模块,包含有一乘法单元,用来将多个等化信号(Equalized Signal)乘以一缩放系数(Scaling Coefficient),以取得多个缩放信号(Scaled Signal);一判断单元,耦接于该乘法单元,用来判断该多个缩放信号是否位于一特定区域,产生多个判断结果;一比例计算单元,耦接于该判断单元,用来根据该多个判断结果,计算一区内比例,其中该区内比例相关于该多个缩放信号位于该特定区域的一比例;以及一系数计算单元,耦接于该比例计算单元,用来根据该区内比例,计算该缩放系数。The present invention discloses an equalization enhancement module, comprising a multiplication unit for multiplying a plurality of equalized signals by a scaling coefficient to obtain a plurality of scaled signals; a judgment a unit, coupled to the multiplication unit, used for judging whether the plurality of scaling signals are located in a specific area, and generating a plurality of judgment results; a ratio calculation unit, coupled to the judgment unit, used for according to the plurality of judgment results, calculating an intra-scale ratio, wherein the intra-scale ratio is related to a ratio at which the plurality of zoom signals are located in the specific area; and a coefficient calculation unit coupled to the scale calculation unit for calculating the intra-scale ratio according to the intra-scale ratio zoom factor.
本发明另揭示露一种解调制(Demodulation)系统,包含有一等化模块,用来对多个接收信号进行等化,以产生多个等化信号;一符元判断模块;以及一等化增强模块,耦接于这些化模块与该符元判断模块之间,这些化增强模块包含有一乘法单元,用来将该多个等化信号乘以一缩放系数,以取得多个缩放信号;一判断单元,耦接于该乘法单元,用来判断该多个缩放信号是否位于一特定区域,产生多个判断结果;一比例计算单元,耦接于该判断单元,用来根据该多个判断结果,计算一区内比例;以及一系数计算单元,耦接于该比例计算单元,用来根据该区内比例,计算该缩放系数;其中,该符元判断模块对该多个缩放信号进行解调制。The present invention further discloses a demodulation system, comprising an equalization module for equalizing a plurality of received signals to generate a plurality of equalized signals; a symbol judging module; and an equalization enhancement a module, coupled between the UL modules and the symbol judgment module, the UL enhancement modules include a multiplication unit for multiplying the plurality of equalization signals by a scaling factor to obtain a plurality of scaling signals; a judgment a unit, coupled to the multiplication unit, used for judging whether the plurality of scaling signals are located in a specific area, and generating a plurality of judgment results; a ratio calculation unit, coupled to the judgment unit, used for according to the plurality of judgment results, calculating a scale within an area; and a coefficient calculating unit coupled to the scale calculating unit for calculating the scaling coefficient according to the scale within the area; wherein the symbol determination module demodulates the plurality of scaled signals.
本发明另揭示一种等化增强方法,包含有将多个等化信号乘以一缩放系数,以取得多个缩放信号;判断多个缩放信号是否位于一特定区域,产生多个判断结果;根据该多个判断结果,计算一区内比例,其中该区内比例相关于该多个缩放信号位于该特定区域的一比例;以及根据该区内比例,计算该缩放系数。The present invention further discloses an equalization enhancement method, which includes multiplying a plurality of equalization signals by a scaling factor to obtain a plurality of scaled signals; judging whether the plurality of scaled signals are located in a specific area, and generating a plurality of judgment results; The plurality of determination results are used to calculate an in-area ratio, wherein the in-area ratio is related to a ratio of the plurality of zoom signals in the specific area; and the zoom coefficient is calculated according to the in-area ratio.
附图说明Description of drawings
图1为本发明实施例一解调制系统的示意图。FIG. 1 is a schematic diagram of a demodulation system according to an embodiment of the present invention.
图2为本发明实施例一等化增强模块的示意图。FIG. 2 is a schematic diagram of an equalization enhancement module according to an embodiment of the present invention.
图3为本发明实施例一比例计算单元的示意图。FIG. 3 is a schematic diagram of a proportional calculation unit according to an embodiment of the present invention.
图4为本发明实施例一系数计算单元的示意图。FIG. 4 is a schematic diagram of a coefficient calculation unit according to an embodiment of the present invention.
图5为多个等化信号的星座图。FIG. 5 is a constellation diagram of a plurality of equalized signals.
图6为多个缩放信号的星座图。FIG. 6 is a constellation diagram of a plurality of scaled signals.
图7为一帧的示意图。FIG. 7 is a schematic diagram of one frame.
图8为本发明实施例一解调制系统的示意图。FIG. 8 is a schematic diagram of a demodulation system according to
图9为本发明实施例一等化增强模块的示意图。FIG. 9 is a schematic diagram of an equalization enhancement module according to an embodiment of the present invention.
符号说明Symbol Description
1 解调制系统1 Demodulation system
10 等化增强模块10 Equalization Enhancement Module
12 等化模块12 Equalization Modules
14 符元判断模块14 Symbolic judgment module
200 乘法单元200 Multiplication Units
202 判断单元202 Judgment unit
204、304 比例计算单元204, 304 proportional calculation unit
206、406 系数计算单元206, 406 Coefficient calculation unit
300 平均单元300 average units
80 等化增强流程80 Equalization Enhancement Process
800~810 步骤800~810 steps
90 等化增强模块90 Equalization Enhancement Module
902 处理单元902 processing unit
904 储存单元904 storage unit
908 程序代码908 program code
y1~yn 接收信号y 1 to yn received signal
x1~xn 等化信号x 1 ~ x n equalized signal
gx1~gxn 缩放信号gx 1 to gx n scaled signal
AD1、AD2 加法器AD1, AD2 adder
D1、D2 缓存器D1, D2 registers
Data 数据子帧Data data subframe
FR 帧FR frame
Header 标头子帧Header subframe
MUX 多任务器MUX multitasker
MP1、MP2 乘法器MP1, MP2 Multiplier
Ik、Ik+1 区内比例Proportion within I k , I k+1
IR 特定比例IR specific ratio
R0 特定区域R 0 specific area
SB 减法器SB subtractor
gk、gk+1 缩放系数g k , g k+1 scaling factor
hitk 判断结果hit k judgment result
α 平均系数α Average coefficient
μ 调整系数μ adjustment factor
具体实施方式Detailed ways
请参考图1,图1为本发明实施例一解调制系统1的示意图。解调制系统1可为一特殊应用集成电路(Application-Specific Integrated Circuit,ASIC),其包含一等化模块12、一等化增强模块10以及一符元判断模块14。解调制系统1自一信道中接收多个接收信号,等化模块12用来对该多个接收信号进行等化,以产生多个等化信号(EqualizedSignal),等化增强模块10将该多个等化信号乘以一缩放系数(Scaling Coefficient),以产生多个缩放信号(Scaled Signal)至符元判断模块14,符元判断模块14即可对该多个缩放符元进行解调制(Demodulation)。其中,等化模块12可为一最小均方差均衡器(MinimumMean Square Error Equalizer,MMSE Equalizer)。详细来说,于一第1时间区间至一第n时间区间中,解调制系统1分别由等化模块12接收到接收信号y1~yn,而等化模块12接收到接收信号y1~yn后分别对接收信号y1~yn进行等化,而产生等化信号x1~xn。等化增强模块10可根据等化信号x1~xn-1(即于第n时间区间前等化增强模块10所接收来自等化模块12的输出信号),产生缩放系数g1~gn,并将等化信号x1~xn分别乘以缩放系数g1~gn,以产生缩放信号gx1~gxn。符元判断模块14即可对缩放信号gx1~gxn进行解调制。Please refer to FIG. 1 , which is a schematic diagram of a
具体来说,于第1时间区间时,等化增强模块10可预先设定缩放系数g1为1,缩放信号gx1即为等化信号x1本身(即gx1=x1)。于第2时间区间时,等化增强模块10可根据等化信号x1产生缩放系数g2,并将等化信号x2乘以缩放系数g2以产生缩放信号gx2为gx2=g2x2。以此类推,于第n时间区间时,等化增强模块10可根据等化信号x1~xn-1产生缩放系数gn,并将等化信号xn乘以缩放系数gn以产生缩放信号gxn为gxn=gnxn。Specifically, in the first time interval, the
需注意的是,因等化模块12为最小均方差均衡器,当噪声能量强时,其输出信号(即等化信号x1~xn)的能量比其对应的接收信号y1~yn的能量小(即|xk|2<|yk|2)。为了避免因等化信号x1~xn的能量较小而导致对应于解调制系统1的符元错误率或位错误率上升,等化增强模块10所产生的缩放系数g1~gn系用来补偿等化模块12(即最小均方差均衡器)所造成的能量缩减,以进一步改善系统效能。It should be noted that since the
关于等化增强模块10产生缩放系数g2~gn(缩放系数g1已预先设定为1)的操作细节,请进一步参考图1,图2为等化增强模块10的示意图。如图2所示,等化增强模块10包含一乘法单元200、一判断单元202、一比例计算单元204以及一系数计算单元206。于第1时间区间至第n时间区间中,等化增强模块10自等化模块12分别接收等化信号x1~xn,乘法单元200分别将等化信号x1~xn乘以缩放系数g1~gn,以取得缩放信号gx1~gxn。判断单元202耦接于乘法单元200,用来判断缩放信号gx1~gxn的对应星座点是否位于一特定区域R,以产生判断结果hit1~hitn。比例计算单元204耦接于判断单元202,用来根据判断结果hit1~hitn,计算区内比例I1~In,其中区内比例I1~In相关于缩放信号gx1~gxn-1位于特定区域R的比例。系数计算单元206耦接于比例计算单元204,用来根据区内比例I1~In,计算缩放系数g1~gn,并将缩放系数g1~gn传递回乘法单元200,使得于第n时间区间时,乘法单元200可将等化信号xn乘以缩放系数gn,以产生缩放信号gxn至符元判断模块14,符元判断模块14即可对缩放信号gxn进行解调制。For details of the operation of the
详细来说,于第k时间区间中,判断单元202判断缩放信号gxk的对应星座点是否位于特定区域R,若缩放信号gxk位于特定区域R,判断单元202输出对应于缩放信号gxk的判断结果hitk为1;反之,若缩放信号gxk不位于特定区域R,判断单元202输出对应于缩放信号gxk的判断结果hitk为0。判断单元202判断缩放信号gxk之对应星座点是否位于特定区域R的方式并未有所限,于一实施例中,判断单元202可判断缩放信号gxk的一同相成份(In-phaseComponent)与一正交成份(Quadrature Component)是否于一特定范围,若缩放信号gxk的同相成份与正交成份于特定范围,判断单元202判断缩放信号gxk位于特定区域R且输出判断结果hitk为1;反之,判断单元202判断缩放信号gxk不位于特定区域R且输出判断结果hitk为0。举例来说,当接收信号y1~yn具有以四位相位偏移调制(Quadrature Phase ShiftKeying,QPSK)的符元(Symbol)信号时,判断单元202可判断缩放信号gxk的同相成份的一绝对值(记为|Re{gxk}|)是否小于一特定值d,并判断缩放信号gxk的正交成份的一绝对值(记为|Im{gxk}|)是否小于特定值d,当|Re{gxk}|小于特定值d且|Im{gxk}|小于特定值d时,判断单元202判断缩放信号gxk位于特定区域R且输出判断结果hitk为1;反之,判断单元202输出判断结果hitk为0。判断单元202产生判断结果hit1~hitn,并将判断结果hit1~hitn传递至比例计算单元204。In detail, in the kth time interval, the
比例计算单元204可根据判断结果hit1~hitn并利用一递归平均(RecursiveAverage)方式,计算区内比例I1~In。请参考图3,图3为本发明实施例一比例计算单元304的示意图。比例计算单元304可用来实现比例计算单元204,其包含有一多任务器MUX以及一平均单元300,多任务器MUX可耦接于判断单元202,用来接收判断单元202所产生的判断结果hit1~hitn。以判断结果hit1~hitn中一判断结果hitk为例,当判断结果hitk为1时,多任务器MUX输出一信号S为一平均系数α;当判断结果hitk为0时,多任务器MUX输出该信号为0。换句话说,多任务器MUX所输出的信号S可表示为αhitk。The
另一方面,平均单元300可根据平均系数α以及判断结果hit1~hitn,计算区内比例I1~In,具体来说,平均单元300包含有一乘法器MP1、一加法器AD1以及一缓存器D1,加法器AD1耦接于多任务器MUX,缓存器D1耦接于加法器AD1,乘法器MP1耦接于加法器AD1与缓存器D1之间。以下以第k时间区间与第k+1时间区间为例进行说明,于第k时间区间时,缓存器D1的输出为一区内比例Ik(对应至暂存区内比例),乘法器MP1将区内比例Ik乘以一系数为(1-α)后产生一相乘结果R1,并将相乘结果R1传递至加法器AD1,其中相乘结果R1可表示为R1=(1-α)Ik。加法器AD1将信号S与相乘结果R1相加以取得一相加结果R2,相加结果R2可表示为R2=αhitk+(1-α)Ik,相加结果R2即为区内比例Ik+1。另外,比例计算单元304将相加结果R2/区内比例Ik+1储存于缓存器D1中,使得于第k+1时间区间时,缓存器D1即可输出区内比例Ik+1,换句话说,比例计算单元304的平均单元300用来实现Ik+1=αhitk+(1-α)Ik,其中整数k可为1到n-1的正整数。如此一来,比例计算单元304于第1时间区间至第n-1时间区间接收到判断结果hit1~hitn-1后,即可根据判断结果hit1~hitn-1分别于第1时间区间至第n时间区产生区内比例I1~In,其中区内比例I1可预先设定为一特定值。同时,于第1时间区间至第n时间区间中,比例计算单元304将所产生的区内比例I1~In传递至系数计算单元206。On the other hand, the averaging
系数计算单元206可于第1时间区间至第n时间区间中分别判断区内比例I1~In是否大于一特定比例IR,以计算缩放系数g2~gn,使得区内比例渐趋近于(收敛至)特定比例IR。以于第k时间区间所收到的区内比例Ik为例,当区内比例Ik大于特定比例IR时,系数计算单元206计算缩放系数gk+1为缩放系数gk(对应至暂存缩放系数)增加一第一特定值Δg1(即gk+1=gk+Δg1);反之,当区内比例Ik小于特定比例IR时,系数计算单元206计算缩放系数gk+1为缩放系数gk减去一第二特定值Δg2(即gk+1=gk-Δg2),其中第一特定值Δg1与第二特定值Δg2皆大于零。The
具体来说,请参考图4,图4为本发明实施例一系数计算单元406的示意图。系数计算单元406可用来实现系数计算单元206,其包含有一减法器SB、一乘法器MP2、一加法器AD2以及一缓存器D2。减法器SB耦接于比例计算单元204以接收比例计算单元204所产生的区内比例,乘法器MP2耦接于减法器SB,加法器AD2耦接于乘法器MP2与缓存器D2之间,且缓存器D2还将输出回馈至加法器AD2。同样地,以下以第k时间区间与第k+1时间区间为例进行说明,于第k时间区间时,减法器SB接收比例计算单元204所产生的区内比例Ik,减法器SB将区内比例Ik减去特定比例IR,产生一相减结果R3,相减结果R3可表示为R3=Ik-IR。乘法器MP2将相减结果R3(即Ik-IR)乘以一调整系数μ,即产生一相乘结果R4并将相乘结果R4传递至加法器AD2,其中相乘结果R4可表示为R4=μ(Ik-IR),此时(即于第k时间区间中)缓存器D2的输出为缩放系数gk(对应至暂存缩放系数),而加法器AD2将相乘结果R4与缩放系数gk相加,以产生一相加结果R5,相加结果R5可表示为R5=gk+μ(Ik-IR),相加结果R5即为缩放系数gk+1。另外,系数计算单元406将相加结果R5/缩放系数gk+1储存于缓存器D2中,使得于第k+1时间区间时,缓存器D2即可输出缩放系数gk+1,换句话说,系数计算单元406用来实现gk+1=gk+μ(Ik-IR),其中整数k可为1到n-1的正整数。如此一来,系数计算单元406于第1时间区间至第n-1时间区间接收到区内比例I1~In-1,并分别计算缩放系数g2~gn(其中缩放系数g1预先设定为1),使得区内比例收敛至特定比例IR。Specifically, please refer to FIG. 4 , which is a schematic diagram of a
如此一来,等化增强模块10可产生缩放系数,以补偿等化模块12(即最小均方差均衡器)所造成的能量缩减。请参考图5及图6,图5为等化模块12所输出的多个等化信号的之星座图,图6等化增强模块10所产生的多个缩放信号的星座图。因等化模块12造成能量缩减,多个等化信号位于一特定区域R0的一比例为52%,若直接对等化模块12所输出的多个等化信号进行解调制,将导致符元错误率或位错误率升高。相比之下,透过等化增强模块10所产生的缩放系数,可使多个缩放信号的星座点向外散开,多个缩放信号位于特定区域R0的一比例降低为25%,对化增强模块10所产生的缩放系数进行解调制,可降低符元错误率或位错误率,提升解调制系统1的效能。In this way, the
另一方面,解调制系统1可用来对一帧(Frame)FR进行解调制。详细来说,帧FR可包含一标头子帧Header以及一数据子帧Data,如图7所示。帧FR可由一传送端传送至一通道中,解调制系统1可自信道接收对应于帧FR的接收信号y1~yN,其中接收信号y1~yn可对应于标头子帧Header而接收信号yn+1~yN可对应于数据子帧Data。解调制系统1可依照上述方式根据接收信号y1~yn产生缩放系数gn(即最后更新的缩放系数),并根据缩放系数gn对其后续对应于数据子帧Data的接收信号yn+1~yN进行解调。如此一来,即可更准确地解调制出帧FR所包含的信息,以提升系统效能。On the other hand, the
关于等化增强模块产生缩放信号的操作流程,可进一步归纳为一等化增强流程80,请参考图8,图8为本发明实施例等化增强流程80的示意图。等化增强流程80可由一等化增强模块来执行,其包含以下步骤:The operation flow of the equalization enhancement module for generating the scaling signal can be further summarized as a first
步骤800:开始。Step 800: Start.
步骤802:将等化信号x1~xn-1乘以一缩放系数g,以取得缩放信号gx1~gxn-1。Step 802 : Multiply the equalized signals x 1 ˜x n-1 by a scaling factor g to obtain the scaling signals gx 1 ˜gx n-1 .
步骤804:判断缩放信号gx1~gxn-1之对应星座点是否位于特定区域R,产生判断结果hit1~hitn-1。Step 804 : Determine whether the corresponding constellation points of the scaling signals gx 1 ˜gx n-1 are located in the specific region R, and generate determination results hit 1 ˜hit n-1 .
步骤806:根据判断结果hit1~hitn-1,计算一区内比例In,其中区内比例In相关于缩放信号gx1~gxn-1位于特定区域R的比例。Step 806 : Calculate an intra-area ratio In according to the judgment results hit 1 ˜hit n-1 , wherein the intra-area ratio In is related to the ratio of the scaling signals gx 1 ˜gx n -1 in the specific area R.
步骤808:根据区内比例In,调整缩放系数g。Step 808: Adjust the scaling factor g according to the intra-area ratio I n .
步骤810:结束。Step 810: End.
于等化增强流程80中,缩放系数g的系数值可随时间变化而不同,即缩放系数g的系数值于第1时间区间至第n时间区间可分别为缩放系数g1~gn。另外,于步骤806中,等化增强模块可利用递归平均方式计算区内比例In,即计算区内比例In为Ik+1=αhitk+(1-α)Ik,除此之外,等化增强模块亦可直接计算区内比例In为 亦符合本发明的要求。In the
另外,于步骤808中,等化增强模块可判断区内比例In是否大于特定比例IR,当区内比例In大于特定比例IR时,等化增强模块计算缩放系数g为一暂存缩放系数g-1增加第一特定值Δg1(即g=g-1+Δg1);当区内比例In小于特定比例IR时,等化增强模块计算缩放系数为暂存缩放系数g-1减去第二特定值Δg2(即gk+1=gk-Δg2)。除此之外,等化增强模块亦可计算缩放系数g为g=g-1+μ(In-IR),亦符合本发明的要求。其余等化增强流程80之操作细节,可参考前述相关段落,于此不再赘述。In addition, in
另一方面,等化增强模块不限于以特殊应用集成电路来实现,请参考图9,图9本发明实施例一等化增强模块90的示意图,等化增强模块90包含一处理单元902及一储存单元904。前述等化增强流程80可编译成一程序代码908并储存于储存单元904中,以指示处理单元902执行等化增强流程80。其中,处理单元902可为一中央处理器(CPU)、一数字信号处理器(Digital Signal Processor,DSP)或是一微处理器(Microprocessor),而不在此限,储存单元904可为一只读式内存(read-only memory,ROM)或是一非挥发性内存(non-volatile memory,例如,一电子抹除式可复写只读存储器(electrically erasableprogrammable read only memory,EEPROM)或一闪存(flash memory)),而不在此限。On the other hand, the equalization enhancement module is not limited to be implemented by special application integrated circuits. Please refer to FIG. 9 , which is a schematic diagram of an
需注意的是,前述实施例用以说明本发明的概念,本领域具通常知识者当可据以做不同的修饰,而不限于此。举例来说,前述实施例是以接收信号y1~yn为具有四位相位偏移调制(QPSK)的符元信号为例进行说明,而本发明不限于此,接收信号y1~yn亦可具有正交振幅调制(Quadrature Amplitude Modulation,QAM)、相位偏移调制(Phase ShiftKeying,PSK)或振幅相位偏移调制(Amplitude Phase Shift Keying,APSK)的符元信号,亦属于本发明的范畴。另外,等化模块12不限于最小均方差均衡器,只要等化模块12所产生的等化信号的能量不大于等化模块12所产生的接收信号的能量,皆可利用本发明的等化增强模块补偿等化模块12所造成的能量缩减,以进一步改善解调制系统1的系统效能。It should be noted that the foregoing embodiments are used to illustrate the concept of the present invention, and those skilled in the art can make various modifications accordingly, but are not limited thereto. For example, the foregoing embodiments are described by taking the received signals y 1 ˜yn as symbol signals with four-bit phase shift modulation (QPSK) as an example, but the present invention is not limited to this, the received signals y 1 ˜yn are It can also have a symbol signal with Quadrature Amplitude Modulation (QAM), Phase Shift Keying (PSK) or Amplitude Phase Shift Keying (APSK), which also belongs to the scope of the present invention. . In addition, the
由上述可知,本发明根据缩放信号位于特定区域的比例来调整缩放系数,以补偿等化模块(最小均方差均衡器)所造成的能量缩减,进一步降低符元错误率或位错误率,提升解调制系统的效能。It can be seen from the above that the present invention adjusts the scaling factor according to the ratio of the scaling signal in a specific area, so as to compensate the energy reduction caused by the equalization module (minimum mean square error equalizer), further reduce the symbol error rate or bit error rate, and improve the solution. Efficiency of the modulation system.
以上所述仅为本发明的较佳实施例,凡依本发明申请专利范围所做的均等变化与修饰,皆应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
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