CN107230629A - The preparation method and gallium nitride field effect transistor of gallium nitride field effect transistor - Google Patents

Abstract

The present invention provides the preparation method and gallium nitride field effect transistor of a kind of gallium nitride field effect transistor, and method includes：Dielectric layer is formed on gallium nitride substrates；Ohmic contact metal layer is formed in the dielectric layer, the bottom of the ohmic contact metal layer contacts the gallium nitride substrates；Grid is formed in the dielectric layer and the gallium nitride substrates, the bottom of the grid is located in the gallium nitride substrates, and the side of the grid is connected to the bottom of between the top of the bottom of the grid and the grid and side and the grid in obtuse angle.In accordance with the invention it is possible to improve the resistance to pressure of gallium nitride field effect transistor.

Description

GaN Field Effect Transistor Manufacturing Method and GaN Field Effect Transistor

technical field

The invention relates to semiconductor technology, in particular to a manufacturing method of a gallium nitride field effect transistor and a gallium nitride field effect transistor.

Background technique

Power devices featuring low power consumption and high speed have recently attracted a lot of attention as the need for efficient and complete power conversion circuits and systems has increased. GaN is the third-generation wide-bandgap semiconductor material, because of its large bandgap (3.4eV), high electron saturation rate (2e ⁷ cm/s), high breakdown electric field (1e ¹⁰ V/cm-3e ¹⁰ V/ cm), high thermal conductivity, corrosion resistance and radiation resistance, and has strong advantages in high-voltage, high-frequency, high-temperature, high-power and radiation-resistant environmental conditions. Optimal material for power devices. Therefore, Gallium Nitride Field-effect Transistor based on gallium nitride and aluminum gallium nitride has good heat dissipation performance, high breakdown electric field, high saturation speed, gallium nitride field effect transistor Transistors have great application prospects in high-power high-frequency energy conversion and high-frequency microwave communication.

The structure of the gate contact hole in the prior art is a vertical structure, that is, a rectangular structure. The disadvantage of this structure is that the electric field at the edge of the gate contact hole is concentrated, which will cause premature breakdown of the GaN field effect transistor, thereby causing GaN FETs have poor withstand voltage.

Contents of the invention

The invention provides a method for manufacturing a gallium nitride field effect transistor and a gallium nitride field effect transistor, so as to solve the problem of poor withstand voltage of the gallium nitride field effect transistor in the prior art.

The first aspect of the present invention provides a method for manufacturing a gallium nitride field effect transistor, including:

forming a dielectric layer on the gallium nitride substrate;

forming an ohmic contact metal layer in the dielectric layer, the bottom of the ohmic contact metal layer contacts the gallium nitride substrate;

A gate is formed in the dielectric layer and the gallium nitride substrate, the bottom of the gate is located in the gallium nitride substrate, and the top of the gate is higher than the dielectric layer or connected to the dielectric layer flush, the side of the gate is connected between the bottom of the gate and the top of the gate and the side is at an obtuse angle to the bottom of the gate.

Another aspect of the present invention provides a gallium nitride field effect transistor, comprising:

GaN substrate;

a dielectric layer formed on the gallium nitride substrate;

an ohmic contact metal layer formed in the dielectric layer, the bottom of the ohmic contact metal layer contacts the gallium nitride substrate;

Gate, formed in the dielectric layer, the bottom of the gate is located in the gallium nitride substrate, the top of the gate is higher than the dielectric layer or flush with the dielectric layer, the gate The side of the electrode is connected between the bottom of the gate and the top of the gate and the side is at an obtuse angle to the bottom of the gate.

It can be seen from the above technical solution that the fabrication method of the GaN field effect transistor and the GaN field effect transistor provided by the present invention can form an inverted trapezoidal gate contact hole in the gate contact hole, thereby forming an inverted trapezoidal gate contact hole. pole, the structure of the gate contact hole can make the electric field at the edge of the gate contact hole disperse with the inclined side, adjust the distribution of the electric field, make the electric field not concentrated at one point as much as possible, and then avoid the GaN field effect transistor from being damaged as much as possible. Early breakdown improves the withstand voltage of eGaN FETs.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic flow chart of a method for manufacturing a gallium nitride field effect transistor according to an embodiment of the present invention;

2A to 2F are schematic structural diagrams of GaN field effect transistors according to another embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Embodiment one

This embodiment provides a method for manufacturing a GaN field effect transistor, which is used for manufacturing a GaN field effect transistor.

As shown in FIG. 1 , it is a schematic flowchart of a method for manufacturing a GaN field effect transistor according to this embodiment. The fabrication method of the gallium nitride field effect transistor includes:

Step 101, forming a dielectric layer on a gallium nitride substrate.

The dielectric layer can be composed of one layer of material, or multiple layers of material, and this step can specifically be:

forming a passivation layer on the gallium nitride substrate;

An oxide layer is formed on the passivation layer.

The passivation layer in this embodiment may be a Si ₃ N ₄ layer, and the oxide layer may be a PETEOS (Plasma enhanced tetraethyl orthosilicate, plasma enhanced deposition of tetraethoxysilane) layer.

The gallium nitride substrate in this embodiment may be a common gallium nitride substrate material for GaN field effect transistors, for example, a Si substrate, a GaN layer and an AlGaN layer are formed sequentially from bottom to top. Certainly, other material layers may also be used, and details are not repeated here.

Step 102 , forming an ohmic contact metal layer in the dielectric layer, and the bottom of the ohmic contact metal layer contacts the GaN substrate.

Specifically, an ohmic contact hole may be firstly formed in the dielectric layer to expose part of the gallium nitride substrate, and then metal is deposited in the ohmic contact hole to form an ohmic contact metal layer. The ohmic contact metal layer may include a Ti layer, an Al layer, a Ti layer and a TiN layer formed sequentially from bottom to top. The shape of the ohmic contact metal layer can be T-shaped, for example, the top of the ohmic contact metal layer is higher than the dielectric layer, and the width of the part higher than the dielectric layer is larger than the width in the dielectric layer.

Step 103, forming a gate in the dielectric layer and the gallium nitride substrate, the bottom of the gate is located in the gallium nitride substrate, the side of the gate is connected between the bottom of the gate and the top of the gate, and the side is connected to the top of the gate The bottom is obtusely angled.

The gate has a top, a bottom and two sides, and the two sides are respectively connected between the top and the bottom, and an obtuse angle is formed between the sides and the bottom, indicating that the sides are inclined in the dielectric layer.

For example, the manner of forming the gate may include the following two methods:

The first method: etching the dielectric layer and the gallium nitride substrate to form a gate contact hole, the gate contact hole includes a bottom contact hole in the gallium nitride substrate and an upper contact hole in the dielectric layer, the upper contact hole is An inverted trapezoid, such as an inverted isosceles trapezoid, the bottom contact hole is rectangular, and a metal layer is deposited in the gate contact hole to form a gate.

In this embodiment, the dielectric layer and the GaN substrate may be etched separately in a dry etching manner, for example, the dielectric layer and the GaN substrate are etched anisotropically. If the same dry etching process is used, since the materials of the dielectric layer and the gallium nitride substrate are different, the shapes of the contact holes finally formed are different. In the first method, by forming contact holes of two shapes, and then forming a complete gate contact hole, it is possible to minimize the number of gates located in the dielectric layer while ensuring the space occupied by the gate located in the gallium nitride substrate. The space occupied by the gate avoids affecting the miniaturization of GaN field effect transistors.

It should be noted that, in order to avoid errors in the process, the top of the gate can be higher than the top of the dielectric layer. The part of the gate higher than the dielectric layer may be rectangular, and the length of the rectangle may be greater than the width of the top of the gate contact hole. The part of the gate higher than the dielectric layer can be used as the top of the gate, and the part of the gate located in the gallium nitride substrate can be used as the bottom of the gate.

The second method: etching the dielectric layer and the gallium nitride substrate to form a gate contact hole, the gate contact hole is in an inverted trapezoidal shape, and depositing a metal layer in the gate contact hole to form a gate.

In the second manner, the shape of the gate is an inverted trapezoid, such as an inverted isosceles trapezoid, and the width of the top of the gate is greater than the width of the bottom of the gate. The second method of forming gate contact holes is also dry etching.

It should be noted that, in order to avoid errors in the process, the top of the gate can be higher than the top of the dielectric layer. The part of the gate higher than the dielectric layer may be rectangular, and the length of the rectangle may be greater than the width of the top of the gate contact hole. The part of the gate higher than the dielectric layer can be used as the top of the gate, and the part of the gate located in the gallium nitride substrate can be used as the bottom of the gate.

According to the fabrication method of the eGaN field effect transistor of this embodiment, by forming the gate contact hole with the inclined side, the gate with the inclined side can be formed in the gate contact hole, and the structure of the gate can make the gate The electric field at the pole edge disperses with the inclined side, and the distribution of the electric field is adjusted so that the electric field is not concentrated at one point as much as possible, thereby avoiding early breakdown of the GaN FET and improving the durability of the GaN FET. oppressive.

Example two

This embodiment provides a specific manufacturing method of a GaN field effect transistor manufacturing method. As shown in FIGS. 2A to 2F , they are schematic structural diagrams of various steps in the manufacturing method of the GaN field effect transistor according to the present embodiment.

As shown in FIG. 2A , a dielectric layer 202 is formed on a GaN substrate 201 .

The gallium nitride substrate 201 includes a Si substrate 2011 , a GaN layer 2012 and an AlGaN layer 2013 which are sequentially formed from bottom to top. The dielectric layer 202 in this embodiment includes a passivation layer 2021 and an oxide layer 2022. Specifically, a layer of Si ₃ N ₄ can be formed on the surface of the barrier layer of the AlGaN layer 2013 as the passivation layer 2021, and on the Si ₃ N ₄ layer A PETEOS layer is formed as the oxide layer 2022.

As shown in FIG. 2B , an ohmic contact hole 203 is formed in the dielectric layer 202 to expose the GaN substrate 201 , and surface treatment is performed on the ohmic contact hole 203 .

For example, the dielectric layer 202 can be etched by dry method, the etching gas is SF6 (Sulfurhexafluoride, sulfur hexafluoride), the etching power is 10W, and the etching pressure is 100mT. In addition, the ohmic contact hole 203 may be surface-treated with a mixed liquid using a hydrofluoric acid liquid, ammonia water, and hydrochloric acid, wherein the hydrofluoric acid liquid is diluted hydrofluoric acid (Diluted HF).

Specifically, two ohmic contact holes 203 may be formed simultaneously, one of which is a source contact hole, and the other ohmic contact hole is a drain contact hole.

The semiconductor device formed in step 2B is the first device 210 .

As shown in FIG. 2C , metal is deposited on the first device 210 to form an ohmic metal material layer 204 .

The ohmic metal material layer 204 may be composed of multiple layers of metal. For example, the ohmic metal material layer 204 includes a Ti layer, an Al layer, a Ti layer and a TiN layer formed sequentially from bottom to top. Specifically, a magnetron sputtering process may be used to deposit metal on the first device 210 to form the ohmic metal material layer 204 .

After the ohmic metal material layer 204 is formed, an annealing process is performed on the second device 220 shown in FIG. 2C , specifically at 840° C. for 30 seconds in an N ₂ atmosphere.

As shown in FIG. 2D , processes such as photolithography and etching are performed on the ohmic metal material layer 204 to form an ohmic contact metal layer 205 .

As shown in FIG. 2E , a gate contact hole 206 is formed in the GaN substrate 201 and the dielectric layer 202 .

Specifically, the gate contact hole 206 may be formed by a dry etching process, and the gate contact hole 206 shown in FIG. 2E is formed using the first method of the first embodiment above. The gate contact hole 206 is spaced apart from the ohmic contact metal layer 205 , that is, between two ohmic contact metal layers 205 . For example, the Si ₃ N ₄ layer 2021 and part of the AlGaN layer 2013 may be etched by dry method to form the gate contact hole 206 . Then, the gate contact hole 206 is cleaned with hydrochloric acid (HCl).

As shown in FIG. 2F , a gate 207 is formed in the gate contact hole 206 .

The gate dielectric layer of the gate 207 may be silicon nitride, and a metal layer is located above the gate dielectric layer. As shown in FIG. 2F, the top 2071 of the gate 207 is higher than the dielectric layer 202, the bottom 2072 of the gate 207 is located in the gallium nitride substrate, such as in the AlGaN layer 2013, and the two sides 2073 of the gate 207 are connected The top 2071 and the bottom 2072 of the gate 207, and the side 2073 and the bottom 2072 are obtuse angles.

After the gate 207 is formed, a metal interconnection layer and various subsequent processes may also be formed, and these processes are all in the prior art, and will not be repeated here.

According to the fabrication method of the eGaN field effect transistor of this embodiment, by forming the gate contact hole 206 with the inclined side, the gate 207 with the inclined side 2073 can be formed in the gate contact hole 206, and the gate 207 The structure can make the electric field at the edge of the gate 207 disperse with the inclined side, adjust the distribution of the electric field, make the electric field not concentrated at one point as far as possible, and thus avoid the premature breakdown of the GaN field effect transistor as far as possible, and improve the nitride Voltage withstand of gallium field effect transistors. In addition, by cleaning the gate contact hole 206, impurities in the gate contact hole 206 can be removed, thereby preventing these impurities from affecting the performance of the GaN field effect transistor, and ensuring the reliability of the GaN field effect transistor.

Embodiment three

This embodiment provides a gallium nitride field effect transistor, which is specifically manufactured by the method of embodiment 1 or embodiment 2.

As shown in FIG. 2F , the GaN field effect transistor of this embodiment includes a GaN substrate 201 , a dielectric layer 202 , an ohmic contact metal layer 205 and a gate 207 .

Wherein, the dielectric layer 202 is formed on the gallium nitride substrate 201; the ohmic contact metal layer 205 is formed in the dielectric layer 202, and the bottom of the ohmic contact metal layer 205 contacts the gallium nitride substrate 201; the gate 207 is formed in the dielectric layer 202, The bottom of the gate 207 is located in the gallium nitride substrate 201, the top 2071 of the gate 207 is higher than the dielectric layer 202 or flush with the dielectric layer 202, and the side 2073 of the gate 207 is connected to the bottom 2072 of the gate 207 and the gate 207 Between the top 2071 of the gate 207 and the side 2073 forms an obtuse angle with the bottom 2072 of the gate 207 .

Optionally, the gate 207 includes a bottom gate 208 located in the gallium nitride base portion, and an upper gate 209 located in the dielectric layer 202 , the upper gate 209 is in an inverted trapezoidal shape, or the gate 207 is in an inverted trapezoidal shape as a whole.

Optionally, the dielectric layer 202 includes a passivation layer 2021 and an oxide layer 2022 formed sequentially from bottom to top. Wherein, the passivation layer 2021 is a Si ₃ N ₄ layer, and the oxide layer 2022 is a PETEOS layer.

According to the eGaN field effect transistor of this embodiment, the formed gate contact hole includes inclined sides, and then a gate with inclined sides can be formed in the gate contact hole, and the structure of the gate contact hole can make The electric field at the edge of the gate contact hole disperses with the inclined side, and the distribution of the electric field is adjusted so that the electric field is not concentrated at one point as much as possible, thereby avoiding the premature breakdown of the GaN field effect transistor and improving the GaN field effect. Transistor voltage resistance.

Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the It includes the steps of the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for manufacturing a gallium nitride field effect transistor, characterized in that, comprising: forming a dielectric layer on the gallium nitride substrate; forming an ohmic contact metal layer in the dielectric layer, the bottom of the ohmic contact metal layer contacts the gallium nitride substrate; A gate is formed in the dielectric layer and the gallium nitride substrate, the bottom of the gate is located in the gallium nitride substrate, and the side of the gate is connected between the bottom of the gate and the gate between the tops of the poles and the sides form an obtuse angle with the bottom of the gate. 2. The fabrication method of GaN field effect transistor according to claim 1, characterized in that, The forming the gate in the dielectric layer and the gallium nitride substrate includes: Etching the dielectric layer and the gallium nitride substrate to form a gate contact hole, the gate contact hole includes a bottom contact hole in the gallium nitride substrate and an upper contact hole in the dielectric layer , the upper contact hole is in an inverted trapezoidal shape, and the bottom contact hole is in a rectangular shape; A metal layer is deposited in the gate contact hole to form the gate. 3. The method for manufacturing a gallium nitride field effect transistor according to claim 1, wherein said forming a gate in said dielectric layer and said gallium nitride substrate comprises: Etching the dielectric layer and the gallium nitride substrate to form a gate contact hole, the gate contact hole is an inverted trapezoid; A metal layer is deposited in the gate contact hole to form the gate. 4. The method for manufacturing a gallium nitride field effect transistor according to any one of claims 1-3, wherein forming a dielectric layer on a gallium nitride substrate comprises: forming a passivation layer on the gallium nitride substrate; An oxide layer is formed on the passivation layer. 5 . The method for manufacturing a GaN field effect transistor according to claim 4 , wherein the passivation layer is a Si ₃ N ₄ layer, and the oxide layer is a PETEOS layer. 6. A gallium nitride field effect transistor, characterized in that it comprises: GaN substrate; a dielectric layer formed on the gallium nitride substrate; an ohmic contact metal layer formed in the dielectric layer, the bottom of the ohmic contact metal layer contacts the gallium nitride substrate; a gate formed in the dielectric layer, the bottom of the gate is located in the gallium nitride substrate, the side of the gate is connected between the bottom of the gate and the top of the gate, and The side faces form an obtuse angle with the bottom of the gate. 7. The gallium nitride field effect transistor according to claim 6, wherein the gate comprises a bottom gate located in the gallium nitride base portion, and an upper gate located in the dielectric layer , the upper gate is in an inverted trapezoidal shape. 8. The GaN field effect transistor according to claim 6, wherein the gate is in an inverted trapezoidal shape. 9. The GaN field effect transistor according to any one of claims 6-8, wherein the dielectric layer comprises a passivation layer and an oxide layer formed sequentially from bottom to top. 10 . The GaN field effect transistor according to claim 9 , wherein the passivation layer is a Si ₃ N ₄ layer, and the oxide layer is a PETEOS layer. 11 .