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CN107180826B - 半导体封装组件 - Google Patents

半导体封装组件 Download PDF

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Publication number
CN107180826B
CN107180826B CN201710067544.3A CN201710067544A CN107180826B CN 107180826 B CN107180826 B CN 107180826B CN 201710067544 A CN201710067544 A CN 201710067544A CN 107180826 B CN107180826 B CN 107180826B
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Prior art keywords
pad
ground
chip
coupled
memory chip
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CN201710067544.3A
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CN107180826A (zh
Inventor
林圣谋
何敦逸
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明实施例提供一种半导体封装组件，可包括：基板；位于所述基板上的第一衬垫和第二衬垫；安装在所述基板上的逻辑芯片，所述逻辑芯片包括耦接于所述第二衬垫的第一逻辑芯片衬垫；安装在所述基板上的存储器芯片，所述存储器芯片包括第一存储器芯片衬垫和第一再分配层轨迹；其中，所述第一再分配层轨迹包括第一端和第二端，所述第一端通过所述第一存储器芯片衬垫耦接于所述第一衬垫，所述第二端耦接于所述第二衬垫而非所述第一衬垫；其中，所述第一衬垫和所述第二衬垫为接地衬垫。实施本发明实施例，可在存储器芯片的再分配层轨迹长度较长时，改善信号的完整性和减少耦合噪声。

Description

半导体封装组件
【技术领域】
本发明涉及半导体封装技术领域，尤其涉及半导体封装组件结构。
【背景技术】
为了确保电子产品和通信设备的小型化和多功能，期望半导体封装具有小的尺寸，以支持多针(mluti-pin)连接、高速率以及高功能。多功能系统级封装(System InPackage，SIP)通常要求集成离散的逻辑芯片(logic die)和存储器芯片(memory die)。所述存储器芯片通常使用较长的再分配层(Redistribution Layer，RDL)接地轨迹作为所述存储器芯片和所述逻辑芯片的连接。但是，在用于无线频率应用的系统级封装设计时，所述较长的再分配层接地轨迹带来不期望的信号完整性问题和噪声耦合问题。
因此，需要一种新型的半导体封装组件。
【发明内容】
本发明提供半导体封装组件结构，可在存储器芯片的再分配层轨迹长度较长时，改善信号的完整性和减少耦合噪声。
本发明实施例提供的一种半导体封装组件，可包括：基板；位于所述基板上的第一衬垫和第二衬垫；安装在所述基板上的逻辑芯片，所述逻辑芯片包括耦接于所述第二衬垫的第一逻辑芯片衬垫；安装在所述基板上的存储器芯片，所述存储器芯片包括第一存储器芯片衬垫和第一再分配层轨迹；其中，所述第一再分配层轨迹包括第一端和第二端，所述第一端通过所述第一存储器芯片衬垫耦接于所述第一衬垫，所述第二端耦接于所述第二衬垫而非所述第一衬垫；其中，所述第一衬垫和所述第二衬垫为接地衬垫。在该种半导体封装组件中，存储器芯片的第一再分配层轨迹的第一端和第二端分别耦接于基板的第一接地衬垫(第一衬垫)和第二接地衬垫(第二衬垫)，由此，当所述存储器芯片的再分配层轨迹长度较长时，该设计可通过降低串音缺陷来改善信号的完整性。而当所述半导体封装组件的逻辑芯片中包括射频电路用于射频应用，所述存储器芯片的再分配层轨迹同样可以通过减少所述存储器芯片的电路和所述逻辑芯片的射频电路之间的耦合噪声来改善射频灵敏度问题。
本发明实施例提供的另一种半导体封装组件，可包括：基板；位于所述基板上的第一衬垫和第二衬垫；安装在所述基板上的存储器芯片；以及安装在所述基板上的逻辑芯片；其中，所述存储器芯片包括第一侧、第二侧、存储器芯片衬垫以及再分配层轨迹；其中，所述存储器芯片衬垫靠近所述第一侧且与所述第一衬垫耦接；其中，所述再分配层轨迹包括靠近所述第一侧的第一端和靠近所述第二侧的第二端，所述第一端通过所述存储器芯片衬垫耦接于所述第一衬垫，所述第二端通过第一单导电路径耦接于靠近所述第二侧的所述第二衬垫；其中，所述逻辑芯片包括逻辑芯片衬垫，所述逻辑芯片衬垫靠近所述第二侧，且与所述第二衬垫耦接；其中，所述第一衬垫和所述第二衬垫为接地衬垫。类似第一种半导体封装组件，在该种半导体封装组件中，存储器芯片的再分配层轨迹的第一端和第二端分别耦接于基板的第一接地衬垫(第一衬垫)和第二接地衬垫(第二衬垫)，由此，当所述存储器芯片的再分配层轨迹长度较长时，该设计可通过降低串音缺陷来改善信号的完整性。而当所述半导体封装组件的逻辑芯片中包括射频电路用于射频应用，所述存储器芯片的再分配层轨迹同样可以通过减少所述存储器芯片的电路和所述逻辑芯片的射频电路之间的耦合噪声来改善射频灵敏度问题。
本发明实施例提供的再一种半导体封装组件，可包括：基板；位于所述基板上的第一接地衬垫和第二接地衬垫；安装在所述基板上的存储器芯片；以及安装在所述基板上的逻辑芯片；其中，所述存储器芯片包括存储器接地衬垫以及再分配层接地轨迹；其中，所述存储器接地衬垫耦接于所述第一接地衬垫；其中，所述再分配层轨迹包括第一端和第二端，所述第一端通过包括所述存储器接地衬垫的第一导电路径耦接于所述第一接地衬垫，所述第二端通过不与所述存储器接地轨迹耦接的第二导电路径耦接于所述第二接地衬垫；其中，所述逻辑芯片包括逻辑接地衬垫，所述逻辑接地衬垫通过所述第二接地衬垫耦接于所述第二端。类似第一种半导体封装组件，在该种半导体封装组件中，存储器芯片的再分配层接地轨迹的第一端和第二端分别耦接于基板的第一接地衬垫和第二接地衬垫，由此，当所述存储器芯片的再分配层轨迹长度较长时，该设计可通过降低串音缺陷来改善信号的完整性。而当所述半导体封装组件的逻辑芯片中包括射频电路用于射频应用，所述存储器芯片的再分配层轨迹同样可以通过减少所述存储器芯片的电路和所述逻辑芯片的射频电路之间的耦合噪声来改善射频灵敏度问题。
【附图说明】
图1为依据本发明的一些实施例的半导体封装组件500a和500b的俯视图。
图2为依据本发明的一些实施例的半导体封装结构500c的俯视图。
图3-图4为图1的剖面图，示出图1中的半导体封装组件的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局。
图5为依据本发明的一些实施例的半导体封装组件500d和500e的俯视图。
图6-图7为图5的截面图，示出图5中的半导体封装组件的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局。
【具体实施方式】
在说明书及权利要求当中使用了某些词汇来指称特定的组件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在通篇说明书及权利要求当中所提及的“包含”及“包括”为一开放式的用语，故应解释成“包含但不限定于”。“大体上”是指在可接受的误差范围内，本领域技术人员能够在一定误差范围内解决所述技术问题，基本达到所述技术效果。此外，“耦接”一词在此包含任何直接及间接的电性连接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表该第一装置可直接电性连接于该第二装置，或通过其它装置或连接手段间接地电性连接至该第二装置。以下所述为实施本发明的较佳方式，目的在于说明本发明的精神而非用以限定本发明的保护范围，本发明的保护范围当视后附的权利要求所界定者为准。
本发明实施例提供了半导体封装组件。所述半导体封装组件为系统级封装。所述半导体封装组件包括至少一个逻辑芯片和至少一个存储器芯片。所述存储器芯片包括再分配层接地轨迹，所述再分配层接地轨迹包括朝向相反的两个端子。所述两个端子中的其中一个设计为靠近所述存储器芯片的接地衬垫(pad)并耦接于所述接地衬垫。所述两个端子中的另一个耦接于基板的接地衬垫。所述半导体封装组件设计为增加所述再分配层接地轨迹的两个端子的接地点，以避免具有较长的长度的所述再分配层接地轨迹的两个端子之间的电势差(potential different)。此外，所述再分配层接地轨迹的额外的接地点可减少所述较长的再分配层接地轨迹造成的射频干扰(interference)。
图1为依据本发明的一些实施例的半导体封装组件500a和500b的俯视图(planview)。图3-4为图1的剖面图，示出图1中的半导体封装组件的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局。为了清楚地展示半导体封装组件500a和500b的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局，图1中省略了成型材料。
如图1及图3所示，半导体封装组件500a通过多个导电结构710安装在基础800上。在一些实施例中，半导体封装组件500a为系统级封装。在一些实施例中，所述基础800可包括印刷电路板(Printed Circuit Board，PCB)。导电结构710可包括导电凸块(bump)结构，例如，铜凸块、焊锡球结构、焊锡凸块结构、导电柱结构、导线结构或者导电膏中任一种。半导体封装组件500a包括基板700、半导体芯片(逻辑芯片)100a、半导体芯片(存储器芯片)200a以及存储器芯片200a的再分配层接地轨迹240。需要注意的是，基板700、逻辑芯片100a以及存储器芯片200a为半导体封装组件500a的离散的，独立的组件。
图1和图3提供了基板700。基板700包括芯片粘接表面701用于安装逻辑芯片100a和存储器芯片200a。基板700包括靠近芯片粘接表面701设置的多个离散的接地衬垫102和104。在一些实施例中，接地衬垫102和104用于将输入/输出连接至地。因此，接地衬垫102和104同时作为基板700的接地衬垫。基板700还包括形成在其内部且耦接于接地衬垫102和104的互连(未图示)。在一些实施例中，基板700可包括半导体基板，例如，硅基板。在其他一些实施例中，基板700可包括介电材料，例如，有机材料。在一些实施例中，所述有机材料包括带有玻璃纤维的聚丙烯、环氧树脂、聚酰亚胺、氰酸酯、其他合适的材料中任一种或者它们的组合。
如图1和图3所示，半导体芯片100a设置在基板700上。半导体芯片100a可通过半导体芯片100a和基板700之间的粘合剂112(例如，糊状物)安装到基板700的芯片粘接表面701。在一些实施例中，半导体芯片100a通过引线接合技术(bonding technology)耦接至基板700。在一些实施例中，如图3所示，半导体芯片100a通过包括导线(例如，导线320a)的导体结构耦接至基板700。在一些实施例中，半导体芯片100a可为逻辑芯片100a，所述逻辑芯片100a包括中央处理单元、图像处理单元、动态随机存储器控制器中任一种，或者它们的组合。
如图1和图3所示，半导体芯片200a通过半导体芯片100a和200a之间的粘合剂212(例如，糊状物)直接堆叠安装在半导体芯片100a上。在一些实施例中，半导体芯片200a可作用为存储器芯片200a，例如，动态随机访问存储器芯片。在一些实施例中，半导体芯片200a通过引线接合技术耦接至基板700。如图3所示，半导体芯片200a通过包括导线(例如，导线300a和310a)的导体结构耦接至基板700。
如图1和图3所示，存储器芯片200a可包括存储器输入/输出芯片衬垫202且在存储器芯片200a的输入/输出芯片衬垫202上包括再分配层结构270a。在一些实施例中，存储器芯片200a可为一个或多个动态随机存储器芯片。再分配层结构270a可包括至少一个再分配层轨迹240和至少一个衬垫250a。再分配层轨迹240和衬垫250a用于输入/输出连接至地。如图3所示，在一些实施例中，再分配层轨迹240作用为再分配层接地轨迹240。再分配层轨迹240设计为位于单层(single layered-level)的再分配层结构270a中。如图3所示，在一些实施例中，衬垫250a位于再分配层结构270a的顶部且位于输入/输出衬垫区域210内部。衬垫250a作用为存储器芯片200a的接地衬垫。
再分配层轨迹240用于将存储器输入/输出芯片衬垫202的接地路径从衬垫250a处以扇形方式散开至或重新路由至特定的位置(例如，所述特定的位置靠近逻辑芯片100a的输入/输出衬垫区域110)。存储器芯片200a的再分配层接地轨迹240可具有长的长度。如图1和图3所示，存储器芯片200a的再分配层接地轨迹240设计为从存储器芯片200a的第一侧220延伸至存储器芯片200a的第二侧222，以用于连接存储器芯片200a和逻辑芯片100a。再分配层接地轨迹240包括第一端242和远离第一端242的第二端244。第一端242耦接于邻近的衬垫250a。存储器芯片200a的衬垫250a耦接于其邻近的属于基板700的接地衬垫102。在一些实施例中，再分配层接地轨迹240的第一端242和存储器芯片200a的衬垫250a均设置为邻近存储器芯片200a的第一侧220。基板700的接地衬垫102靠近存储器芯片200a的第一侧220设置。此外，基板700的接地衬垫102靠近存储器芯片200a的衬垫250a设置，以减小存储器芯片200a到基板700的接地路径。
如图1和图3所示，存储器芯片200a的衬垫250a通过导电路径300a(例如，接合线)耦接于接地衬垫102。需要注意的是，导电路径300a为包括两端的单接合线，所述两端分别与衬垫250a和接地衬垫102接触。导电路径300a不与接地衬垫104接触。
如图1和图3所示，再分配层接地轨迹240的第二端244耦接于基板700的接地衬垫，例如，接地衬垫104而非接地衬垫102。再分配层接地轨迹240的第二端244耦接于接地衬垫104，而不使用衬垫250a和接地衬垫102。在一些实施例中，再分配层接地轨迹240的第二端244和接地衬垫104均靠近存储器芯片200a的第二侧222设置。第一侧220和第二侧222为存储器芯片200a的不同侧。再分配层接地轨迹240的第二端244通过导电路径310a(例如，接合线)耦接于接地衬垫104。需要注意的是，导电路径310a为包括两端的单接合线，所述两端分别与第二端244和接地衬垫104接触。导电路径310a不与接地轨迹102和接地路径300a接触。
如图1和图3所示，逻辑芯片100a可包括逻辑设备(未图示)以及位于所述逻辑设备上的再分配层结构(未图示)。逻辑芯片100a的再分配层结构可包括至少一个再分配层轨迹和至少一个衬垫150a，该再分配层结构用于传输逻辑设备的接地信号。如图3所示，在一些实施例中，衬垫150a设置在所述再分配层结构的顶部。衬垫150a设置在逻辑芯片100a的输入/输出衬垫区域110中，且作用为逻辑芯片100a的接地衬垫。
如图1和图3所示，逻辑芯片100a的衬垫150a仅通过导电路径320a(例如，接合线)耦接于基板700的接地衬垫104。在一些实施例中，逻辑芯片100a的衬垫150a不与基板700的接地衬垫102耦接。导电路径300a、310a以及320a为不同的导电路径。也即，导电路径320a不与导电路径300a和310a接触。
如图1所示，图3中的半导体芯片200a的再分配层结构270a可包括第二再分配层信号轨迹260和耦接于第二再分配层信号轨迹260的至少一个衬垫252a。在一些实施例中，如图1所示，第二再分配层信号轨迹260设计为靠近再分配层接地轨迹240并与240平行。类似于再分配层接地轨迹240，存储器芯片200a的第二再分配层信号轨迹260具有长的长度。存储器芯片200a的第二再分配层信号轨迹260设计为从存储器芯片200a的第一侧220延伸至第二侧222。
第二再分配层信号轨迹260和衬垫252a用于输入/输出连接至存储器输入/输出芯片衬垫202的信号。第二再分配层信号轨迹260可作用为再分配层信号轨迹。第二再分配层信号轨迹260不与基板700的接地衬垫102和104耦接。在一些实施例中，衬垫252a也设置在再分配层结构(例如，图3所示的再分配层结构270a)的顶部。衬垫252a作用为存储器芯片200a的信号衬垫。衬垫252a位于输入/输出衬垫范围210内。此外，衬垫252a靠近衬垫250a但与衬垫250a绝缘。
如图1所示，第二再分配层信号轨迹260包括第三端262和远离第三端262的第四端264。第二再分配层信号轨迹260的第三端262位于再分配层接地轨迹240的第一端242旁边。此外，第二再分配层信号轨迹260的第四端264位于再分配层接地轨迹240的第二端244旁边。第三端262耦接于其附近的衬垫252a。存储器芯片200a的衬垫252a耦接于基板700的相应的信号衬垫(未图示)。第二再分配层信号轨迹260通过基板700的导电路径330、340和导电结构720耦接于逻辑芯片100a的衬垫152。在一些实施例中，导电路径330和340可包括接合线。基板700的导电结构720可包括电路和衬垫。
如图1所示，在一些实施例中，逻辑芯片100a的衬垫152靠近衬垫150a但是与150a电隔离。衬垫152可作用为逻辑芯片100a的信号衬垫。
如图3所示，半导体封装组件500a进一步包括围绕逻辑芯片100a、存储器芯片200a以及导电路径(包括导电路径300a、310a以及320a)的成型材料(molding compound)750。成型材料750与逻辑芯片100a、存储器芯片200a以及导电路径300a、310a以及320a接触。成型材料750还覆盖基板700的芯片附着表面701。在一些实施例中，成型材料750可由非导电材料形成，例如，环氧树脂、树脂、可塑造的聚合物，以及它们的类似物。成型材料750刚提供时可为流体的，然后通过化学反应处理，例如环氧树脂、树脂。在另一些实施例中，成型材料750可为紫外线或热处理后的聚合物用作为可设置在逻辑芯片100a和存储器芯片200a周围的胶体或可伸缩的固体，并随时可被紫外线或热处理流程处理。成型材料750可使用模具进行处理。
图4为图1的截面图，示出半导体封装组件500b的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局。此实施例与前面描述的实施例中相同或者相近的元件请参考图1和图3，为简化起见在此将不再重复。半导体封装组件500b与半导体封装组件500a的区别为半导体封装组件500b包括通过倒装技术设置在基板700上的半导体芯片(逻辑芯片)100b。在一些实施例中，半导体芯片100b可作用为逻辑芯片100b。逻辑芯片100b可包括至少一个衬垫150b，用于输入/输出连接至地。衬垫150b作用为逻辑芯片100b的接地衬垫。如图1所示，衬垫150b设置在输入/输出衬垫区域110内。
如图4所示，逻辑芯片100b是倒装的，并通过导电结构160耦接于基板700。导电结构160设置在衬垫150b上。导电结构160可包括耦接于相应的衬垫150b的至少一个凸块结构。导电凸块结构可包括铜凸块、焊锡球结构、焊锡凸块结构、导电柱结构、导线结构或者导电膏结构中任一种。逻辑芯片100b的衬垫150b通过互连320b(例如，基板700中嵌入的电路)耦接于基板700的接地衬垫104。
图2为依据本发明的一些实施例的半导体封装结构500c的俯视图。此实施例与前面描述的实施例中相同或者相近的元件请参考图1、图3以及图4，为简化起见在此将不再重复。半导体封装组件500c与半导体封装组件500a/500b的区别为半导体封装组件500c的半导体芯片(逻辑芯片)100a/100b还包括集成在所述半导体芯片(逻辑芯片)100a/100b中的至少一个射频单元360，用于射频应用。
图5为依据本发明的一些实施例的半导体封装组件500d和500e的俯视图。图6-7为图5的截面图，示出图5中的半导体封装组件的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局。为简洁地示出半导体封装组件500d和500e的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局，在图5中未示出成型材料。此实施例与前面描述的实施例中相同或者相近的元件请参考图1-图4，为简化起见在此将不再重复。
如图5和图6所示，半导体封装组件500d和图1-图3中的半导体封装组件500a/500b的区别为存储器芯片200a设置在逻辑芯片100a旁边。因此，存储器芯片200a和逻辑芯片100a分别通过糊状物212和112安装在芯片附着表面701上。
如图6所示，在一些实施例中，逻辑芯片100a通过引线结合技术耦接于逻辑芯片100a。半导体芯片100a可通过半导体芯片100a和基板700之间的粘合剂112(例如，糊状物)安装在基板700的芯片附着表面701上。
如图5和图6所示，在一些实施例中，再分配层接地轨迹240的第一端242、存储器芯片200a的衬垫250a以及基板700的接地衬垫102靠近存储器芯片200a的第一侧220设置。再分配层接地轨迹240的第二端244、逻辑芯片100a的衬垫150a和接地轨迹104均靠近存储器芯片200a的第二侧222设置。此外，如图6所示，接地衬垫104设置在逻辑芯片100a和存储器芯片200a之间。
图7为图5的截面图，示出图5中的半导体封装组件500e的基板、逻辑芯片、存储器芯片以及所述存储器芯片的再分配层接地轨迹的布局。此实施例与前面描述的实施例中相同或者相近的元件请参考图5-图6，为简化起见在此将不再重复。半导体封装组件500e与半导体封装组件500d的区别为半导体封装组件500e包括通过倒装芯片技术设置在基板700上的半导体芯片100b和半导体芯片200b。在一些实施例中，半导体芯片100b作用为逻辑芯片100b、半导体芯片200b作用为存储器芯片200b。
如图7所示，逻辑芯片100b可包括至少一个衬垫150b，用于输入/输出连接至地。衬垫150b作用为逻辑芯片100b的接地衬垫。
存储器芯片200b可包括存储器输入/输出芯片衬垫202和位于存储器输入/输出芯片衬垫202上的再分配层结构270b。再分配层结构270b可包括至少一个再分配层轨迹240和至少两个衬垫250b和250c。再分配层轨迹240和衬垫250b和250c用于输入/输出连接至地。如图7所示，在一些实施例中，再分配层结构240作用为再分配层接地轨迹240。再分配层轨迹240设计为位于再分配层结构270b的单一水平面上。再分配层轨迹240的两端242和244分别耦接于衬垫250b和250c。衬垫250b和250c作用为存储器芯片200a的接地衬垫。如图5所示，衬垫250b设置在输入/输出衬垫区域210内。衬垫250c设置在输入/输出衬垫区域210外。例如，衬垫250c靠近再分配层轨迹240的端244设置。此外，衬垫250b不与衬垫250c接触。
如图7所示，存储器芯片200b上下倒装，且通过导电结构266和268耦接于基板700。导电结构266和268分别设置在衬垫250b和250c上。导电结构266和268可包括耦接于衬垫250b和250c的相应的导电凸块。此外，导电结构266不与导电结构268接触。存储器芯片200b的接地衬垫250b通过导电结构266和互连300b耦接于基板700的接地衬垫102。存储器芯片200b的衬垫250c通过导电结构268和嵌入在基板700中的互连320b耦接于基板700的接地衬垫104。在一些实施例中，互连300b和320b嵌入在基板700中。互连300b和320b可包括多个电路。
如图7所示，逻辑芯片100b上下倒装，且通过导电结构160耦接于基板700。导电结构160设置在衬垫150b上。导电结构160可包括耦接于衬垫150b的相应的导电凸块结构。逻辑芯片100b的衬垫150b通过导电结构160和基板700的互连320b耦接于基板700的接地衬垫104。也即，互连320b与存储器芯片200b的衬垫250c、逻辑芯片100b的衬垫150b以及基板700的接地衬垫104电连接。此外，互连300b和320b为离散的电路。互连300b不与互连320b接触。
实施例提供了半导体封装组件。所述半导体封装组件包括基板、位于基板上的存储器芯片和逻辑芯片。所述存储器芯片包括再分配层接地轨迹，所述再分配层接地轨迹包括第一端和远离所述第一端的第二端。所述第一端和第二端分别靠近所述存储器芯片的不同侧。所述再分配层接地轨迹的所述第一端通过包含所述存储器芯片的一个衬垫的第一导电路径耦接于所述基板的第一接地衬垫，所述第一接地衬垫设置在一个输入/输出衬垫范围内。所述再分配层接地轨迹的第二端通过与所述第一导电路径不同的第二导电路径耦接于所述基板的第二接地衬垫。所述第二导电路径不与所述存储器的所述衬垫耦接。所述逻辑芯片包括通过所述基板的所述第二接地衬垫耦接于所述再分配层的第二端的衬垫。
本发明的半导体封装组件设计为在所述存储器芯片的再分配层轨迹的两端包括接地路径。如果所述存储器芯片的再分配层接地轨迹长度较长，再分配层接地轨迹的设计可通过降低串音缺陷来改善信号的完整性。如果所述半导体封装组件的逻辑芯片中包括射频电路用于射频应用，所述存储器芯片的再分配层接地轨迹同样可以通过减少所述存储器芯片的电路和所述逻辑芯片的射频电路之间的耦合噪声来改善射频灵敏度问题。
权利要求书中用以修饰元件的“第一”、“第二”等序数词的使用本身未暗示任何优先权、优先次序、各元件之间的先后次序、或所执行方法的时间次序，而仅用作标识来区分具有相同名称(具有不同序数词)的不同元件。
本发明虽以较佳实施例揭露如上，然其并非用以限定本发明的范围，任何本领域技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰，因此本发明的保护范围当视权利要求所界定者为准。

Claims (20)

1.一种半导体封装组件，其特征在于，包括：
基板；
位于所述基板上的第一衬垫和第二衬垫；
安装在所述基板上的逻辑芯片，所述逻辑芯片包括耦接于所述第二衬垫的第一逻辑芯片衬垫；
安装在所述基板上的存储器芯片，所述存储器芯片包括第一存储器芯片衬垫和第一再分配层轨迹；
其中，所述第一再分配层轨迹包括第一端和第二端，所述第一端通过所述第一存储器芯片衬垫耦接于所述第一衬垫，其中，所述第一存储器芯片衬垫通过第一导电路径耦接于所述第一衬垫，所述第二端通过单导电路径耦接于所述第二衬垫而非所述第一衬垫，所述单导电路径的两端分别与所述第二端和所述第二衬垫接触；
其中，所述第一逻辑芯片衬垫通过第三导电路径耦接于所述第二衬垫，其中，所述第三导电路径、所述第一导电路径和所述单导电路径为不同的导电路径；
其中，所述第一衬垫和所述第二衬垫为接地衬垫。
2.如权利要求1所述的半导体封装组件，其特征在于，所述第一存储器芯片衬垫和所述第一衬垫均靠近所述存储器芯片的第一侧设置。
3.如权利要求2所述的半导体封装组件，其特征在于，所述第一逻辑芯片衬垫和所述第二衬垫靠近所述存储器芯片的第二侧设置，其中，所述第二侧与所述第一侧不同。
4.如权利要求1所述的半导体封装组件，其特征在于，所述第一再分配层轨迹为接地轨迹。
5.如权利要求1所述的半导体封装组件，其特征在于，所述第一再分配层轨迹设置在单层结构上。
6.如权利要求1所述的半导体封装组件，其特征在于，所述存储器芯片直接位于所述逻辑芯片上。
7.如权利要求1所述的半导体封装组件，其特征在于，所述存储器芯片设置在所述逻辑芯片旁边。
8.如权利要求1所述的半导体封装组件，其特征在于，所述存储器芯片进一步包括：
第二再分配层信号轨迹，包括第三端和第四端，其中，所述第三端耦接于所述存储器芯片的第二存储器芯片衬垫，所述第四端耦接于所述逻辑芯片的第二逻辑芯片衬垫。
9.如权利要求8所述的半导体封装组件，其特征在于，所述第二存储器芯片衬垫与所述第一存储器芯片衬垫隔离，所述第二逻辑芯片衬垫与所述第一逻辑芯片衬垫隔离。
10.如权利要求8所述的半导体封装组件，其特征在于，所述第二再分配层信号轨迹不与所述第一衬垫或所述第二衬垫耦接。
11.如权利要求9所述的半导体封装组件，其特征在于，所述第四端通过所述基板的导电结构耦接于所述第二逻辑芯片衬垫。
12.如权利要求10所述的半导体封装组件，其特征在于，所述第二再分配层信号轨迹为单轨迹。
13.一种半导体封装组件，其特征在于，包括：
基板；
位于所述基板上的第一衬垫和第二衬垫；
安装在所述基板上的存储器芯片；以及
安装在所述基板上的逻辑芯片；
其中，所述存储器芯片包括第一侧、第二侧、存储器芯片衬垫以及再分配层轨迹；
其中，所述存储器芯片衬垫靠近所述第一侧且与所述第一衬垫耦接；
其中，所述再分配层轨迹包括靠近所述第一侧的第一端和靠近所述第二侧的第二端，所述第一端通过所述存储器芯片衬垫耦接于所述第一衬垫，其中，所述存储器芯片衬垫通过第一导电路径耦接于所述第一衬垫，所述第二端通过第一单导电路径耦接于靠近所述第二侧的所述第二衬垫；
其中，所述逻辑芯片包括逻辑芯片衬垫，所述逻辑芯片衬垫靠近所述第二侧，且与所述第二衬垫耦接；
其中，所述第一衬垫和所述第二衬垫为接地衬垫；
其中，所述第一单导电路径的两端分别与所述第二端和所述第二衬垫接触；
其中，所述逻辑芯片衬垫通过第三导电路径耦接于所述第二衬垫，其中，所述第三导电路径、所述第一导电路径和所述第一单导电路径为不同的导电路径。
14.如权利要求13所述的半导体封装组件，其特征在于，所述第一单导电路径不与所述第一衬垫接触。
15.如权利要求14所述的半导体封装组件，其特征在于，所述存储器芯片衬垫通过不与所述第一单导电路径接触的第二单导电路径耦接于所述第一衬垫。
16.如权利要求13所述的半导体封装组件，其特征在于，所述第一衬垫和所述第二衬垫为离散的接地衬垫。
17.一种半导体封装组件，其特征在于，包括：
基板；
位于所述基板上的第一接地衬垫和第二接地衬垫；
安装在所述基板上的存储器芯片；以及
安装在所述基板上的逻辑芯片；
其中，所述存储器芯片包括存储器接地衬垫以及再分配层接地轨迹；
其中，所述存储器接地衬垫耦接于所述第一接地衬垫；
其中，所述再分配层接地轨迹包括第一端和第二端，所述第一端通过包括所述存储器接地衬垫的第一导电路径耦接于所述第一接地衬垫，所述第二端通过不与所述存储器接地衬垫耦接的第二导电路径耦接于所述第二接地衬垫；
其中，所述逻辑芯片包括逻辑接地衬垫，所述逻辑接地衬垫通过所述第二接地衬垫耦接于所述第二端；
其中，所述第二导电路径为单导电路径，所述单导电路径的两端分别与所述第二端和所述第二接地衬垫接触。
18.如权利要求17所述的半导体封装组件，其特征在于，所述第一接地衬垫和所述第二接地衬垫为离散的接地衬垫，所述第一导电路径和所述第二导电路径为不同的导电路径。
19.如权利要求17所述的半导体封装组件，其特征在于，所述第一端位于所述第一接地衬垫和所述存储器接地衬垫附近。
20.如权利要求17所述的半导体封装组件，其特征在于，所述第二端始终远离所述第一接地衬垫和所述存储器接地衬垫，所述第二端靠近所述第二接地衬垫。
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