CN107180651A - Storage element and memory array - Google Patents

Abstract

The invention discloses a storage element, which comprises a storage unit and a voltage transmission device. The memory cell includes a floating gate transistor, a word line transistor, a first capacitive element, and a second capacitive element. The floating grid transistor is provided with a first end, a second end and a floating grid, and the first end of the floating grid transistor receives a bit line signal. The first terminal of the word line transistor is coupled to the second terminal of the floating gate transistor, the second terminal of the word line transistor receives the third voltage, and the control terminal of the word line transistor receives the word line signal. The voltage transmitting means outputs the second voltage during the inhibiting operation and outputs the first voltage during the writing operation or the erasing operation. The first capacitor element is coupled to the voltage transmission device and the floating gate and receives a first control signal. The second capacitive element receives a second control signal.

Description

Storage element and memory array

technical field

The present invention relates to a memory element, especially a memory element with a voltage transmission device.

Background technique

Electronic rewritable non-volatile memory is a memory that can save stored information without power supply, and can be rewritten by other programs after the memory is loaded. Since the non-volatile memory can be used in a wide range of applications, it has become a trend to embed the non-volatile memory and the main circuit on the same chip, especially for personal electronic devices that have strict restrictions on the circuit area. in application.

A conventional non-volatile memory device may include a floating gate transistor for storing data, and one or two select transistors for controlling the floating gate transistor to perform corresponding operations. Since all operations of the memory cell, such as write operation, clear operation, inhibit operation and read operation, must be controlled by the selection transistor, the selection transistor often needs to operate at a high voltage, and must be implemented with a transistor with a high threshold voltage. Do.

However, since the select transistor has a high threshold voltage, the read operation of the memory cell must also be driven at a high voltage, thus prolonging the time required for reading data and increasing unnecessary power consumption. Therefore, how to speed up the reading process and reduce the reading voltage requirement has become a problem to be solved.

Contents of the invention

In order to speed up the reading process of a memory cell and reduce unnecessary power consumption compared with the prior art, an embodiment of the present invention provides a memory element. The storage element includes: a first voltage transmission device and a first storage unit.

The first voltage transmission means outputs a voltage according to the operation of the storage element. The first storage unit includes a first floating gate transistor and a first capacitance element. The first floating gate transistor has a first terminal, a second terminal and a floating gate. The first end of the first floating gate transistor receives the first bit line signal. The first capacitive element has a first end, a second end, a control end and a base, the first end of the first capacitive element is coupled to the first voltage transmission device, and the control end of the first capacitive element is coupled to the first floating connection The floating gate of the gate transistor is connected, and the base of the first capacitive element receives the first control signal.

Both the first capacitive element and the first voltage transmission device are arranged in the first N well region. During the writing operation or erasing operation of the first storage unit, the first terminal of the first capacitive element receives the first voltage output by the first voltage transmission device. During the inhibit operation of the first storage unit, the first terminal of the first capacitive element receives the second voltage output by the first voltage transmission device. The first voltage is greater than the second voltage.

An embodiment of the present invention provides a memory array including at least one column of storage elements. Each storage element in the same column includes a first voltage transfer device, a second voltage transfer device, a first storage unit and a second storage unit.

The first voltage transmission device receives the operation prohibition signal, and outputs a voltage according to the first transmission grid control signal. The second voltage transmission device receives the operation prohibition signal, and outputs a voltage according to the second transmission gate control signal.

The first storage unit includes a first floating gate transistor, a first capacitance element, a first word line transistor and a second capacitance element. The first floating gate transistor has a first terminal, a second terminal and a floating gate, and the first terminal of the first floating gate transistor receives a first bit line signal. The first capacitive element has a first end, a second end, a control end and a base, the first end of the first capacitive element is coupled to the first voltage transmission device, and the control end of the first capacitive element is coupled to the first floating connection The floating gate of the gate transistor and the base of the first capacitive element receive the first control signal. The first word line transistor has a first end, a second end and a control end, the first end of the first word line transistor is coupled to the second end of the first floating gate transistor, and the second end of the first word line transistor The third voltage is received, and the control terminal of the first word line transistor is used for receiving the word line signal. The second capacitive element is coupled to the floating gate of the first floating gate transistor and receives a second control signal.

The second memory unit includes a second floating gate transistor, a third capacitive element, a second word line transistor and a fourth capacitive element. The second floating gate transistor has a first terminal, a second terminal and a floating gate, and the first terminal of the second floating gate transistor receives the second bit line signal. The third capacitive element has a first end, a second end, and a control end that is a base, the first end of the third capacitive element is coupled to the second voltage transmission device, and the control end of the third capacitive element is coupled to the second floating connection. The floating gate of the gate transistor is connected, and the base of the third capacitive element receives the first control signal. The second word line transistor has a first end, a second end and a control end, the first end of the second word line transistor is coupled to the second end of the second floating gate transistor, and the second end of the second word line transistor The third voltage is received, and the control terminal of the second word line transistor receives the word line signal. The fourth capacitive element is coupled to the floating gate of the second floating gate transistor and receives the second control signal.

A plurality of storage elements in the same column receive the same operation prohibition signal, the same first control signal, the same second control signal, and the same word line signal. A plurality of storage elements in the same column receive a plurality of different first bit line signals, a plurality of different second bit line signals, a plurality of different first transmission gate control signals, and a plurality of different The second transfer gate control signal.

Description of drawings

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention.

FIG. 2 is a top view of the layout of the storage device in FIG. 1 .

FIG. 3 is a schematic structural diagram of the first capacitive element and the first voltage transmission device in FIG. 2 .

FIG. 4 is a schematic diagram of a storage device according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a storage device according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a memory array according to an embodiment of the invention.

FIG. 7 is a schematic diagram of a storage device according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of a storage device according to another embodiment of the present invention.

FIG. 9 is a schematic diagram of a storage device according to another embodiment of the present invention.

FIG. 10 is a schematic structural diagram of the first capacitive element and the first voltage transmission device in FIG. 9 .

FIG. 11 is a schematic diagram of a storage device according to another embodiment of the present invention.

FIG. 12 is a schematic diagram of a storage device according to another embodiment of the present invention.

Wherein, the reference signs are explained as follows:

10, 301 to 30K, 50, 60, memory element

70, 80, 90

100 first storage unit

110 First capacitive element

120 Second capacitive element

130, 730 First voltage transmission device

FGT1 first floating gate transistor

WLT1 first word line transistor

PG1 First Pass Gate Transistor

PG2 Second Pass Gate Transistor

PL, PL1 to PLK First transfer gate control signal

PL’, PL’1 to PL’K Second transfer gate control signals

WL, WL1 to WLM, word line signals

AWL1 to AWLN

GND third voltage

BL, BL1 to BLK, first bit line signal

ABL1 to ABLN

CS1 First control signal

CS2 Second control signal

INH Inhibit operation signal

NW1 First N Well Area

PW1 P well area

NW2 Second N well area

AA1, AA2, AA3 active area

FG1 floating gate

131, 731 first end of first transfer gate transistor

132, 732 second terminal of the first transfer gate transistor

133, 733 Control terminal of the first transfer gate transistor

134 First terminal of the second transfer gate transistor

135 Second terminal of the second transfer gate transistor

136 Control terminal of the second transfer gate transistor

P+ P type doped region

230, 330 second voltage transmission means

PG3 Third Pass Gate Transistor

PG4 Fourth Pass Gate Transistor

310 third capacitive element

320 fourth capacitive element

BL', BL'1 to BL'K Second bit line signal

FGT2 Second Floating Gate Transistor

WLT2 Second word line transistor

40 memory array

W1 to WM characters

5001 to 500N, 6001 to 600N, additional storage unit

8001 to 800N, 9001 to 900N

510, 610, 810, 910 First additional capacitive element

520 Second additional capacitive element

AFGT Additional Floating Gate Transistor

AWLT Additional Word Line Transistor

detailed description

FIG. 1 is a schematic diagram of a memory device 10 according to an embodiment of the present invention. The storage element 10 includes a first storage unit 100 and a first voltage transmission device 130 . The first memory cell 100 includes a first floating gate transistor FGT1 , a first word line transistor WLT1 , a first capacitive element 110 and a second capacitive element 120 . The first voltage transmission device 130 may output a voltage according to the operation of the storage element 10 .

The first floating gate transistor FGT1 has a first terminal, a second terminal and a floating gate. The first terminal of the first floating gate transistor FGT1 can receive the first bit line signal BL. The word line transistor WLT1 has a first terminal, a second terminal and a control terminal. The first end of the word line transistor WLT1 is coupled to the second end of the first floating gate transistor FGT1, the second end of the word line transistor WLT1 receives the third voltage GND, and the control end of the word line transistor WLT1 can receive the word line Signal WL.

The first capacitive element 110 is coupled to the first voltage transmission device 130 and the floating gate of the first floating gate transistor FGT1 . The first capacitive element 110 can receive the first control signal CS1 and the voltage output by the first voltage transmission device 130 . The second capacitive element 120 is coupled to the floating gate of the first floating gate transistor FGT1 and can receive the second control signal CS2. The first voltage transmission device 130 can output different voltages during different operations of the storage element 10 and can help prevent the first storage unit 100 from being written or erased.

FIG. 2 is a top view of the layout of the memory device 10 according to an embodiment of the present invention. In FIG. 2 , the first capacitive element 110 and the first voltage transmission device 130 are substantially disposed in the active region AA1 of the first N-well region NW1 . The first floating gate transistor FGT1 and the first word line transistor WLT1 are partially disposed in the active region AA2 of the P well region PW1 adjacent to the first N well region NW1, and the second capacitive element 120 is substantially disposed In the active region AA3 of the second N-well region NW2 adjacent to the P-well region PW1. The active areas AA1 , AA2 , and AA3 may include doped areas for forming the required transistor architecture of the memory device 10 . The floating gate FG1 of the first floating gate transistor FGT1 extends to the first N-well region NW1 and the second N-well region NW2 to be coupled to the first capacitive element 110 and the second capacitive element 120 . The first capacitive element 110 can directly receive the first control signal CS1 from the first N-well region NW1 , and the second capacitive element 120 can directly receive the second control signal CS2 from the second N-well region.

In FIG. 2 , the area of the floating gate FG1 above the first capacitive element 110 is larger than the area of the floating gate FG1 above the second capacitive element 120 . However, in other embodiments of the present invention, the area ratio of the floating gate FG1 above the first capacitive element 110 and the second capacitive element 120 can also be adjusted according to the requirements of the system, so as to improve the writing operation and/or Efficiency of purge operations.

FIG. 3 is a schematic structural diagram of the first capacitive element 110 and the first voltage transmission device 130 in FIG. 2 . In FIG. 3 , the first capacitive element 110 has a first terminal, a second terminal, a control terminal and a base. The first terminal and the second terminal of the first capacitive element 110 can be coupled to the first voltage transmission device 130, and the control terminal of the first capacitive element 110 can be coupled to the floating gate of the first floating gate transistor FGT1 FG1. The base of the first capacitive element 110 can be a part of the first N-well region NW1 and can receive the first control signal CS1.

The first voltage transmission device 130 includes a first transmission gate transistor PG1 and a second transmission gate transistor PG2. The first transfer gate transistor PG1 has a first terminal 131 , a second terminal 132 and a control terminal 133 . The first terminal 131 and the second terminal 132 of the first transfer gate transistor PG1 can be P-type doped regions, and the control terminal 133 of the first transfer gate transistor PG1 can be a gate structure. The first terminal 131 of the first transmission gate transistor PG1 can receive the operation inhibit signal INH, the second terminal 132 of the first transmission gate transistor PG1 can be coupled to the first terminal of the first capacitive element 110, and the first transmission gate The control terminal 133 of the pole transistor PG1 can receive the first transfer gate control signal PL.

The second pass gate transistor PG2 has a first terminal 134 , a second terminal 135 and a control terminal 136 . The first terminal 134 and the second terminal 135 of the second transfer gate transistor PG2 can be P-type doped regions, and the control terminal 136 of the second transfer gate transistor PG2 can be a gate structure. The first terminal 134 of the second transfer gate transistor PG2 can be coupled to the second terminal of the first capacitive element 110, and the second terminal 135 of the second transfer gate transistor PG2 can receive the first voltage VPP or the first control signal CS1 , and the control terminal 136 of the second pass gate transistor PG2 can receive the second pass gate control signal PL′.

By controlling the first transfer gate transistor PG1 and the second transfer gate transistor PG2, the first capacitive element 110 can receive different voltages during different operations, so that the capacitance value of the first capacitive element 110 can be adjusted, Furthermore, it is possible to prevent the first storage unit 100 from being written or erased.

Table 1 shows signal voltages received by the first memory unit 100 during different operations according to an embodiment of the present invention.

Table 1

The third voltage GND is less than the fourth voltage VDD, the fourth voltage VDD is less than the fifth voltage VX, the fifth voltage VX is less than the second voltage VZ, and the second voltage VZ is less than the first voltage VPP. For example, the third voltage GND can be the ground voltage, that is, 0V, the second voltage VZ can be 4V, the first voltage VPP can be 10V, the fourth voltage VDD can be 0.5V to 1.2V, and the fifth voltage VX Can be 3V.

In Table 1, the first capacitive element 110 is mainly used for writing operations, and the second capacitive element 120 is mainly used for erasing operations. During the write operation of the first memory cell 100 of the storage element 10, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the first voltage VPP, the first bit line signal BL may be between the fourth Between the voltage VDD and the third voltage GND, the word line signal WL can be between the fourth voltage VDD and the third voltage GND, the operation prohibition signal INH can be the second voltage VZ, and the first transmission gate control signal PL can be is the first voltage VPP, and the second transfer gate control signal PL′ can be the fifth voltage VX.

That is, during the write operation of the first memory cell 100 , the first pass gate transistor PG1 is turned off, and the second pass gate transistor PG2 is turned on. Therefore, the first control signal CS1 received by the first capacitive element 110 and the voltage output by the first voltage transmission device 130 are both the first voltage VPP. The floating gate FG1 is coupled to a high voltage sufficient to generate Fowler Nordheim electron tunneling. In this way, the first storage unit 100 can be written.

During the write inhibit operation of the first memory cell 100, the first control signal CS1 is the first voltage VPP, the second control signal CS2 is the first voltage VPP, and the first bit line signal BL is between the fourth voltage VDD and the third voltage VPP. Between the range of the voltage GND, the word line signal WL is between the fourth voltage VDD and the third voltage GND, the operation prohibition signal INH is the second voltage VZ, the first transmission gate control signal PL is the fifth voltage VX, and The second transfer gate control signal PL' is the first voltage VPP.

That is, during the write-inhibit operation of the first memory cell 100 , the first pass gate transistor PG1 is turned on, and the second pass gate transistor PG2 is turned off. Therefore, the first capacitive element 110 not only receives the first control signal CS1 at the first voltage VPP, but also receives the voltage output by the first voltage transmission device 130 , that is, the second voltage VZ. Since the second voltage VZ is lower than the first voltage VPP, the floating gate FG1 will not be coupled to a high voltage enough to generate electron tunneling injection, and thus the first memory cell 100 will not be written.

In this way, the first transmission gate control signal PL and the second transmission gate control signal PL' can control the first transmission gate transistor PG1 and the second transmission gate transistor PG2 to complete the writing of the first memory cell 100 operation and prohibit write operation. Since the disable operation can be accomplished by using the first voltage transfer device 130, the first word line transistor WLT1 does not need to receive any high voltage. That is, the first word line transistor WLT1 operates at a low voltage, and thus also has a low threshold voltage. For example, the threshold voltage of the word line transistor in the prior art may be about 0.7V, but the threshold voltage of the first word line transistor WLT2 is about 0.3V to 0.4V. In some embodiments of the present invention, the first word line transistor WLT1 can be manufactured by adjusting the thickness of the gate oxide layer, using native devices or implanting well regions. In this way, the reading process of the memory cell can be completed at a low voltage, that is, the third voltage GND and the fourth voltage VDD shown in Table 1. Low voltage operation helps to speed up the reading process and also helps to reduce power consumption.

In some embodiments of the present invention, all storage units in the storage element may be cleared first, so the storage element can control the state of each storage unit through a write operation and a write-inhibit operation. In this case, the purge operation can be considered a reset operation. That is to say, every time before the storage unit is written, each storage unit will be cleared first, and then the write operation will be performed. This type of storage element does not need to disable the erase operation.

However, in some embodiments of the present invention, all storage cells in the storage element may also be written first at the beginning. The storage element can control the state of each storage unit through clearing operation and clearing prohibition operation. In this case, the write operation can be considered a reset operation. Table 2 shows the signal voltages received by the first memory unit 100 during different operations according to another embodiment of the present invention. In Table 2, the first capacitive element 110 is mainly used for erasing operations, and the second capacitive element 120 is mainly used for writing operations.

Table 2

In Table 2, during the clear operation of the first memory cell 100, the first control signal CS1 is the first voltage VPP, the second control signal CS2 is the third voltage GND, and the first bit line signal BL can be the fourth voltage VDD Between the range of the third voltage GND, the word line signal WL can be between the fourth voltage VDD and the third voltage GND, the operation prohibition signal INH is the second voltage VZ, and the first transfer gate control signal PL is the first voltage VPP, and the second transfer gate control signal PL′ can be a fifth voltage VX.

That is, during the clear operation of the first memory cell 100 , the first transfer gate PG1 is turned off, and the second transfer gate PG2 is turned on. In this way, both the first control signal CS1 and the voltage output by the first voltage transmission device 130 are the first voltage VPP. Since the second capacitive element 120 will receive the third voltage GND, the voltage difference between the first capacitive element 110 and the second capacitive element 120 will cause the Founault tunneling effect to release electrons, so the first storage unit 100 will be cleared .

During the erasure inhibit operation of the first memory cell 100, the first control signal CS1 is the first voltage VPP, the second control signal CS2 is the third voltage GND, and the first bit line signal BL can be the fourth voltage VDD to the third voltage Between the range of GND, the word line signal WL can be between the fourth voltage VDD and the third voltage GND, the operation prohibition signal INH is the second voltage VZ, the first transmission gate control signal PL is the fifth voltage VX, and the first transmission gate control signal PL is the fifth voltage VX. The second transfer gate control signal PL' can be a first voltage VPP.

That is, during the erasing inhibit operation of the first memory cell 100 , the first pass gate transistor PG1 is turned on, and the second pass gate transistor PG2 is turned off. Therefore, the first capacitive element 110 not only receives the first control signal CS1 whose voltage is the first voltage VPP, but also receives the voltage output by the first voltage transmission device 130 and whose voltage is the second voltage VZ. Since the second voltage VZ is smaller than the first voltage VPP, the voltage difference between the first capacitive element 110 and the second capacitive element 120 is not enough to generate the tunneling effect, so electrons will not be released from the floating gate, The first storage unit 100 will not be erased. In this way, the first transmission gate control signal PL and the second transmission gate control signal PL' can control the first transmission gate transistor PG1 and the second transmission gate transistor PG2 to complete the clearing operation of the first storage unit 100 and disable clearing. Since the disable operation can be accomplished through the first voltage transmission device 130, the first word line transistor WLT1 does not need to receive a high voltage. That is, the first word line transistor WLT1 may operate at a low voltage and may have a low threshold voltage. Therefore, the read operation of the storage element 10 can be completed at a low voltage, such as the third voltage GND and the fourth voltage VDD shown in Table 2. Low voltage operation helps to speed up the reading process and reduce power consumption.

In some embodiments of the present invention, the storage device may require write-inhibited and erase-inhibited operations. In this case, the storage element may also include a second voltage transmission device coupled to the second capacitive element. FIG. 4 is a schematic diagram of a storage device 20 according to another embodiment of the present invention.

The structures of the storage elements 10 and 20 are similar, but the storage element 20 further includes a second voltage transmission device 230 . The second capacitive element 120 of the storage element 20 can be coupled to the second voltage transmission device 230 and can receive the voltage output by the second voltage transmission device 230 . The second voltage transmission device 230 may output the first voltage VPP during the write operation or the erase operation of the first memory cell 100 , and may output the second voltage VZ during the inhibit operation of the first memory cell 100 . That is to say, if the first voltage transmission device 130 performs the write-inhibit operation according to the signal voltage shown in Table 1, the second voltage transmission device 230 can perform the write-inhibit operation according to the signal voltage shown in Table 2 . In this case, the storage element 20 can complete the prohibit write operation through the first voltage transmission device 130 , and complete the prohibit erase operation through the second voltage transmission device 230 . At the same time, the first word line transistor WLT1 can still operate at a low voltage, so the time and power consumption of the memory element 20 during the read operation can be reduced.

FIG. 5 is a schematic diagram of a storage device 30 according to an embodiment of the present invention. The storage element 30 includes a first storage unit 100 , a second storage unit 300 , a first voltage transmission device 130 and a second voltage transmission device 330 . The structure of the second storage unit 300 is similar to that of the first storage unit 100 , and the difference between them lies in the received signal. The second memory cell 300 includes a second floating gate transistor FGT2 , a second word line transistor WLT2 , a third capacitive element 310 and a fourth capacitive element 320 .

The second voltage transmission device 330 includes a third transmission gate transistor PG3 and a fourth transmission gate transistor PG4. The third pass gate transistor PG3 has a first terminal, a second terminal and a control terminal. The first terminal of the third pass gate transistor PG3 can receive the operation inhibit signal INH, and the control terminal of the third pass gate transistor PG3 can receive the second pass gate control signal PL'.

The fourth pass gate transistor PG4 has a first terminal, a second terminal and a control terminal. The second terminal of the fourth pass gate transistor PG4 can receive the first voltage VPP or the first control signal CS1, and the control terminal of the fourth pass gate transistor PG4 can receive the first pass gate control signal PL.

The third capacitive element 310 may be coupled to the second terminal of the third pass gate transistor PG3 and the first terminal of the fourth pass gate transistor PG4. The third capacitive element 310 can receive the first control signal CS1 and the voltage output by the second voltage transmission device 330 . The fourth capacitive element 320 can receive the second control signal CS2.

In addition, the second floating gate transistor FGT2 has a first terminal, a second terminal and a floating gate FG2. The first terminal of the second floating gate transistor FGT2 can receive the second bit line signal BL′, and the floating gate FG2 of the second floating gate transistor FGT2 can be coupled to the third capacitor 310 and the fourth capacitor. Element 320. The second word line transistor WLT2 has a first terminal, a second terminal and a control terminal. The first end of the second word line transistor WLT2 is coupled to the second end of the second floating gate transistor FG2, the second end of the second word line transistor WLT2 can receive the third voltage GND, and the second word line transistor WLT2 The control terminal can receive the word line signal WL.

In some embodiments of the present invention, the first transfer gate control signal PL and the second transfer gate control signal PL' may be complementary signals. Since the first transfer gate transistor PG1 receives the first transfer gate control signal PL, and the third transfer gate transistor PG3 receives the second transfer gate control signal PL', the first transfer gate transistor PG1 and the third Pass gate transistor PG3 performs a different operation. For example, when the first pass gate transistor PG1 is turned on, the third pass gate transistor PG3 is turned off. In addition, when the first pass gate transistor PG1 is turned off, the third pass gate transistor PG3 is turned on. Similarly, since the second transfer gate transistor PG2 and the fourth transfer gate transistor PG4 receive the second transfer gate control signal PL' and the first transfer gate control signal PL respectively, the timing of turning them off and on will also be different. That is to say, when the floating gate FG1 of the first floating gate transistor FGT1 is written through the second pass gate transistor PG2, the floating gate FG2 of the second floating gate transistor FGT2 will be written through the second pass gate transistor PG2. Three pass gate transistors PG3 are write-inhibited. And when the floating gate FG1 of the first floating gate transistor FGT1 is prohibited from being written by the first transfer gate transistor PG1, the floating gate FG2 of the second floating gate transistor FGT2 will pass through the fourth transfer gate transistor PG1. The gate transistor PG4 is written.

That is to say, after the writing operation of the storage element 30 is completed, the first storage unit 100 and the second storage unit 300 will be in different states. Therefore, the storage element 30 can output differential signals according to system requirements.

Moreover, since the transmission gate transistor can control the output of the high voltage VPP, the first voltage transmission device 130 and the second voltage transmission device 330 can share the same high voltage driving circuit, thereby simplifying the design of the storage element. That is to say, in some embodiments of the present invention, the first voltage transmission device 130 and the second voltage transmission device 330 can be coupled to the same high voltage driving circuit to receive the first voltage VPP generated by the high voltage driving circuit.

FIG. 6 is a schematic diagram of a memory array 40 according to an embodiment of the present invention. The memory array 40 includes M characters W1 to WM, each of which includes K storage elements 301 to 30K. Each storage element has a similar structure to the storage element 30 of FIG. 5 . The M characters W1 to WM can receive different first control signals CS11 to CS1M, different second control signals CS21 to CS2M, different inhibit operation signals INH1 to INHM, and different word line signals WL1 to WLM . Therefore, the M characters W1 to WM can be operated independently.

In addition, the storage elements 301 to 30K in the same character, such as the storage elements in the character W1, will receive different first bit line signals BL1 to BLK, different second bit line signals BL'1 to BL' K, different first transfer gate control signals PL1 to PLK, and different second transfer gate control signals PL′1 to PL′K. Therefore, the memory elements 301 to 30K can also operate independently.

FIG. 7 is a schematic diagram of a storage device 50 according to an embodiment of the present invention. The memory element 50 has a similar structure to the memory element 10 . However, the memory element 50 further includes N additional memory cells 5001 to 500N. The N additional memory cells 5001 to 500N have a similar structure to the first memory cell 100 . Each of the additional memory cells 5001 to 500N includes a first additional capacitive element 510 , a second additional capacitive element 520 , an additional floating gate transistor AFGT and an additional word line transistor AWLT. N is a positive integer. In some embodiments of the present invention, the N first additional capacitive elements 510 , the first capacitive elements 110 and the first voltage transmission device 130 of the N additional storage units 5001 to 500N are all disposed in the same N-well area.

The N first capacitive elements 510 of the N additional memory cells 5001 to 500N have the same structure as the first capacitive element 110 and are arranged in the same N-well region. The N first capacitive elements 510 of the N additional memory cells 5001 to 500N may be connected in series between the second end of the first capacitive element 110 and the first end of the second pass gate transistor PG2 . That is to say, the first end of the additional first capacitive element 510 of the additional storage unit 5001 is coupled to the second end of the first capacitive element 110, and the first end of the additional first capacitive element 510 of the additional storage unit 5002 is coupled to connected to the second terminal of the additional first capacitive element 510 of the additional storage unit 5001, and so on. Finally, the second terminal of the additional first capacitive element 510 of the additional storage unit 500N is coupled to the first terminal of the second pass gate transistor PG2. The additional floating gate transistor AFGT has a first terminal, a second terminal and a floating gate. The first terminal of each additional floating gate transistor AFGT receives the corresponding bit line signal among the bit line signals ABL1 to ABLN, and the floating gate of the additional floating gate transistor AFGT is coupled to the corresponding first additional The capacitive element 510 and the corresponding second additional capacitive element 520 .

The AWLT has a first terminal, a second terminal and a control terminal. The first terminal of the additional word line transistor AWLT is coupled to the second terminal of the additional floating gate transistor AFGT, the second terminal of the additional word line transistor AWLT can receive the third voltage GND, and the control terminal of the additional word line transistor AWLT can be A corresponding word line signal among the word line signals AWL1 to AWLN is received.

Since the voltage can be transmitted between the first additional capacitive element 510 and the first capacitive element 110 through the N-well region, different memory cells can also share the same voltage transmission device, thereby saving required circuit area. For example, in FIG. 7, when the first transfer gate transistor PG1 is turned on, the first additional capacitive elements 510 of the additional storage units 5001 to 500N all receive the prohibition operation signal INH, whose voltage is the second voltage VZ . And when the second transfer gate transistor PG2 is turned on, the first additional capacitive elements 510 of the additional storage units 5001 to 500N all receive the first control voltage CS1 (or the first voltage VPP) through the second transfer gate transistor PG2 .

In some embodiments of the present invention, the N additional floating gate transistors AFGT of the N additional memory cells 5001 to 500N can be controlled by different bit line signals ABL1 to ABLN, and the N additional memory cells 5001 to 500N The N additional word line transistors AWLT can be controlled by different word line signals AWL1 to AWLM. However, in some embodiments, the N additional floating gate transistors AFGT of the N additional memory cells 5001 to 500N may also receive the same bit line signal. The N additional word line transistors AWLT of the N additional memory cells 5001 to 500N can also receive the same word line signal. In this case, the N additional floating gate transistors AFGT of the N additional memory cells 5001 to 500N will operate simultaneously and synchronously, that is, be written to or cleared simultaneously.

FIG. 8 is a schematic diagram of a storage device 60 according to an embodiment of the present invention. The memory element 60 has a similar structure to the memory element 50 . The memory element 60 has N additional memory cells 6001 to 600N instead of the additional memory cells 5001 to 500N. Additional memory cells 6001 to 600N have a similar structure to additional memory cells 5001 to 500N, but have different signal connections.

The first additional capacitive element 610 of the additional memory cells 6001 to 600N has a similar structure to the first capacitive element 110 and is disposed in the same N-well region. The first additional capacitive element 610 of each additional storage unit 6001 to 600N has a first terminal, a second terminal and a control terminal. The first end of the first additional capacitive element 610 is coupled to the first end of the first capacitive element, the second end of the first additional capacitive element 610 is coupled to the first end of the second transfer gate transistor PG2, and the first The control terminal of the additional capacitive element 610 is coupled to the corresponding floating gate of the additional floating gate transistor AFGT.

In FIG. 8, when the first transfer gate transistor PG1 is turned on, the first additional capacitive element 610 of each additional storage unit 6001 to 600N receives the operation inhibit signal INH. In addition, when the second transfer gate transistor PG2 is turned on, the first additional capacitive element 610 of each additional storage unit 6001 to 600N will receive the first control voltage CS1 (or the first voltage VPP). In this case, different memory cells can also share the same voltage transmission device, thereby reducing the required circuit area.

Furthermore, the storage elements 50 and 60 may further include a high-voltage driving circuit to provide all the first voltage VPP required by the storage elements 50 and 60, so that the design of the storage elements can be further simplified.

FIG. 9 is a schematic diagram of a storage element 70 according to an embodiment of the present invention. The storage element 70 includes a first storage unit 100 and a first voltage transmission device 730 . FIG. 10 is a schematic structural diagram of the first capacitive element 110 and the first voltage transmission device 730 .

In FIG. 10, the first voltage transfer means 730 includes a first transfer gate transistor PG1'. The first transfer gate transistor PG1' has a first terminal 731, a second terminal 732 and a control terminal 733. The first terminal 731 and the second terminal 732 of the first transfer gate transistor PG1' can be P-type doped regions, and the control terminal of the first transfer gate transistor PG1' is a gate structure. The first terminal 731 of the first transmission gate transistor PG1' can receive the inhibit control signal INH, the second terminal 732 of the first transmission gate transistor PG1' is coupled to the first terminal of the first capacitive element 110, and the first transmission The control terminal 733 of the gate transistor PG1 ′ can receive the first transmission gate control signal PL.

In this embodiment, the first end of the first capacitive element 110 is coupled to the first voltage transfer device 730, and the control end of the first capacitive element 110 is coupled to the floating ground of the first floating gate transistor FGT1. Gate FG1. The base of the first capacitive element 110 is a part of the first N-well region NW1 and can receive the first control signal CS1. In addition, in FIG. 10 , the second end 112 of the first capacitive element 110 may be a floating P-type doped region. However, in some embodiments, the second end 112 of the first capacitive element 110 can also be implemented as a shallow trench isolation region.

Table 3 shows the received signal voltages of the storage device 70 during different operation periods according to an embodiment of the present invention.

table 3

In Table 3, the first capacitive element 110 is mainly used for writing operations, and the second capacitive element 120 is mainly used for erasing operations. During the writing operation of the first memory cell 100, the first control signal CS1 can be the first voltage VPP, the second control signal CS2 can be the first voltage VPP, and the first bit line signal BL can be between the fourth voltage VDD and the first voltage VPP. Between the ranges of the three voltages GND, the word line signal can be between the fourth voltage VDD and the third voltage GND, the operation prohibition signal INH can be the first voltage VPP, and the first transfer gate control signal PL can be the fifth voltage VX .

That is, during the write operation of the memory cell 100 of the memory element 70, the first transfer gate transistor PG1' is turned on, and the operation inhibit signal INH is at the first voltage VPP. Therefore, the voltage output by the first voltage transmission device 730 is the first voltage VPP, so that the floating gate FG1 is coupled to a high voltage sufficient to generate electron tunneling injection, and the memory cell 100 of the memory element 70 can be written.

During the write inhibit operation of the memory cell 100 of the memory element 70, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the first voltage VPP, and the first bit line signal BL may be between the fourth voltage Between VDD and the third voltage GND, the word line signal can be between the fourth voltage VDD and the third voltage GND, the operation prohibition signal INH can be the second voltage VZ, and the first transmission gate control signal PL can be the first transmission gate control signal PL. Five voltage VX.

That is to say, during the write-inhibit operation of the first memory cell 100 of the storage element 70, the first transfer gate transistor PG1' is turned on, and the operation-inhibit signal INH is at the second voltage VZ at this time. Therefore, the voltage output by the first voltage transmission device 730 is also the second voltage VZ. In this case, the first capacitive element 110 not only receives the first control signal CS1 at the first voltage VPP, but also receives the second voltage VZ output by the first voltage transmission device 730 . Since the second voltage VZ is lower than the first voltage VPP, the floating gate FG1 will not be coupled to a high voltage enough to generate electron tunneling injection, and thus the first memory cell 100 of the memory element 70 will not be written.

In this way, the first transmission gate control signal PL and the operation inhibit signal INH can be used to complete the write operation and write inhibit operation of the storage element. Since the disable operation can be accomplished by the first voltage transmission device 730, the first word line transistor WLT1 does not need to receive any high voltage signal. That is, the first word line transistor WLT1 may operate at a low voltage and have a low threshold voltage. Therefore, the reading process of the storage element 70 can be completed at a low voltage such as the third voltage GND or the fourth voltage VDD shown in Table 3. Low voltage operation helps speed up the reading process and reduces power consumption.

Table 4 shows the received signal voltages of the memory element 70 in different operation periods according to another embodiment of the present invention. In Table 4, the first capacitive element 110 is mainly used for erasing operations, and the second capacitive element 120 is mainly used for writing operations.

Table 4

In Table 4, during the clear operation of the first memory cell 100 of the memory element 70, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the third voltage GND, the first bit line signal BL Can be between the range of the fourth voltage VDD to the third voltage GND, the word line signal can be between the range of the fourth voltage VDD to the third voltage GND, the prohibition operation signal INH can be the first voltage VPP, and the first transmission gate The control signal PL may be a fifth voltage VX.

That is to say, during the erasing operation of the first memory cell 100 of the memory element 70, the first transfer gate transistor PG1' is turned on, and the operation inhibit signal INH is at the first voltage VPP at this time. Therefore, both the first control signal CS1 and the output voltage of the first voltage transmission device 730 are the first voltage VPP. Since the second capacitive element 120 will be coupled to the third voltage GND, the voltage difference between the first capacitive element 110 and the second capacitive element 120 is sufficient to cause electron tunneling to release electrons, and the first capacitive element 70 of the storage element 70 The storage unit 100 can then be erased.

During the erasure inhibit operation of the first memory cell 100 of the storage element 70, the first control signal CS1 may be a first voltage VPP, the second control signal CS2 may be a third voltage GND, and the first bit line signal BL may be connected between the fourth Between the voltage VDD and the third voltage GND, the word line signal can be between the fourth voltage VDD and the third voltage GND, the operation prohibition signal INH can be the second voltage VZ, and the first transfer gate control signal PL can be is the fifth voltage VX.

That is to say, during the erasure inhibit operation of the first memory cell 100 of the memory element 70, the first transfer gate transistor PG1' is turned on, and the operation inhibit signal INH is at the second voltage VZ at this time. Therefore, the first capacitive element 110 not only receives the first control signal CS1 at the first voltage VPP, but also receives the second voltage VZ output by the first voltage transmission device 730 . Since the second voltage VZ is smaller than the first voltage VPP, the voltage difference between the first capacitive element 110 and the second capacitive element 120 will not be enough to cause electron tunneling, so the electrons will not be released, and the first The storage unit 100 will not be erased.

In this way, the first transmission gate control signal PL and the operation prohibition signal INH can be used to complete the clearing operation and the prohibiting clearing operation of the storage element. Since the prohibiting operation can be completed through the first voltage transmission device 730, the first word line transistor WLT1 does not need to receive any high voltage signal. That is, the first word line transistor WLT1 may operate at a low voltage and have a low threshold voltage. Therefore, the reading process of the storage element 70 can be completed at a low voltage such as the third voltage GND or the fourth voltage VDD shown in Table 4. Low voltage operation helps speed up the reading process and reduces power consumption.

In some embodiments of the present invention, the storage device may need to inhibit write operations and inhibit erase operations. In this case, the storage element may further include a second voltage transmission device 230 . The second voltage transmission device 230 can be coupled to the second capacitive element 120 , that is, the storage element 20 as shown in FIG. 4 . In addition, in some embodiments of the present invention, both the first voltage transmission device 130 and the second voltage transmission device 230 in the storage element 20 can be implemented with a structure similar to that of the voltage transmission device 730 . Through the signal voltages listed in Table 3 and Table 4, the prohibit write operation and prohibit erase operation can be completed.

FIG. 11 is a schematic diagram of a storage device 80 according to an embodiment of the present invention. Memory elements 70 and 80 have similar structures. The memory element 80 further includes N additional memory cells 8001 to 800N. N is a positive integer. The N first additional capacitive elements 810 of the N additional storage units 8001 to 800N have the same structure as the first capacitive element 110 , and are all disposed in the same N-well region as the first voltage transmission device 730 .

The N first capacitive elements 810 of the N additional storage units 8001 to 800N may be connected in series with the first capacitive element 110 . That is to say, the first end of the first additional capacitive element 810 of the additional storage unit 8001 is coupled to the second end of the first capacitive element 110, and the first end of the first additional capacitive element 810 of the additional storage unit 8002 is coupled to connected to the second terminal of the first additional capacitive element 810 of the additional storage unit 8001, and so on. In addition, the second terminal of the first additional capacitive element 810 of the additional storage unit 800N may be in a floating state.

In FIG. 11 , when the first transfer gate transistor PG1' is turned on, the first additional capacitive elements 810 of the additional memory cells 8001 to 800N all receive the operation inhibit signal INH. Since the voltage can be transmitted between the N-well regions, different memory cells can also share the same voltage transmission device 730 , thereby saving the required circuit area. In some embodiments of the present invention, the N additional floating gate transistors AFGT of the N additional memory cells 8001 to 800N can be controlled by different bit line signals ABL1 to ABLN, and the N additional memory cells 8001 to 800N The N additional word line transistors AWLT can be controlled by different word line signals AWL1 to AWLN.

However, in some embodiments of the present invention, the N additional floating gate transistors AFGT and the first floating gate transistor FGT1 of the N additional memory cells 8001 to 800N can also receive the same bit line signal BL. Furthermore, the N additional word line transistors AWLT of the N additional memory cells 8001 to 800N may also receive the same word line signal WL as the first word line transistor WLT1. In this case, the additional floating gate transistor AFGT will operate synchronously and simultaneously with the first floating gate transistor FGT1 , that is, be written to or cleared at the same time.

FIG. 12 is a schematic diagram of a storage device 90 according to an embodiment of the present invention. Memory elements 90 and 80 have similar structures. The memory element 90 includes N additional memory cells 9001 to 900N instead of the additional memory cells 8001 to 800N. The N first additional capacitive elements 910 of the additional storage units 9001 to 900N have the same structure as the first capacitive element 110 , and are all disposed in the same N-well region as the first voltage transmission device 730 .

The first additional capacitive element 910 of each additional storage unit 9001 to 900N has a first terminal, a second terminal and a control terminal. The first end of the first additional capacitive element 910 is coupled to the first end of the first capacitive element 110, the second end of the first additional capacitive element 910 can be floated to the second end of the first capacitive element 110, and the first The control terminal of the additional capacitive element 910 is coupled to the corresponding additional floating gate transistor AFGT in the additional memory cells 9001 to 900N.

In FIG. 12, when the first transfer gate transistor PG1' is turned on, the first additional capacitive elements 910 of the additional memory cells 9001 to 900N all receive the operation inhibit signal INH. In this case, different memory units can also share the same voltage transmission device 730 , thereby saving required circuit area.

In addition, the storage elements of the above-mentioned various embodiments may further include a plurality of selection transistors, and each selection transistor may be coupled to a corresponding floating gate transistor to receive a corresponding bit line signal, which may also allow the disabled operation There are elastics for different bias conditions. That is, a floating gate transistor may receive its bitline signal through a corresponding select transistor.

To sum up, the storage element provided by the embodiment of the present invention can perform a prohibition operation through the voltage transmission device. Therefore, the word line transistor can operate at a low voltage and have a low threshold voltage, thereby helping to speed up the reading process of the storage device and reduce computer consumption. In addition, since the transfer gate transistor can control high-voltage signals, the storage elements of the same character or the capacitor elements in the same storage element can share the high-voltage power supply, thereby reducing the circuit area of the storage elements.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (26)

1. A storage element, characterized in that, comprising: a first voltage transmission device for outputting a voltage according to the operation of the memory element; and A first storage unit comprising: a first floating gate transistor having a first terminal for receiving a first bit line signal, a second terminal, and a floating gate; and The first capacitive element has a first end coupled to the first voltage transmission device, a second end, and a control end coupled to the floating gate of the first floating gate transistor, and a base for receiving a first control signal; in: Both the first capacitive element and the first voltage transmission device are disposed in the first N-well region; During the writing operation or erasing operation of the first storage unit, the first terminal of the first capacitive element receives the first voltage output by the first voltage transmission device; The first end of the first capacitive element receives a second voltage output by the first voltage transmission means during a disabled operation of the first memory cell; and The first voltage is greater than the second voltage. 2. The memory device according to claim 1, wherein the first voltage transmission means comprises a first transmission gate transistor having a first terminal for receiving an operation prohibition signal, and a second terminal coupled to the first transmission gate transistor. The first end and the control end of a capacitive element are used for receiving transmission gate control signals. 3. The memory element according to claim 2, characterized in that: During the write operation of the first memory cell, the first control signal is at the first voltage, and the first bit line signal is in a range from a fourth voltage to a third voltage, so the disable operation signal is at the first voltage, the transfer gate control signal is at a fifth voltage, and the first terminal of the first transfer gate transistor receives the first voltage; During the write-inhibit operation of the first memory cell, the first control signal is at the first voltage, and the first bit line signal is at all voltages between the fourth voltage and the third voltage. In the above range, the operation inhibit signal is at the second voltage, the transfer gate control signal is at the fifth voltage, and the first terminal of the first transfer gate transistor receives the the second voltage; and The third voltage is less than the fourth voltage, the fourth voltage is less than the fifth voltage, and the fifth voltage is less than the second voltage. 4. The storage element according to claim 3, wherein the first storage unit further comprises: The first word line transistor has a first end coupled to the second end of the first floating gate transistor, the second end is used to receive the third voltage, and the control end is used to receive the word line signal ; in: during the write operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage; and During the write-inhibit operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage. 5. The memory element of claim 4, wherein the first word line transistor has a low threshold voltage. 6. The storage element according to claim 3, wherein the first storage unit further comprises: a second capacitive element, coupled to the floating gate of the first floating gate transistor, and used to receive at least one second control signal; in: during the write operation of the first memory cell, the second control signal is at the first voltage; and During the write inhibit operation of the first memory cell, the second control signal is at the first voltage. 7. The memory element of claim 2, wherein: During the clear operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is in a range from a fourth voltage to a third voltage, the an inhibit operation signal is at the first voltage, the transfer gate control signal is at a fifth voltage, and the first terminal of the first transfer gate transistor receives the first voltage; During the inhibit erase operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is at the voltage between the fourth voltage and the third voltage range, the disable operation signal is at the second voltage, the transfer gate control signal is at the fifth voltage, and the first terminal of the first transfer gate transistor receives the first two voltages; and The third voltage is less than the fourth voltage, the fourth voltage is less than the fifth voltage, and the fifth voltage is less than the second voltage. 8. The storage element according to claim 7, wherein the first storage unit further comprises: The first word line transistor has a first end coupled to the second end of the first floating gate transistor, the second end is used to receive the third voltage, and the control end is used to receive the word line signal ; in: during the clear operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage; and During the inhibit erase operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage. 9. The memory element of claim 8, wherein the first word line transistor has a low threshold voltage. 10. The storage element according to claim 7, wherein the first storage unit further comprises: a second capacitive element, coupled to the floating gate of the first floating gate transistor, and used to receive at least one second control signal; in: during the clear operation of the first memory cell, the second control signal is at the third voltage; and During the inhibit clear operation of the first memory cell, the second control signal is at the third voltage. 11. The memory element according to claim 1, wherein said first voltage transfer means comprises: The first transmission gate transistor has a first terminal for receiving an operation prohibition signal, a second terminal coupled to the first terminal of the first capacitive element, and a control terminal for receiving a first transmission gate control signal ;and The second transfer gate transistor has a first terminal coupled to the second terminal of the first capacitive element, the second terminal is used for receiving the first voltage or the first control signal, and the control terminal is used for to receive the second transmission gate control signal. 12. The memory element of claim 11, wherein: During the write operation of the first memory cell, the first control signal is at the first voltage, and the first bit line signal is in a range from a fourth voltage to a third voltage, so the disable operation signal is at the second voltage, the first transfer gate control signal is at the first voltage, and the second transfer gate control signal is at a fifth voltage; During the write-inhibit operation of the first memory cell, the first control signal is at the first voltage, and the first bit line signal is at all voltages between the fourth voltage and the third voltage. Within the stated range, the operation inhibit signal is at the second voltage, the first transfer gate control signal is at the fifth voltage, and the second transfer gate control signal is at the first voltage; and The third voltage is less than the fourth voltage, the fourth voltage is less than the fifth voltage, and the fifth voltage is less than the second voltage. 13. The storage device according to claim 12, wherein the first storage unit further comprises: The first word line transistor has a first end coupled to the second end of the first floating gate transistor, the second end is used to receive the third voltage, and the control end is used to receive the word line signal ; in: during the write operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage; and During the write-inhibit operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage. 14. The storage device according to claim 12, wherein said first storage unit further comprises: a second capacitive element, coupled to the floating gate of the first floating gate transistor, and used to receive at least one second control signal; in: during the write operation of the first memory cell, the second control signal is at the first voltage; and During the write inhibit operation of the first memory cell, the second control signal is at the first voltage. 15. The memory element of claim 11, wherein: During the clear operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is in a range from a fourth voltage to a third voltage, the an inhibit operation signal is at the second voltage, the first transfer gate control signal is at the first voltage, and the second transfer gate control signal is at a fifth voltage; During the inhibit erase operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is at the voltage between the fourth voltage and the third voltage range, the disable operation signal is at the second voltage, the first transfer gate control signal is at the fifth voltage, and the second transfer gate control signal is at the first voltage ;and The third voltage is less than the fourth voltage, the fourth voltage is less than the fifth voltage, and the fifth voltage is less than the second voltage. 16. The storage device according to claim 15, wherein the first storage unit further comprises: The first word line transistor has a first end coupled to the second end of the first floating gate transistor, the second end is used to receive the third voltage, and the control end is used to receive the word line signal ; in: during the write operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage; and During the write-inhibit operation of the first memory cell, the word line signal is within the range of the fourth voltage to the third voltage. 17. The storage device according to claim 15, wherein the first storage unit further comprises: a second capacitive element, coupled to the floating gate of the first floating gate transistor, and used to receive at least one second control signal; in: during the write operation of the first memory cell, the second control signal is at the first voltage; and During the write inhibit operation of the first memory cell, the second control signal is at the first voltage. 18. The memory element of claim 11, wherein: The first storage unit further includes: A first word line transistor having a first end coupled to the second end of the first floating gate transistor, a second end for receiving a third voltage, and a control end for receiving a word line signal; and a second capacitive element, coupled to the floating gate of the first floating gate transistor, and used to receive at least one second control signal; and The storage element further includes: The second voltage transmission device includes: a third transfer gate transistor having a first terminal for receiving the operation inhibit signal, The second end, and the control end are used to receive the second transfer gate control signal; and the fourth transfer gate transistor has a first end, and the second end is used to receive the first voltage or the first control signal signal, and the control terminal is used to receive the first transmission gate control signal; and a second storage unit comprising: A third capacitive element, coupled to the second end of the third transfer gate transistor and the first end of the fourth transfer gate transistor, and used to receive the first control signal and the the voltage output by the second voltage transmission device; a fourth capacitive element, configured to receive the second control signal; a second floating gate transistor having a first terminal for receiving a second bit line signal, a second terminal, and a floating gate coupled to the third capacitive element and the fourth capacitive element; and The second word line transistor has a first end coupled to the second end of the second floating gate transistor, the second end is used to receive the third voltage, and the control end is used to receive the third voltage. the word line signal. 19. The memory element according to claim 1, further comprising: N additional storage units, each additional storage unit includes: a first additional capacitive element; a second additional capacitive element; The additional floating gate transistor has a first terminal for receiving a corresponding bit line signal, a second terminal, and a floating gate coupled to the first additional capacitance element and the second additional capacitance components; and An additional word line transistor having a first terminal coupled to the second terminal of the additional floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a corresponding word line signal; Where N is a positive integer. 20. The memory element of claim 19, wherein: The first voltage transmission device includes a first transmission gate transistor having a first terminal for receiving an operation prohibition signal, a second terminal coupled to the first terminal of the first capacitive element, and a control terminal for receiving a transmit gate control signal; and The N first additional capacitive elements of the N additional storage units are connected with the first capacitive elements connected in series. 21. The memory element of claim 19, wherein: The first voltage transmission device includes a first transmission gate transistor having a first terminal for receiving an operation prohibition signal, a second terminal coupled to the first terminal of the first capacitive element, and a control terminal for receiving a transmit gate control signal; and The first additional capacitive element has a first end coupled to the first end of the first capacitive element, a second end coupled to the second end of the first capacitive element, and a control end coupled to the first end of the first capacitive element. connected to the floating gate of the additional floating gate transistor. 22. The memory element of claim 19, wherein: The first voltage transmission device includes: The first transmission gate transistor has a first terminal for receiving an operation prohibition signal, a second terminal coupled to the first terminal of the first capacitive element, and a control terminal for receiving a first transmission gate control signal ;and a second transfer gate transistor having a first terminal, a second terminal for receiving the first voltage or the first control signal, and a control terminal for receiving a second transfer gate control signal; and The N first additional capacitive elements of the N additional storage units are connected in series with the first capacitor between the second terminal of the element and the first terminal of the second transfer gate transistor. 23. The memory element of claim 19, wherein: The first voltage transmission device includes: The first transmission gate transistor has a first terminal for receiving an operation prohibition signal, a second terminal coupled to the first terminal of the first capacitive element, and a control terminal for receiving a first transmission gate control signal ;and a second transfer gate transistor having a first terminal, a second terminal for receiving the first voltage or the first control signal, and a control terminal for receiving a second transfer gate control signal; and The first additional capacitive element has a first end coupled to the first end of the first capacitive element, a second end coupled to the first end of the second transfer gate transistor, and a control terminal coupled to the floating gate of the additional floating gate transistor. 24. The memory element of claim 1, further comprising: second voltage transmission means for outputting the first voltage during the writing operation or the erasing operation of the first memory cell, and outputting the prohibition operation of the first memory cell said second voltage; and The second capacitive element is coupled to the floating gate of the first floating gate transistor and the second voltage transmission device, and is used for receiving the voltage output by the second voltage transmission device. 25. A memory array, comprising: At least one column of storage elements, each storage element of the same column comprising: The first voltage transmission device is used to receive the operation prohibition signal and output the voltage according to the first transmission gate control signal; a second voltage transmission device, configured to receive the operation prohibition signal, and output a voltage according to the second transmission gate control signal; A first storage unit, comprising: The first floating gate transistor has a first terminal for receiving the first bit line signal, a second terminal, and a floating gate; The first capacitive element has a first terminal coupled to the first voltage transmission device, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a base for to receive a first control signal; A first word line transistor having a first end coupled to the second end of the first floating gate transistor, a second end for receiving a third voltage, and a control end for receiving a word line signal; and a second capacitive element, coupled to the floating gate of the first floating gate transistor, and used to receive a second control signal; and a second storage unit comprising: The second floating gate transistor has a first terminal for receiving the second bit line signal, a second terminal, and a floating gate; The third capacitive element has a first terminal coupled to the second voltage transmission device, a second terminal, a control terminal coupled to the floating gate of the second floating gate transistor, and a base for to receive the first control signal; The second word line transistor has a first terminal coupled to the second terminal of the second floating gate transistor, a second terminal for receiving the third voltage, and a control terminal for receiving the character line signal; and a fourth capacitive element, coupled to the floating gate of the second floating gate transistor, and used to receive the second control signal; in: A plurality of storage elements located in the same column receive the same operation inhibit signal, the same first control signal, the same second control signal, and the same word line signal; and The plurality of storage elements in the same column receive a plurality of different first bit line signals, a plurality of different second bit line signals, and a plurality of different first transfer gate control signals, and a plurality of different second transmission gate control signals. 26. The memory array of claim 25, wherein: A plurality of storage elements in different columns receive a plurality of different prohibition signals, a plurality of different first control signals, a plurality of different second control signals, and a plurality of different word line signals; and A plurality of storage elements located in different columns and in the same row receive the same first bit line signal, the same second bit line signal, the same first transfer gate control signal, and the same second transfer gate control signal .