CN107153308B

CN107153308B - Array substrate and manufacturing method

Info

Publication number: CN107153308B
Application number: CN201710464019.5A
Authority: CN
Inventors: 林碧芬; 甘启明
Original assignee: Shenzhen China Star Optoelectronics Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd
Priority date: 2017-06-19
Filing date: 2017-06-19
Publication date: 2020-08-28
Anticipated expiration: 2037-06-19
Also published as: CN107153308A

Abstract

The invention provides an array substrate which comprises a substrate, a plurality of scanning lines, an active layer arranged on the scanning lines, a plurality of data lines arranged in a staggered mode with the scanning lines, a drain electrode in contact with the active layer, a passivation layer formed on the drain electrode and a pixel electrode formed on the passivation layer. The invention also provides a manufacturing method of the array substrate. Compared with the prior art, the scanning line holes are formed in the positions, staggered with the data lines, of the scanning lines, so that the overlapping area of the scanning lines and the data lines is reduced, the parasitic capacitance is reduced, the influence of vacuum voltage on panel display is reduced, and the resistance value of the scanning lines is kept unchanged while the aperture opening ratio of the pixel electrodes is improved.

Description

Array substrate and manufacturing method

Technical Field

The invention relates to a liquid crystal display panel technology, in particular to an array substrate and a manufacturing method thereof.

Background

Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, and are widely used, for example: liquid crystal televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens, notebook computer screens, or the like, are dominant in the field of flat panel displays.

A Thin Film Transistor (TFT) lcd is the most common lcd in the mainstream market at present, and a light-shielding structure design is generally adopted in the TFT pixel design to reduce the problem of large leakage current influence caused by backlight illumination; one disadvantage of the light-shielding structure is large parasitic capacitance, resulting in large feed through voltage, which results in signal error writing. At present, a large-size panel requires that the line width of a scan line is as large as possible to normally drive the panel, but this may increase the parasitic capacitance of a data line and the scan line, and cause RC Delay (that is, Delay time caused by increase of capacitance and resistance), which may cause an abnormal problem of a flash screen (Flicker).

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides the array substrate and the manufacturing method thereof, so that the overlapping area of the data line and the scanning line is reduced, and the influence of the vacuum voltage on the display of the panel is reduced by reducing the parasitic capacitance.

The invention provides an array substrate, which comprises a substrate, a plurality of scanning lines, an active layer arranged on the scanning lines, a plurality of data lines arranged in a staggered manner with the scanning lines, a drain electrode in contact with the active layer, a passivation layer formed on the drain electrode and a pixel electrode formed on the passivation layer, wherein the pixel electrode is connected with the drain electrode through a through hole positioned on the passivation layer; and scanning line holes are respectively formed in the scanning lines at the positions where the data lines are staggered, one part of the line bodies is overlapped with the scanning line holes in the part of the line bodies staggered with the scanning lines on the data lines, and the other part of the line bodies is overlapped with the active layer and is mutually overlapped.

Furthermore, at least one part of the line body occupying half of the line width of the line body is partially overlapped with the scanning line holes, and the rest part of the line body is partially overlapped and lapped with the active layer.

Furthermore, at least one side edge of the active layer is aligned with one side edge of the scanning line hole at the line body.

Further, the scanning line hole is a rectangular hole.

Further, the length of the first edge of the via hole in the scan line hole, which is the same as the extending direction of the data line, is equal to the length of the first edge of the active layer, which is the same as the extending direction of the data line, in the active layer; the length of a second edge of the through hole, which is perpendicular to the first edge of the through hole, in the data line is at least twice of the line width of the data line.

Further, a part of the line body occupying two thirds of the line width of the line body is partially overlapped with the scanning line hole.

Further, a widening portion is arranged between adjacent data lines on the scanning line.

The invention also provides a manufacturing method of the array substrate, which comprises the following steps:

step S01, providing a substrate, manufacturing a gate electrode layer on the surface of the substrate and patterning to form a scanning line;

step S02, manufacturing a scanning line hole on the scanning line along the length direction of the scanning line;

step S03, manufacturing a gate insulation layer on the scanning line;

step S04, respectively manufacturing active layers beside each scanning line hole on the grid insulation layer;

step S05, manufacturing a data line and a drain electrode which are arranged in a staggered mode with the scanning line on the grid electrode insulating layer respectively, wherein the drain electrode is in contact with the active layer, one part of line bodies of the line bodies is overlapped with the scanning line holes in the part of line bodies which are arranged on the data line in the staggered mode with the scanning line, and the other part of line bodies of the line bodies is overlapped with the active layer and is mutually overlapped;

step S06, manufacturing a passivation layer on the data line and the drain electrode, and manufacturing a via hole on the passivation layer at the drain electrode;

and step S07, manufacturing a pixel electrode on the passivation layer, wherein the pixel electrode is in contact with the drain electrode through the via hole on the passivation layer.

Further, in step S05, at least a portion of the line body occupying half of the line width of the line body overlaps with the scanning line hole, and the remaining portion of the line body overlaps and overlaps with the active layer.

Further, in step S05, at least one side edge of the active layer is aligned with one side edge of the scan line hole at the line body.

Compared with the prior art, the invention reduces the overlapping area of the scanning line and the data line by arranging the scanning line hole at the position of the scanning line which is staggered with the data line, thereby reducing the parasitic capacitance and further reducing the influence of vacuum voltage on the display of the panel, and keeping the resistance value of the scanning line unchanged while improving the aperture opening ratio of the pixel electrode.

Drawings

FIG. 1-1 is a top view of an array substrate of the present invention;

FIG. 1-2 is a cross-sectional view taken along A-A of FIG. 1;

FIG. 2-1 is a top view of the present invention making a scan line;

FIG. 2-2 is a cross-sectional view taken along line B-B of FIG. 2-1;

FIG. 3-1 is a top view of the present invention for fabricating an active layer;

FIG. 3-2 is a cross-sectional view taken along the direction C-C of FIG. 3-1;

FIG. 4-1 is a top view of the present invention for fabricating a data line and a drain electrode;

FIG. 4-2 is a cross-sectional view taken along D-D of FIG. 4-1;

FIG. 5-1 is a top view of the passivation layer made by the present invention;

FIG. 5-2 is a cross-sectional view taken along the direction E-E of FIG. 5-1;

FIG. 6 is a flow chart of a method of making the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Only the positional relationship of the devices relevant to the present invention is shown in fig. 1-1, 2-1, 3-1, 4-1, 5-1.

As shown in fig. 1-1 and 1-2, an array substrate according to the present invention includes a substrate 1, a plurality of scan lines (gate lines) 2, an active layer 3 disposed on the scan lines 2, a plurality of data lines 4 disposed alternately with the scan lines 2, a drain electrode 5 contacting the active layer 3, a passivation layer 6 formed on the drain electrode 5, and a pixel electrode 7 formed on the passivation layer 6; a gate insulating layer 12 is arranged between the scanning line 2 and the active layer 3, and the pixel electrode 7 is connected with the drain electrode 5 through a via hole on the passivation layer 6; the scanning lines 2 and the data lines 4 are respectively provided with scanning line holes 8 at staggered positions, one part of line body 9 of the data lines 4 and the scanning lines 2 are staggered in the line body 9 (the dotted line part in fig. 1-1 is the part overlapped with the scanning line holes 8), one part of line body of the line body 9 is overlapped with the scanning line holes 8, and the other part of line body of the line body 9 is overlapped with the active layer 3 and is mutually overlapped, so that the line width of the scanning lines 2 is changed, the area overlapped with the data lines is reduced, the parasitic capacitance is reduced, and the influence of vacuum voltage on the display panel is reduced.

In the invention, at least a part of the line body occupying half of the line width of the line body 9 is partially overlapped with the scanning line hole 8, and the rest part of the line body 9 is partially overlapped and lapped with the active layer 3, thereby further reducing the overlapping area of the scanning line and the data line, specifically, the part of the line body occupying two thirds of the line width of the line body 9 in the line body 9 is partially overlapped with the scanning line hole 8, so that the normal work of the thin film transistor can be ensured.

As an embodiment of the present invention, at least one side edge of the active layer 3 is aligned with one side edge of the scanning line hole 8 at the line body 9, so as to ensure that the data line and the active layer can overlap and overlap, and the overlapping area with the scanning line 2 becomes small, thereby ensuring that the scanning line can also play a role of shading light.

In the present invention, the scan line hole 8 is a rectangular hole (shown in fig. 2-1), and specifically, the scan line hole 8 has two via first edges 10 that are opposite to and in the same extending direction as the data line 4, and two via second edges 13 that are perpendicular to and opposite to the via first edges 10; wherein, the length of the first edge 10 of the via hole under the data line 4 is equal to the length of the first edge 11 (shown in fig. 3-1) of the active layer 3, which extends in the same direction as the data line 4; the length of the second edge 13 of the via hole is at least twice the line width of the data line 4.

As shown in fig. 1-1 and fig. 2-1, in order to make the resistance value of the scan line constant, a widening portion 14 is provided between adjacent data lines 4 on the scan line 2, so that two side edges of the scan line 2 form a rectangular tooth-shaped structure; the active layer 3 corresponds in position to the widening 14.

As shown in fig. 6, the method for manufacturing an array substrate of the present invention includes the following steps:

step S01, providing a substrate 1, fabricating a gate electrode layer on a surface of the substrate 1 and patterning the gate electrode layer to form a scan line (gate line) 2 (shown in fig. 2-1 and 2-2), specifically, depositing the gate electrode layer by magnetron sputtering or the like, and patterning the gate electrode layer by photolithography and etching processes to form the scan line 2;

the gate electrode layer is made of molybdenum aluminum alloy, chromium metal and molybdenum metal, and can also be made of a material with a light shielding function and conductivity, which is not particularly limited herein;

step S02, manufacturing a scanning line hole 8 on the scanning line 2 along the length direction of the scanning line 2, wherein the scanning line hole 8 can be formed by adopting the photoetching and etching process in the prior art;

step S03, forming a gate insulating layer 12 (shown in fig. 3-2) on the scan line 2, and forming the gate insulating layer 12 by using a conventional deposition process;

step S04, respectively fabricating an active layer 3 (shown in fig. 3-1 and 3-2) on the gate insulating layer 12 beside each scan line hole 8, specifically, the active layer 3 is made of amorphous silicon, metal oxide, polysilicon, or the like; etching away the rest active layers 3 except the active layer 3 beside the scanning line control 8 by the photoetching and etching process in the prior art;

step S05, respectively manufacturing a data line 4 and a drain electrode 5 (shown in fig. 4-1 and 4-2) on the gate insulating layer 12, the data line 4 and the drain electrode 5 being interlaced with the scan line 2, specifically, the drain electrode 5 is in contact with the active layer 3, a part of line bodies 9 on the data line 4, which are interlaced with the scan line 2, overlap the scan line hole 8, and another part of line bodies 9 overlap the active layer 3 and overlap each other;

the data line 4 and the drain electrode 5 are made of molybdenum aluminum alloy, chromium metal, molybdenum metal, or a material having a light shielding function and a conductive property, which is not specifically limited herein;

step S06, forming a passivation layer 6 on the data line 4 and the drain electrode 5, and forming a via hole (shown in fig. 5-1 and 5-2) on the passivation layer 6 at the drain electrode 5, wherein the via hole is formed by using the existing photolithography and etching processes;

step S07, a pixel electrode 7 (shown in fig. 1-1 and 1-2) is fabricated on the passivation layer 6, and the pixel electrode 7 contacts the drain electrode 5 through the via hole on the passivation layer 6.

In step S05, at least a portion of the line body occupying half of the line width of the line body 9 overlaps the scanning line hole 8, and the remaining portion of the line body 9 overlaps and overlaps the active layer 3, so as to further reduce the overlapping area of the scanning line and the data line, and specifically, a portion of the line body occupying two-thirds of the line width of the line body 9 overlaps the scanning line hole 8, so that the thin film transistor can be ensured to operate normally.

At least one side edge of the active layer 3 in step S05 is aligned with one side edge of the scan line hole 8 at the position of the line body 9 (as shown in fig. 3-1), so as to ensure that the data line and the active layer can overlap and overlap, and the overlapping area with the scan line 2 becomes small, which also ensures that the scan line can shield light.

In addition to the above steps, the manufacturing method of the present invention should also be understood to include other conventional manufacturing steps for preparing an array substrate, and the above description is only directed to the improvement of the present invention.

The invention reduces the overlapping area of the data line, the active layer and the scanning line by changing partial line width of the scanning line, thereby reducing the parasitic capacitance of the pixel, and keeping the resistance value of the scanning line unchanged while improving the aperture opening ratio of the pixel.

While the invention has been shown and described with reference to certain embodiments, those skilled in the art will understand that: various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

Claims

1. An array substrate, comprising: the pixel structure comprises a substrate (1), a plurality of scanning lines (2), an active layer (3) arranged on the scanning lines (2), a plurality of data lines (4) arranged in a staggered manner with the scanning lines (2), a drain electrode (5) contacted with the active layer (3), a passivation layer (6) formed on the drain electrode (5) and a pixel electrode (7) formed on the passivation layer (6), wherein the pixel electrode (7) is connected with the drain electrode (5) through a via hole on the passivation layer (6), and the projection of the drain electrode (5) on the substrate (1) is positioned in the projection of the scanning lines (2) on the substrate (1); the scanning line (2) is provided with scanning line holes (8) at the positions where the data lines (4) are staggered, one part of line bodies of the line bodies (9) is overlapped with the scanning line holes (8) in the part of line bodies (9) on the data lines (4) where the data lines (2) are staggered, the other part of line bodies of the line bodies (9) is overlapped with the active layer (3) and is mutually overlapped, and the edges of the active layer (3) parallel to the data lines (4) are aligned with the edges of the scanning line holes (8) parallel to the data lines (4).

2. The array substrate of claim 1, wherein: at least the part of the line body occupying half of the line width of the line body (9) is partially overlapped with the scanning line hole (8), and the rest part of the line body (9) is partially overlapped and lapped with the active layer (3).

3. The array substrate of claim 1 or 2, wherein: the scanning line hole (8) is a rectangular hole.

4. The array substrate of claim 3, wherein: the length of a first via hole edge (10) in the scanning line hole (8) in the same extending direction as the data line (4) is equal to the length of a first active layer edge (11) in the active layer (3) in the same extending direction as the data line (4); and the length of a via hole second edge (13) perpendicular to the via hole first edge (10) in the data line (4) is at least twice of the line width of the data line (4).

5. The array substrate of claim 2, wherein: and the part of the line body (9) occupying two thirds of the line width of the line body (9) is partially overlapped with the scanning line hole (8).

6. The array substrate of claim 1, wherein: and a widening part (14) is arranged between the adjacent data lines (4) on the scanning line (2).

7. A manufacturing method of an array substrate is characterized in that: the method comprises the following steps:

step S01, providing a substrate (1), manufacturing a gate electrode layer on the surface of the substrate (1) and patterning to form a scanning line (2);

step S02, manufacturing a scanning line hole (8) on the scanning line (2) along the length direction of the scanning line (2);

step S03, manufacturing a gate insulation layer (12) on the scanning line (2);

step S04, respectively manufacturing an active layer (3) on the grid insulation layer (12) beside each scanning line hole (8);

step S05, respectively manufacturing a data line (4) and a drain electrode (5) which are arranged in a staggered manner with a scanning line (2) on a gate insulating layer (12), wherein the drain electrode (5) is in contact with an active layer (3), the projection of the drain electrode (5) on the substrate (1) is positioned in the projection of the scanning line (2) on the substrate (1), one part of line body of the line body (9) is overlapped with the scanning line hole (8) in the part of line body (9) which is arranged on the data line (4) in a staggered manner with the scanning line (2), the other part of line body of the line body (9) is overlapped with the active layer (3) and is mutually overlapped, and the edge of the active layer (3) which is parallel to the data line (4) is aligned with the edge of the scanning line hole (8) which is parallel to the data line (4);

step S06, manufacturing a passivation layer (6) on the data line (4) and the drain electrode (5), and manufacturing a through hole on the passivation layer (6) at the position of the drain electrode (5);

and step S07, manufacturing a pixel electrode (7) on the passivation layer (6), wherein the pixel electrode (7) is in contact with the drain electrode (5) through a via hole on the passivation layer (6).

8. The method of manufacturing according to claim 7, wherein: in the step S05, at least a portion of the line body that occupies half of the line width of the line body (9) overlaps with the scanning line hole (8), and the rest of the line body (9) overlaps and overlaps with the active layer (3).