CN107134925B - A kind of adaptive segmentation slope compensation circuit suitable for buck converter - Google Patents

Abstract

A kind of adaptive segmentation slope compensation circuit suitable for buck converter, belongs to electronic circuit technology field.Pass through first switch signal clk₁With second switch signal clk₂Duty ratio size is divided into three sections, and slope compensation is carried out to buck converter according to different hill slopes respectively in three sections, make the dynamics of slope compensation circuit both can subharmonic concussion after anti-loops undercompensation, it can also be to avoid making loop load capacity and response speed be deteriorated after overcompensation, the information of buck converter input voltage vin is introduced simultaneously, to allow slope compensation adaptively to adjust, the application suitable for wide input range with the variation range of input voltage.

Description

An Adaptive Segmented Slope Compensation Circuit for Buck Converter

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to an adaptive subsection slope compensation circuit suitable for a step-down buck converter in a wide input variation range.

Background technique

The peak current mode step-down Buck converter is favored by people because of its simple loop compensation, and higher linear regulation rate and load regulation rate. Figure 1 is the architecture diagram of the peak current mode. The error signal of the output voltage and the reference voltage becomes the negative terminal input of the PWM comparator through the error amplifier (EA), which is compared with the sampled inductor current to generate a PWM with a certain duty cycle. The waveform is used to drive the switching tube to realize the charging and discharging of the inductor to stabilize the output voltage. However, the peak current mode has the problem of sub-harmonic oscillation when the duty cycle is greater than 0.5. As shown in Figure 2, assuming that at the beginning of a switching cycle, the inductor current has a small disturbance ΔI ₀ , when the duty ratio is less than 0.5, the disturbance of the inductor current gradually becomes smaller; when the duty ratio is greater than 0.5, the inductor current The current disturbance will become larger and larger, resulting in sub-harmonic oscillations.

Adding slope compensation circuit can solve sub-harmonic oscillation. As shown in Figure 3, the slope signal is superimposed before the sampling current and voltage feedback comparison. When the sampled information and the slope voltage are superimposed, the Vc limit of the EA output is touched, and the PWM comparator is reversed. The slope of the slope compensation is very critical. If the slope is too small, sub-harmonic oscillation cannot be avoided. If the slope is too large, it will be closer to the voltage mode and lose the characteristics of fast response. In the case of a wide input range, the duty cycle can vary widely. If the traditional fixed slope compensation is used, the maximum duty cycle must be satisfied to achieve system stability. However, this usually leads to overcompensation at small duty cycles, which affects the response speed of the current loop and the load capacity of the system. .

Contents of the invention

The present invention provides an adaptive segmented slope compensation circuit for a wide input range suitable for a step-down converter, which divides the entire range of the duty cycle of the system application into three sections, and does not require slope compensation when the duty cycle is small. Add an appropriate slope in the medium duty cycle, so that the compensation amount in this interval is just right, and increase the slope slope in the case of a large duty cycle, so that the worst working condition of the loop will not cause oscillation stability problems , while introducing the information of the input voltage, so that the loop stability and high load capacity can still be maintained when the input changes greatly.

Technical scheme of the present invention is:

An adaptive segmented slope compensation circuit suitable for a step-down converter, characterized in that it includes an operational amplifier A ₀ , a first resistor R ₁ , a second resistor R ₂ , a third resistor R ₀ , and a fourth resistor R _sense , the first capacitor C ₁ , the second capacitor C ₂ , the first NMOS transistor M ₁ , the second NMOS transistor M ₂ , the third NMOS transistor M ₅ , the fourth NMOS transistor M ₆ , the fifth NMOS transistor M ₇ , the first PMOS transistor M ₃ , second PMOS transistor M ₄ , third PMOS transistor M ₈ , fourth PMOS transistor M ₉ , fifth PMOS transistor M ₁₀ , first triode Q ₁ , second triode Q ₂ , third Three transistors Q ₃ , fourth transistors Q ₄ , fifth transistors Q ₅ and sixth transistors Q ₆ ,

The positive input terminal of the operational amplifier _A0 is used as the input terminal of the slope compensation circuit to connect the voltage division signal of the step-down converter, and its negative input terminal is connected to the source of the third NMOS transistor _M5 and passed through the third resistor R0 is then grounded, and its output terminal is connected to the gate of the third NMOS transistor _{M5 ;}

_The gate-drain of the first PMOS transistor M3 is short-circuited and connected to the gates of the second PMOS transistor M4 and the _third PMOS transistor _M8 and the drain of the third NMOS transistor _M5 ;

_The collector of the _first transistor Q1 is connected to the drain of the second PMOS transistor M4 and the base of the third transistor _Q3 , and its base is connected to the base of the second transistor _Q2 , the third three The emitter of the pole transistor _Q3 and the drain of the fourth NMOS transistor _M6 ;

The _first switching signal clk1 is connected to the gates of the _first NMOS transistor M1 and the fourth NMOS transistor _M6 , and the drain of the _first NMOS transistor M1 is connected to the emitter of the _first triode Q1 and passed through the first capacitor C ₁ after grounding;

The _first resistor R1 is connected between the emitter of the second transistor _Q2 and the ground;

_The gate-drain of the fourth PMOS transistor M9 is short-circuited and connected to the gate of the fifth PMOS transistor _M10 and the collectors of the second transistor _Q2 and the _fifth transistor Q5, and the drain of the fifth PMOS transistor _M10 Outputting the slope compensation voltage as the output terminal of the slope compensation circuit through the fourth resistor R _sense ;

The _second switching signal clk2 is connected to the gates of the second NMOS transistor _M2 and the fifth NMOS transistor _M7 , and the drain of the _second NMOS transistor M2 is connected to the emitter of the fourth transistor _Q4 and passed through the second capacitor C ₂ and then grounded, the _second capacitor C2 is equal to the first capacitor _C1 ; the drain of the fifth NMOS transistor _M7 is connected to the bases of the fourth transistor _Q4 and the _fifth transistor Q5 and the sixth transistor The emitter of tube _Q6 ;

The _second resistor R2 is connected between the emitter of the fifth transistor _Q5 and the ground, and the collector of the fourth transistor _Q4 is connected to the base of the sixth transistor _Q6 and the third PMOS transistor _M8 the drain;

The sources of the first PMOS transistor M ₃ , the second PMOS transistor M ₄ , the third PMOS transistor M ₈ , the fourth PMOS transistor M ₉ and the fifth PMOS transistor M ₁₀ and the third triode Q ₃ and the sixth triode The collector of the transistor Q ₆ is connected to the power supply voltage, and the sources of the first NMOS transistor M ₁ , the second NMOS transistor M ₂ , the fourth NMOS transistor M ₆ and the fifth NMOS transistor M ₇ are grounded;

The _first transistor Q1 is matched with the second transistor _Q2 , and the _fourth transistor Q4 is matched with the _fifth transistor Q5.

Specifically, the first switching signal clk ₁ and the second switching signal clk ₂ are obtained by multiplying the clock frequency of the step-down converter.

Working principle of the present invention is:

The duty ratio is divided into three intervals by the first switch signal clk ₁ and the second switch signal clk ₂ : (0, D ₁ ) interval, (D ₁ , D ₂ ) interval and (D ₂ , D ₃ ) interval , the specific method is: the _first switching signal _clk1 jumps to low level when the duty ratio reaches D1, and the _second switching signal _clk2 jumps to low level when the duty ratio reaches D2. Perform slope compensation according to different slopes in the three intervals. In the (0, D ₁ ) interval, the duty cycle is far less than 50%, no slope compensation is required, and the slope is 0; in the (D ₁ , D ₂ ) interval, The slope of the slope is S _e2 =k ₂ ·R _i ·V _in /L; in the interval (D ₂ , D ₃ ), the slope of the slope is S _e3 =k ₃ ·R _i ·V _in /L.

The beneficial effects of the present invention are: the present invention proposes an adaptive segmented linear slope compensation circuit, which is suitable for step-down converters, divides the duty ratio into three intervals and compensates according to different slopes, and solves the problem of wide input voltage at the same time. The changing slope problem makes the slope size adaptively change with the input voltage of the buck converter, which can ensure the stability of the system while fast loop response and high load capacity.

Description of drawings

Figure 1 is a frame diagram of a peak current mode system suitable for buck circuits.

Fig. 2 is a schematic diagram of the influence of current disturbance on the circuit system when the duty cycle is less than and greater than 50%, respectively.

Figure 3 is a working waveform diagram of comparing the sampling signal with the EA output with a fixed slope compensation circuit.

Figure 4 is a schematic diagram of the slope design of the segmented linear slope compensation circuit.

FIG. 5 is a schematic diagram of an adaptive segmented slope compensation circuit suitable for a wide input range of a step-down converter proposed by the present invention.

FIG. 6 is a working waveform diagram of the segmented slope compensation circuit of the present invention.

Detailed ways

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

Segmented linear slope compensation is to divide the entire range of the duty cycle into several segments, generally divided into three segments, each of which uses a different slope for compensation. In order to ensure its stability, there is a certain margin for general interval division, and the slope of each interval is determined by the maximum duty cycle. Obviously, the response speed of the segmented slope compensation is faster than that of the fixed slope compensation under certain duty cycles. quick. In the Ridley model, the quality factor Q is used to describe the loop stability, and the slope of the slope compensation circuit is a component of the Q value. In order to obtain good stability and transient response, the half switching frequency The peak value is within the acceptable range, and the Q value is generally between 0.5 and 1.3. If it is less than 0.5, the system will overcompensate and cause the response speed to be too slow; if it is greater than 1.3, the slope compensation is undercompensation, which will cause sub-harmonics Oscillation, the expression of Q value is

Where D is the duty cycle, D′=1-D, m _c =1+S _e /S _n , S _e represents the slope compensation slope, S _n is the rising slope of the sampled inductor current,

Among them, V _O is the output voltage value V _OUT of the step-down converter, L is the inductance value of the step-down converter inductor, R _i is the sampling equivalent resistance, and substituting S _n into the expression of Q can get:

If the Q value is constant, the right side of the equation (3) is a linear function that varies with the duty cycle. Here, two limits can be determined according to the minimum and maximum values of Q, one is the critical line of overcompensation, and the other is the critical line of undercompensation. Here, Q=0.5 and Q=1.3 can be taken respectively, in the middle area of the critical line is the ideal compensation area. The specific segmented schematic diagram is shown in Figure 4. The ordinate is an expression of the ramp slope, input voltage and inductance (that is, the left part of the equation (3)), and the abscissa is the change of the duty cycle D. The image is 2 A critical condition determined by the Q value, when Q is too small, it enters overcompensation, which affects stability and response speed; when Q is too large, it enters undercompensation, causing system oscillation. Therefore, the circuit is optimal only when the slope of each segment of the segment satisfies the ideal situation between the two lines. The following discussion is divided into three paragraphs:

When the duty cycle is relatively small, namely (0～D ₁ ), the duty cycle is far less than 50%, and no slope compensation is required, so the slope S _e1 =0;

As the duty cycle increases, in the interval (D ₁ ~ D ₂ ), the slope slope should meet the slope required by the maximum value D ₂ of the duty cycle in this interval, then according to the value _{k 2 and} The expression can be calculated as S _e2 =k ₂ ·R _i ·V _in /L;

For the interval with the largest duty cycle (D ₂ ～ D ₃ ), the slope of the slope should be the slope supplemented by point D _3. According to the value k ₃ and the expression corresponding to the ordinate at D ₃ , the slope of the slope at this time can be calculated as S _e3 = k ₃ R _i V _in /L.

The highlight of this design is that the slope of each section of the slope is related to Vin and will change with the change of Vin, so an adaptive segmented slope under a wide input range is achieved.

The implementation of the specific adaptive subsection slope compensation circuit is shown in FIG. 5 . The leftmost part of the circuit is the operational amplifier A ₀ , and its forward terminal introduces the voltage division signal K*Vin of the input voltage _Vin of the step-down converter, where K*Vin needs to meet the allowable input range of the operational amplifier A0, and can be clamped The current flowing through the third resistor R ₀ is K*Vin/R ₀ , the current will be mirrored by the first PMOS transistor M ₃ and the second PMOS transistor M ₄ , and the first switching signal clk ₁ is the The boundary point of the second slope, the initial state is high, which means that there is no slope before the duty cycle reaches D1. At this time, the slope _{I slope1} = 0, and the slope S _e1 = _0. When the duty cycle increases to D1, The first switch signal clk ₁ jumps low, and the mirror current starts to charge the first capacitor C ₁ , the voltage of the first capacitor C ₁ can be calculated as:

Where C is the capacitance value of the first capacitor _C1 , the _first switching signal clk1 is connected to the gate of the fourth NMOS transistor _M6 , and also pulls the gate potential of the _first triode Q1 to the ground when there is no slope, After entering the second section of the slope, release the gate of the _first triode Q1 to make it rise with the increase of the capacitor voltage. Here, the function of the third triode _Q3 is to reduce the first triode Q1. ₁ and the error of the be junction voltage of the second transistor _Q2 , the voltage drop on the _first resistor R1 is equal to the voltage drop of the first capacitor _C1 , and the voltage drop of the first capacitor _C1 is increased by the be junction voltage V _be1 of the first transistor Q1 and then subtracted The be junction voltage V _be2 of the second transistor _Q2 , because the _first transistor Q1 matches the second transistor _Q2 , the voltage on the _first resistor R1 is approximately the voltage on the first capacitor _C1 , so the second slope current is the current flowing through the _first resistor R1, the expression is:

The generation of the third stage current is consistent with the circuit structure of the second stage, the _second capacitor C2 is equal to the first capacitor _C1 , the current flowing through the third PMOS transistor _M8 is equal to the current flowing through the second PMOS transistor M4 _; The second switching signal clk ₂ jumps at the beginning of the third section, before the duty cycle is less than D ₂ , the slope current of the third section is 0, and when the duty cycle reaches D ₂ , the second switching signal clk ₂ Jump from high to low to generate the third section of ramp current, the size is:

Finally, the sum of the ramp current of the second segment and the ramp current of the third segment is mirrored, and flows through the fourth resistor R _sense together, so the expression of the segmented ramp voltage Vslope can be obtained:

1. In the interval (0, D ₁ ), there is no ramp current and ramp voltage, V _slope1 =0, and slope S _e1 =0.

2. In the interval (D ₁ , D ₂ ), there is a ramp current, which is the second ramp current, and the ramp voltage is obtained by multiplying this ramp current by Rsense: slope

3. In the interval (D ₂ , D ₃ ), there are two ramp currents, the second ramp current and the third ramp current, and the ramp voltage is: slope

The segmentation points D ₁ and D ₂ of the above interval are respectively controlled by the first switch signal clk1 and the second switch signal clk2 . Generally, D1 is set to 0.3, and D2 is set to 0.6. The _first switching signal clk1 and the _second switching signal clk2 can be generated by multiplying the system clock frequency clk of the step-down converter, which belongs to a conventional circuit implementation.

The waveform diagram of the specific ramp circuit is shown in Figure 6.

The present invention locks the quality factor Q value in an optimal range to carry out the segmentation of the slope compensation by discussing the important design parameters in the modeling of the peak current mode, and the proposed segmentation idea can help to find a suitable slope compensation segment, The strength of the slope compensation circuit can not only prevent the sub-harmonic oscillation after the loop is under-compensated, but also avoid the deterioration of the loop load capacity and response speed after the over-compensation. At the same time, the information of the input voltage Vin is introduced, so that the slope The compensation can be adaptively adjusted with the input voltage range, suitable for wide input range applications.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (2)

1. An adaptive segmented slope compensation circuit suitable for step-down converters, characterized in that it comprises an operational amplifier (A ₀ ), a first resistor (R ₁ ), a second resistor (R ₂ ), a third resistor (R ₀ ), fourth resistor (R _sense ), first capacitor (C ₁ ), second capacitor (C ₂ ), first NMOS transistor (M ₁ ), second NMOS transistor (M ₂ ), third NMOS transistor tube (M ₅ ), fourth NMOS tube (M ₆ ), fifth NMOS tube (M ₇ ), first PMOS tube (M ₃ ), second PMOS tube (M ₄ ), third PMOS tube (M ₈ ) , the fourth PMOS transistor (M ₉ ), the fifth PMOS transistor (M ₁₀ ), the first transistor (Q ₁ ), the second transistor (Q ₂ ), the third transistor (Q ₃ ), the Four transistors (Q ₄ ), fifth transistors (Q ₅ ) and sixth transistors (Q ₆ ), The positive input terminal of the operational amplifier (A ₀ ) is used as the input terminal of the slope compensation circuit to connect the voltage division signal of the step-down converter, and the negative input terminal thereof is connected to the source of the third NMOS transistor (M ₅ ) and After passing through the third resistor (R ₀ ), it is grounded, and its output terminal is connected to the gate of the third NMOS transistor (M ₅ ); The gate-drain of the first PMOS transistor (M ₃ ) is short-circuited and connected to the gates of the second PMOS transistor (M ₄ ) and the third PMOS transistor (M ₈ ) and the drain of the third NMOS transistor (M ₅ ); The collector of the first transistor (Q ₁ ) is connected to the drain of the second PMOS transistor (M ₄ ) and the base of the third transistor (Q ₃ ), and its base is connected to the second transistor (Q ₂ ), the emitter of the third transistor (Q ₃ ) and the drain of the fourth NMOS transistor (M ₆ ); The first switching signal (clk ₁ ) is connected to the gates of the first NMOS transistor (M ₁ ) and the fourth NMOS transistor (M ₆ ), and the drain of the first NMOS transistor (M ₁ ) is connected to the first triode (Q ₁ ) of the emitter and ground through the first capacitor (C ₁ ); The first resistor (R ₁ ) is connected between the emitter of the second triode (Q ₂ ) and ground; The gate-drain of the fourth PMOS transistor (M ₉ ) is short-circuited and connected to the gate of the fifth PMOS transistor (M ₁₀ ) and the collectors of the second transistor (Q ₂ ) and the fifth transistor (Q ₅ ), The drain of the fifth PMOS transistor (M ₁₀ ) passes through the fourth resistor (R _sense ) and serves as the output terminal of the slope compensation circuit to output the slope compensation voltage; The second switching signal (clk ₂ ) is connected to the gates of the second NMOS transistor (M ₂ ) and the fifth NMOS transistor (M ₇ ), and the drain of the second NMOS transistor (M ₂ ) is connected to the fourth triode (Q ₄ ) and ground through the second capacitor (C ₂ ), the second capacitor (C ₂ ) is equal to the first capacitor (C ₁ ); the drain of the fifth NMOS transistor (M ₇ ) is connected to the fourth triode (Q ₄ ) and the base of the fifth transistor (Q ₅ ) and the emitter of the sixth transistor (Q ₆ ); The second resistor (R ₂ ) is connected between the emitter of the fifth transistor (Q ₅ ) and ground, and the collector of the fourth transistor (Q ₄ ) is connected to the base of the sixth transistor (Q ₆ ). pole and the drain of the third PMOS transistor (M ₈ ); The sources of the first PMOS transistor (M ₃ ), the second PMOS transistor (M ₄ ), the third PMOS transistor (M ₈ ), the fourth PMOS transistor (M ₉ ) and the fifth PMOS transistor (M ₁₀ ) and the third The collectors of the transistor (Q ₃ ) and the sixth transistor (Q ₆ ) are connected to the power supply voltage, the first NMOS transistor (M ₁ ), the second NMOS transistor (M ₂ ), and the fourth NMOS transistor (M ₆ ) and the source of the fifth NMOS transistor (M ₇ ) are grounded; The first transistor (Q ₁ ) is matched with the second transistor (Q ₂ ), and the fourth transistor (Q ₄ ) is matched with the fifth transistor (Q ₅ ). 2. The adaptive subsection slope compensation circuit suitable for buck converter according to claim 1, characterized in that, the first switch signal (clk ₁ ) and the second switch signal (clk ₂ ) are controlled by the The clock frequency of the step-down converter is obtained by frequency multiplication.