CN107134491B - Vertical structure power electronic devices based on arcuate source field plate - Google Patents

Abstract

The invention discloses a vertical structure power electronic device based on an arc-shaped source field plate, which comprises: a substrate (1), a drift layer (2), an aperture layer (3), and two symmetrical current blocking layers on the left and right (4), channel layer (6), potential barrier layer (7) and passivation layer (12), the both sides of channel layer (6) and potential barrier layer (7) etch active groove (8), Two sources (9) are deposited in the source grooves (8) on both sides, a gate (10) is deposited on the barrier layer between the sources (9), and a drain is deposited under the substrate (1). electrode (11), the passivation layer (12) is completely wrapped around all areas except the bottom of the drain electrode (11), arc-shaped source steps (13) are engraved on both sides of the passivation layer, metal is deposited on the arc-shaped source steps, An arcuate source field plate (14) is formed which is electrically connected to the source. The invention has the advantages of high breakdown voltage, simple process, small conduction resistance and high yield, and can be used in power electronic systems.

Description

Vertical structure power electronic device based on curved source field plate

technical field

The invention belongs to the technical field of microelectronics and relates to a semiconductor device, in particular to a power electronic device with a vertical structure based on an arc-shaped source field plate, which can be used in a power electronic system.

technical background

Power semiconductor devices are the core components of power electronics technology. As energy and environmental issues become increasingly prominent, research and development of new high-performance, low-loss power devices has become one of the effective ways to improve power utilization, save energy, and alleviate energy crises. In the research of power devices, there is a serious restrictive relationship between high speed, high voltage and low on-resistance. Reasonable and effective improvement of this restrictive relationship is the key to improving the overall performance of the device. With the development of microelectronics technology, the performance of traditional first-generation Si semiconductors and second-generation GaAs semiconductor power devices has approached the theoretical limit determined by their materials themselves. In order to further reduce the chip area, increase the operating frequency, increase the operating temperature, reduce the on-resistance, increase the breakdown voltage, reduce the volume of the whole machine, and improve the efficiency of the whole machine, the wide bandgap semiconductor material represented by GaN, with its larger The bandgap width, higher critical breakdown electric field and higher electron saturation drift velocity, as well as the outstanding advantages of stable chemical properties, high temperature resistance, and radiation resistance, stand out in the preparation of high-performance power devices and have great application potential. In particular, lateral high electron mobility transistors using a GaN-based heterojunction structure, that is, lateral GaN-based high electron mobility transistor HEMT devices, are becoming more popular due to their low on-resistance, high breakdown voltage, and high operating frequency. The hot spot and focus of research and application at home and abroad.

However, in lateral GaN-based HEMT devices, in order to obtain a higher breakdown voltage, the gate-drain spacing needs to be increased, which will increase the device size and on-resistance, and reduce the effective current density per unit chip area and chip performance. This leads to an increase in chip area and development cost. In addition, in lateral GaN-based HEMT devices, the problem of current collapse caused by high electric field and surface states is more serious. Although there are many suppression measures, the problem of current collapse has not been completely solved. In order to solve the above problems, researchers have proposed a vertical GaN-based current aperture heterojunction field effect device, which is also a vertical structure power electronic device, see AlGaN/GaN current aperture vertical electrontransistors, IEEE Device Research Conference, pp.31- 32, 2002. GaN-based current aperture heterojunction field effect devices can increase the breakdown voltage by increasing the thickness of the drift region, avoiding the problem of sacrificing device size and on-resistance, so high power density chips can be realized. Moreover, in GaN-based current aperture heterojunction field effect devices, the high electric field region is located in the semiconductor material body, which can completely eliminate the current collapse problem. In 2004, Ilan Ben-Yaacov and others used MOCVD regrowth channel technology after etching to develop an AlGaN/GaN current aperture heterojunction field effect device. The device does not use a passivation layer, and the maximum output current is 750mA/mm. The conductance is 120mS/mm, the gate breakdown voltage at both ends is 65V, and the current collapse effect is significantly suppressed, see AlGaN/GaN current aperture vertical electron transistors with regrown channels, Journal of Applied Physics, Vol.95, No.4, pp. 2073-2078, 2004. In 2012, Srabanti Chowdhury and others used the technology of Mg ion implantation barrier layer combined with plasma-assisted MBE to re-grow AlGaN/GaN heterojunction, and developed a current aperture heterojunction field effect device based on GaN substrate. The device adopts a 3μm drift region, the maximum output current is 4kA·cm ^-2 , the on-resistance is 2.2mΩ·cm ² , the breakdown voltage is 250V, and the effect of suppressing current collapse is good. See CAVET on Bulk GaN Substrates Achieved With MBE-Regrown AlGaN/GaN Layers to Suppress Dispersion, IEEE Electron Device Letters, Vol.33, No.1, pp.41-43, 2012. In the same year, an enhanced GaN-based current aperture heterojunction field effect device proposed by Masahiro Sugimoto et al. was authorized, see Transistor, US8188514B2, 2012. In addition, in 2014, Hui Nie et al. developed an enhanced GaN-based current aperture heterojunction field effect device based on a GaN substrate. The threshold voltage of the device is 0.5V, the saturation current is greater than 2.3A, and the breakdown voltage is 1.5kV. , the on-resistance is 2.2mΩ·cm ² , see 1.5-kV and 2.2-mΩ-cm ² Vertical GaN Transistors on Bulk-GaN Substrates, IEEE Electron Device Letters, Vol.35, No.9, pp.939-941, 2014 .

Traditional GaN-based current aperture heterojunction field effect devices are based on GaN-based wide-bandgap semiconductor heterojunction structures, which include: substrate 1, drift layer 2, aperture layer 3, and two symmetrical current blocking layers 4 on the left and right , aperture 5, channel layer 6, potential barrier layer 7 and passivation layer 12; the two sides of channel layer 6 and potential barrier layer 7 etch active groove 8, and two sources are deposited in source groove 8 on both sides The gate 10 is deposited on the barrier layer between the source electrodes 9, the drain 11 is deposited under the substrate 1, and the passivation layer 12 completely covers all regions except the bottom of the drain, as shown in Figure 1 .

After more than ten years of theoretical and experimental research, the researchers found that the above-mentioned traditional GaN-based current aperture heterojunction field effect device has inherent defects in the structure, which will lead to extremely uneven electric field intensity distribution in the device, especially in the barrier layer and Extremely high electric field peaks exist in the semiconductor material near the interface below the aperture region, causing premature breakdown of the device. This makes it difficult to continuously increase the breakdown voltage of the device by increasing the thickness of the n-type GaN drift layer in the actual process. Therefore, the breakdown voltage of GaN-based current aperture heterojunction field effect devices with traditional structures is generally not high. In order to obtain a higher breakdown voltage of the device and continuously increase the breakdown voltage of the device by increasing the thickness of the n-type GaN drift layer, in 2013, Zhongda Li et al. used numerical simulation technology to study a superjunction-based enhanced Type GaN-based current aperture heterojunction field effect device. The research results show that the superjunction structure can effectively modulate the electric field distribution inside the device, so that the electric field intensity inside the device tends to be evenly distributed when it is in the off state, so the breakdown voltage of the device can reach 5-20kV, and the breakdown voltage is 12.4kV when using 3μm half column width, and the on-resistance is only 4.2mΩ·cm ² , see Design and Simulation of 5-20-kVGaN Enhancement-Mode Vertical Superjunction HEMT, IEEE Transactions on Electron Decices, Vol.60, No.10, pp.3230-3237, 2013. GaN-based current aperture heterojunction field-effect devices using superjunctions can theoretically obtain high breakdown voltages, and the breakdown voltage can continue to increase with the increase in the thickness of the n-type GaN drift layer, which has been reported in the literature at home and abroad. A very efficient high-power device structure with the highest breakdown voltage. However, the manufacturing process of the super junction structure is very difficult, especially in the case of a thick n-type GaN drift layer, it is almost impossible to realize the fabrication of a high performance super junction structure. Therefore, it is very necessary and urgent to explore and develop new GaN-based current aperture heterojunction field effect devices with simple manufacturing process, high breakdown voltage and low on-resistance, and has important practical significance.

The field plate structure has become a mature and effective field termination technology for improving the device breakdown voltage and reliability in lateral GaN-based HEMT devices, and this technology can realize that the device breakdown voltage varies with the length and structure of the field plate. Continued to increase. In recent years, the performance of lateral GaN-based HEMT devices has been improved by leaps and bounds by using the field plate structure, see High Breakdown Voltage AlGaN–GaN Power-HEMT Design and High CurrentDensity Switching Behavior, IEEE Transactions on Electron Devices, Vol.50, No.12, pp.2528-2531, 2003, and High Breakdown Voltage AlGaN–GaN HEMTs Achieved by Multiple Field Plates, IEEE Electron Device Letters, Vol.25, No.4, pp.161-163, 2004, and High Breakdown Voltage Achieved on AlGaN/GaN HEMTs With Integrated Slant Field Plates, IEEE Electron Device Letters, Vol.27, No.9, pp.713-715, 2006. However, up to now, there is still no precedent of the field plate structure being successfully applied to GaN-based current aperture heterojunction field-effect devices at home and abroad. This is mainly due to the inherent defects in the structure of GaN-based current aperture heterojunction field-effect devices. As a result, the strongest electric field peak in the drift layer of the device is located near the interface between the barrier layer and the aperture layer, and the electric field peak is far away from the surfaces on both sides of the drift layer. Therefore, the field plate structure can hardly play the role of effectively modulating the electric field distribution in the device, even in GaN-based The field plate structure is adopted in the current aperture heterojunction field effect device, and there is almost no improvement in device performance.

Contents of the invention

The purpose of the present invention is to address the shortcomings of the above-mentioned prior art, and provide a vertical structure power electronic device based on arc-shaped source field plates, so as to reduce the difficulty of making the device, realize the sustainable increase of the breakdown voltage, and alleviate the breakdown of the device. The contradiction between voltage and on-resistance improves the breakdown characteristics and reliability of the device.

To achieve the above object, the technical solution of the present invention is achieved in that:

1. Device structure

A vertical structure power electronic device based on an arc-shaped source field plate, including: a substrate 1, a drift layer 2, an aperture layer 3, two symmetrical current blocking layers 4 on the left and right, a channel layer 6, and a barrier layer 7 and the passivation layer 12, the active trenches 8 are etched on both sides of the channel layer 6 and the barrier layer 7, two sources 9 are deposited in the source trenches 8 on both sides, and the barrier layer between the sources 9 A gate 10 is deposited, a drain 11 is deposited under the substrate 1, a passivation layer 12 is completely wrapped around all areas except the bottom of the drain 11, and an aperture 5 is formed between two symmetrical current blocking layers 4. Features:

The two current blocking layers 4 adopt a two-level stepped structure composed of a first blocking layer 41 and a second blocking layer 42, and the first blocking layer 41 is located outside the second blocking layer 42;

The passivation layer 12 adopts an arc-shaped structure, that is, arc-shaped source steps 13 are engraved on both sides of the passivation layer, and metal is deposited on the arc-shaped source steps to form two symmetrical arc-shaped source field plates 14. The arc-shaped source field plate is electrically connected with the source.

The arc-shaped source field plate 14 and the passivation layer 12 are covered with an insulating dielectric material to form a protective layer 15 .

2. Production method

The method of the present invention for manufacturing a vertical structure power electronic device based on an arc-shaped source field plate includes the following process:

A. epitaxial n ^- type GaN semiconductor material with a thickness of 3-50 μm and a doping concentration of 1×10 ¹⁵ to 1×10 ¹⁸ cm ^-3 on the substrate 1 to form a drift layer 2 ;

B. Epitaxial n-type GaN semiconductor material on the drift layer 2 to form an aperture layer 3 with a thickness u of 1.2-3 μm and a doping concentration of 1×10 ¹⁵ to 1×10 ¹⁸ cm ⁻³ ;

C. Make a mask on the aperture layer 3 for the first time, use the mask to implant p-type impurities with a dose of 1×10 ¹⁵ to 1×10 ¹⁶ cm ^-2 on both sides of the aperture layer, and make a thickness a and Two first barrier layers 41 with the same aperture layer thickness u and a width b of 0.2-1 μm;

D. Make a mask for the second time on the aperture layer 3 and the first barrier layer 41, and use the mask to implant doses of 1×10 ¹⁵ to 1× on both sides of the aperture layer between the left and right first barrier layers 41 10 ¹⁶ cm ^-2 of p-type impurities, making two second barrier layers 42 with a thickness d of 0.3-1 μm and a width e equal to 1.1a, two first barrier layers 41 and two second barrier layers 42 constitute two A current blocking layer 4 with a two-stage step structure, and an aperture 5 is formed between two symmetrical current blocking layers 4;

E. Epitaxial GaN semiconductor material on the two first barrier layers 41, the two second barrier layers 42 and the aperture 5 to form a channel layer 6 with a thickness of 0.04-0.2 μm;

F. Epitaxial GaN-based wide-bandgap semiconductor material on the upper part of the channel layer 6 to form a barrier layer 7 with a thickness of 5-50 nm;

G. Make a mask on the barrier layer 7 for the third time, use the mask to etch the left and right sides of the barrier layer 7, and the etching depth is greater than the thickness of the barrier layer 7, but less than the channel layer 6 and the total thickness of the barrier layer 7 to form two left and right source grooves 8;

H. Make a mask for the fourth time on the upper part of the two source grooves 8 and the upper part of the barrier layer 7, use the mask to deposit metal in the two source grooves, and the thickness of the deposited metal is greater than the depth of the source groove 8 , to make source 9;

1. Make a mask for the fifth time on the top of the source electrode 9 and the top of the barrier layer 7, and utilize the mask to deposit metal on the top of the barrier layer 7 between the source electrodes 9 on the left and right sides to make the gate 10 , there is overlap in the horizontal direction between the gate 10 and the two current blocking layers 4, and the overlap length is greater than 0 μm;

J. Deposit metal on the back side of the substrate 1 to make the drain 11;

K. Deposit an insulating dielectric material in all other regions except the bottom of the drain electrode 11 to form a wrapped passivation layer 12;

L. make the sixth mask on the passivation layer 12 top, use this mask to etch in the left and right sides of the passivation layer 12, form the arc source step 13, the surface of the arc source step 13 is lower than At any point on the lower edge of the first barrier layer 41, the vertical distance from the lower edge of the first barrier layer 41 is g, the horizontal distance from the drift layer 2 is r, and approximately satisfies the relationship g=9.5-10.5exp(-0.6r) , 0 μm<g≤8.5 μm; the surface of the arc-shaped source step 13 is at the same level as the lower edge of the first barrier layer 41, and the horizontal distance t from the drift layer 2 is 0.18 μm;

M. Make the mask for the seventh time on the top of the passivation layer 12, utilize the mask to deposit metal on the arc source steps 13 on the left and right sides to form two symmetrical arc source field plates 14, and place the The arc-shaped source field plates 14 on both sides are electrically connected to the source 9, and the height of the upper edge of the arc-shaped source field plate 14 is equal to or higher than the height of the lower edge of the first barrier layer 41;

N. Deposit insulating dielectric material to completely cover the upper part of the two arc-shaped source field plates 14 and the upper part of the passivation layer 12, and make a protective layer 15 to complete the manufacturing of the entire device.

Compared with the traditional GaN-based current aperture heterojunction field effect device, the device of the present invention has the following advantages:

a. Realize continuous increase in breakdown voltage.

The present invention adopts the current blocking layer in the form of two steps, so that an electric field peak value will be generated near the interface between the first blocking layer, the second blocking layer and the aperture layer inside the device, and the former electric field peak value is greater than the latter electric field peak value; because The peak value of the former electric field is very close to the surfaces on both sides of the drift layer, so the arc-shaped source field plate can be used to effectively modulate the peak value of the electric field near the surfaces on both sides of the drift layer, so as to form a continuous and gentle gradient near the surfaces on both sides of the drift layer at the arc-shaped source field plate. High electric field area;

By adjusting the thickness of the passivation layer between the arc-shaped source field plate and the drift layer, the size and doping of the current blocking layer, the peak value of the electric field near the interface between the current blocking layer and the aperture layer can be made to correspond to the arc-shaped source field plate The peak values of the electric fields in the drift layer are equal and smaller than the breakdown electric field of the GaN-based wide bandgap semiconductor material, thereby improving the breakdown voltage of the device, and the continuous increase of the breakdown voltage can be achieved by increasing the length of the arc-shaped source field plate .

b. While increasing the breakdown voltage of the device, the on-resistance of the device is almost constant.

The present invention improves the breakdown voltage of the device by adopting arc-shaped source field plates on both sides of the device. Since the field plates will not affect the on-resistance of the device, when the device is turned on, only the drift layer inside the device is formed by the barrier layer. The resulting depletion region does not introduce other depletion regions. Therefore, as the length of the arc-shaped source field plate increases, the breakdown voltage of the device continues to increase, while the on-resistance remains almost constant.

c. The process is simple, easy to implement, and the yield rate is improved.

In the device structure of the present invention, the manufacture of the arc source field plate is realized by etching arc source steps and depositing metal in the passivation layer on both sides of the drift layer. The material is damaged, which avoids the complex process problem caused by the structure of the GaN-based current aperture heterojunction field effect device using a superjunction, and greatly improves the yield of the device.

The technical contents and effects of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Description of drawings

Figure 1 is a structural diagram of a traditional GaN-based current aperture heterojunction field effect device;

Fig. 2 is the structural diagram of the vertical structure power electronic device based on the arc source field plate of the present invention;

Fig. 3 is a flow chart of the present invention for making a vertical structure power electronic device based on an arc-shaped source field plate;

Fig. 4 is a graph of breakdown curves obtained by simulating the conventional device and the device of the present invention.

Detailed ways

Referring to Fig. 2, the present invention is based on a GaN-based wide bandgap semiconductor heterojunction structure, which includes: a substrate 1, a drift layer 2, an aperture layer 3, two symmetrical current blocking layers 4 on the left and right, an aperture 5, and a channel layer 6. The barrier layer 7 and the passivation layer 12, the active groove 8 is etched on both sides of the channel layer 6 and the barrier layer 7, and two source electrodes 9 are deposited in the source groove 8 on both sides. A gate 10 is deposited on the barrier layer between them, a drain 11 is deposited under the substrate 1 , and a passivation layer 12 completely covers all areas except the bottom of the drain 11 . in:

The drift layer 2 is located on the upper part of the substrate 1, has a thickness of 3-50 μm, and a doping concentration of 1×10 ¹⁵ to 1×10 ¹⁸ cm ^-3 ;

The aperture layer 3 is located on the upper part of the drift layer 2, its thickness u is 1.2-3 μm, and its doping concentration is 1×10 ¹⁵ to 1×10 ¹⁸ cm ^-3 ;

The current blocking layer 4 is a two-level stepped structure composed of a first blocking layer 41 and a second blocking layer 42, wherein: the two first blocking layers are located on the left and right sides of the aperture layer 3, and the two second blocking layers The layer 42 is located inside the two first barrier layers 41, and each barrier layer adopts p-type doping; the thickness a of the first barrier layer 41 is 1.2-3 μm, and the width b is 0.2-1 μm. The second barrier layer 42 Thickness d is 0.3-1 μm, width is e, and a>d, e=1.1a;

The aperture 5 is located between the two current blocking layers 4;

The channel layer 6 is located on the upper part of the two current blocking layers 4 and the aperture 5, and its thickness is 0.04-0.2 μm;

The barrier layer 7 is located on the upper part of the channel layer 6, which is composed of several layers of the same or different GaN-based wide bandgap semiconductor materials, with a thickness of 5-50 nm;

The etching depth of the source trench 8 is greater than the thickness of the barrier layer 7, but less than the total thickness of the channel layer 6 and the barrier layer 7;

The metal thickness of the source electrode 9 is greater than the depth of the source trench 8;

The grid 10 overlaps with the two current blocking layers 4 in the horizontal direction, and the overlapping length is greater than 0 μm;

The passivation layer 12 on both sides of the device is engraved with an arc-shaped source step 13, and metal is deposited on the arc-shaped source step to form two left and right arc-shaped source field plates 14; the surface of the arc-shaped source step 13 At any point below the lower edge of the first barrier layer 41, the vertical distance from the lower edge of the first barrier layer 41 is g, the horizontal distance from the drift layer 2 is r, and approximately satisfies the relationship g=9.5-10.5exp(- 0.6r), 0 μm<g≤8.5 μm; the surface of the arc-shaped source step 13 is at the same level as the lower edge of the first barrier layer 41 , and the horizontal distance t from the drift layer 2 is 0.18 μm.

The height of the upper edge of the arc-shaped source field plate 14 is equal to or higher than the height of the lower edge of the first barrier layer 41; the two arc-shaped source field plates 14 are electrically connected to the source 9; the two arc-shaped source field plates 14 and the passivation layer 12 are covered with a protective layer 15; the protective layer 15 and the passivation layer 12 can be any of SiO ₂ , SiN, Al ₂ O ₃ , Sc ₂ O ₃ , HfO ₂ , TiO ₂ one or other insulating dielectric material;

Referring to Fig. 3, the process of making the vertical structure power electronic device based on the arc-shaped source field plate of the present invention provides the following three embodiments:

Embodiment 1: Fabricate a vertical structure power electronic device based on an arc-shaped source field plate in which both the passivation layer and the protective layer are SiN.

Step 1. Epitaxial n ^- type GaN on the substrate to form a drift layer 2, as shown in Figure 3a.

Use n ⁺ type GaN as the substrate 1, and use metal organic chemical vapor deposition technology to epitaxially n ^- type GaN material with a thickness of 3 μm and a doping concentration of 1×10 ¹⁵ cm ^-3 on the substrate 1 to form a drift layer 2, of which:

The process conditions used for epitaxy are: temperature 950°C, pressure 40Torr, SiH ₄ as doping source, hydrogen gas flow rate 4000 sccm, ammonia gas flow rate 4000 sccm, gallium source flow rate 100 μmol/min.

Step 2. Epitaxial n-type GaN on the drift layer to form an aperture layer 3, as shown in FIG. 3b.

Using metal-organic chemical vapor deposition technology, epitaxial n-type GaN material with a thickness u of 1.2 μm and a doping concentration of 1×10 ¹⁵ cm ^-3 on the drift layer 2 to form an aperture layer 3, in which:

The process conditions used for epitaxy are: temperature 950°C, pressure 40Torr, SiH ₄ as doping source, hydrogen gas flow rate 4000 sccm, ammonia gas flow rate 4000 sccm, gallium source flow rate 100 μmol/min.

Step 3. Fabricate the first barrier layer 41, as shown in Figure 3c.

Make a mask for the first time on the aperture layer 3;

Then use ion implantation technology to implant p-type impurity Mg with a dose of 1×10 ¹⁵ cm ^-2 on both sides of the aperture layer to form two first barrier layers 41 with a thickness a of 1.2 μm and a width b of 0.2 μm .

Step 4. Fabricate the second barrier layer 42, as shown in Figure 3d.

First make a mask for the second time on the aperture layer 3 and the two first barrier layers 41;

Then, using ion implantation technology, p-type impurity Mg with a dose of 1×10 ¹⁵ cm ^-2 is implanted on both sides of the aperture layer between the left and right first barrier layers 41 to make a thickness d of 0.3 μm and a width e Two second barrier layers 42 with a thickness of 1.32 μm, two first barrier layers 41 and two second barrier layers 42 form two current barrier layers 4 of two-level stepped structure, and between the two symmetrical current barrier layers 4 Aperture 5 is formed.

Step 5. Epitaxial GaN material to make channel layer 6, as shown in Fig. 3e.

Using molecular beam epitaxy, GaN material with a thickness of 0.04 μm is epitaxially grown on the two first barrier layers 41 , the two second barrier layers 42 and the upper part of the aperture 5 to form the channel layer 6 .

The process conditions of the molecular beam epitaxy technology are: the degree of vacuum is less than or equal to 1.0×10 ^-10 mbar, the radio frequency power is 400W, and the reactant uses N ₂ and high-purity Ga source.

Step 6. Epitaxial Al _0.5 Ga _0.5 N to form a barrier layer 7, as shown in Figure 3f.

Using molecular beam epitaxy technology, epitaxial Al _0.5 Ga _0.5 N material with a thickness of 5 nm on the channel layer 6 to form a barrier layer 7, wherein:

The technological conditions of molecular beam epitaxy are: the degree of vacuum is less than or equal to 1.0×10 ^-10 mbar, the radio frequency power is 400W, and the reactant uses N ₂ , high-purity Ga source, and high-purity Al source.

Step 7. Etching and forming source grooves 8 on the left and right sides of the barrier layer 7 and the channel layer 6, as shown in FIG. 3g.

Make a mask on the barrier layer 7 for the third time, and use reactive ion etching technology to etch the left and right sides of the barrier layer 7 and the channel layer 6 with an etching depth of 0.01 μm to form the left and right sides of the channel layer 6. Right two source slots 8;

The technological conditions of the reactive ion etching are as follows: the flow rate of Cl ₂ is 15 sccm, the pressure is 10 mTorr, and the power is 100 W.

Step 8. Fabricate the source electrode 9, as shown in Figure 3h.

Make a mask for the fourth time on the top of the two source grooves 8 and the top of the barrier layer 7;

Then use electron beam evaporation technology to deposit Ti/Au/Ni composite metal on the top of the two source grooves 8 to form the source electrode 9, wherein: the deposited metal is from bottom to top, the thickness of Ti is 0.02 μm, Au The thickness of Ni is 0.3μm, and the thickness of Ni is 0.05μm;

The process conditions of electron beam evaporation are: the degree of vacuum is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than

Step 9. Fabricate the grid 10, as shown in Figure 3i.

9.1) Make a mask for the fifth time on the upper part of the source electrode 9 and the upper part of the barrier layer 7;

9.2) Using electron beam evaporation technology, deposit Ni/Au/Ni combined metal on the barrier layer 7 to form the gate 10, wherein: the deposited metal is from bottom to top, the thickness of Ni is 0.02 μm, and the thickness of Au is 0.02 μm. The thickness is 0.2 μm, the thickness of Ni is 0.04 μm, and the overlap length between the gate 10 and the two current blocking layers 4 in the horizontal direction is 0.4 μm;

The process conditions of electron beam evaporation are: the degree of vacuum is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than

Step 10. Fabricate the drain electrode 11, as shown in Figure 3j.

Using electron beam evaporation technology, metal Ti, Au, Ni are sequentially deposited on the back of the entire substrate 1 to form the drain 11, wherein: the thickness of the deposited metal is 0.02 μm for Ti and 0.7 μm for Au , the thickness of Ni is 0.05 μm;

The process conditions used for metal deposition are: the degree of vacuum is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than

Step 11. Deposit SiN insulating dielectric material to form a wrapped passivation layer 12, as shown in FIG. 3k.

Using plasma-enhanced chemical vapor deposition technology, deposit SiN insulating dielectric material on all regions except the bottom of the drain electrode 11 to form a wrapped passivation layer 12, wherein:

The process conditions for depositing the passivation layer are: the gas is NH ₃ , N ₂ and SiH ₄ , the gas flow rates are 2.5 sccm, 950 sccm and 250 sccm respectively, and the temperature, radio frequency power and pressure are 300°C, 25W and 950mTorr respectively.

Step 12. Etching arc-shaped source steps 13 on the left and right sides of the passivation layer, as shown in FIG. 3l.

The sixth mask is made on the upper part of the passivation layer 12, and the left and right sides of the passivation layer 12 are etched using reactive ion etching technology to form an arc-shaped source step 13, and the surface of the arc-shaped source step 13 is low At any point on the lower edge of the first barrier layer 41, the vertical distance g from the lower edge of the first barrier layer 41 and the horizontal distance r from the drift layer 2 approximately satisfy the relationship g=9.5-10.5exp(-0.6r), g The maximum is 2 μm; the surface of the arc-shaped source step 13 is at the same level as the lower edge of the first barrier layer 41, and the horizontal distance t from the drift layer 2 is 0.18 μm, where:

The technological conditions of the reactive ion etching are as follows: the flow rate of CF ₄ is 45 sccm, the flow rate of O ₂ is 5 sccm, the pressure is 15 mTorr, and the power is 250W.

Step 13. Make a curved source field plate 14, as shown in Figure 3m.

13.1) Make a seventh mask on the upper part of the passivation layer 12 with the arc-shaped source step 13;

13.2) Electron beam evaporation technology is used, that is, the vacuum degree is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than Under the process conditions, metal Ni is deposited on the arc-shaped source steps on the left and right sides, and two arc-shaped source field plates 14 with left and right symmetry are produced, and the arc-shaped source field plates 14 on the two sides are connected to the source For electrical connection, the height of the upper edge of the arc-shaped source field plate 14 is equal to the height of the lower edge of the first barrier layer 41 .

Step 14. Deposit SiN insulating dielectric material to form a protective layer 15, as shown in FIG. 3n.

Using plasma-enhanced chemical vapor deposition technology, the upper regions of the two arc-shaped source field plates 14 are completely filled with SiN insulating dielectric material to form a protective layer 15 to complete the fabrication of the entire device;

The process conditions of the plasma-enhanced chemical vapor deposition technology are as follows: the gas is NH ₃ , N ₂ and SiH ₄ , the gas flow rates are 2.5 sccm, 950 sccm and 250 sccm respectively, and the temperature, radio frequency power and pressure are 300°C and 25W respectively. and 950mTorr.

Embodiment 2: Fabricate a vertical structure power electronic device based on an arc-shaped source field plate in which both the passivation layer and the protective layer are SiO ₂ .

Step 1. Epitaxial n ^- type GaN on the substrate to form a drift layer 2, as shown in Figure 3a.

Under the process conditions of temperature 1000°C, pressure 45 Torr, SiH ₄ as doping source, hydrogen gas flow rate 4400 sccm, ammonia gas flow rate 4400 sccm, gallium source flow rate 110 μmol/min, n ⁺ type GaN was used as the substrate1 , using metal-organic chemical vapor deposition technology, epitaxial n ^- type GaN material with a thickness of 10 μm and a doping concentration of 4×10 ¹⁶ cm ^-3 on the substrate 1 to complete the fabrication of the drift layer 2 .

Step 2. Epitaxial n-type GaN on the drift layer to form an aperture layer 3, as shown in FIG. 3b.

Under the process conditions of temperature 1000°C, pressure 45Torr, dopant source SiH ₄ , hydrogen gas flow rate 4400 sccm, ammonia gas flow rate 4400 sccm, gallium source flow rate 110 μmol/min, metal-organic chemical vapor deposition technology was used. An n-type GaN material with a thickness u of 1.5 μm and a doping concentration of 4×10 ¹⁶ cm ⁻³ is epitaxially grown on the drift layer 2 to complete the manufacture of the aperture layer 3 .

Step 3. Fabricate the first barrier layer 41, as shown in Figure 3c.

3.1) Make a mask for the first time on the aperture layer 3;

3.2) Using ion implantation technology, implant p-type impurity Mg with a dose of 5.5×10 ¹⁵ cm ^-2 on both sides of the aperture layer to form two first barrier layers with a thickness a of 1.5 μm and a width b of 0.4 μm 41.

Step 4. Fabricate the second barrier layer 42, as shown in Figure 3d.

4.1) Make a mask for the second time on the aperture layer 3 and the two first barrier layers 41;

4.2) Using ion implantation technology, implant p-type impurity Mg with a dose of 5.1×10 ¹⁵ cm ⁻² on both sides of the aperture layer between the left and right first barrier layers 41 to form a thickness d of 0.5 μm and a width e Two second barrier layers 42 with a thickness of 1.65 μm, two first barrier layers 41 and two second barrier layers 42 form two current barrier layers 4 of two-level stepped structure, between the two symmetrical current barrier layers 4 Aperture 5 is formed.

Step 5. Epitaxial GaN material to make channel layer 6, as shown in Fig. 3e.

Under the conditions of a vacuum degree of less than or equal to 1.0×10 ^-10 mbar, a radio frequency power of 400W, and N ₂ as a reactant and a high-purity Ga source, using molecular beam epitaxy technology, two first barrier layers 41 and two second barrier layers 41 are formed. The GaN material with a thickness of 0.1 μm is epitaxially grown on the second barrier layer 42 and the upper part of the aperture 5 to complete the fabrication of the channel layer 6 .

Step 6. Epitaxial Al _0.3 Ga _0.7 N to form a barrier layer 7, as shown in Figure 3f.

Under the conditions of a vacuum degree of less than or equal to 1.0×10 ^-10 mbar, a radio frequency power of 400W, and N ₂ , a high-purity Ga source, and a high-purity Al source as reactants, epitaxy is carried out on the channel layer 6 using molecular beam epitaxy technology. Al _0.3 Ga _0.7 N material with a thickness of 20 nm to complete the fabrication of the barrier layer 7 .

Step 7. Etching and forming source grooves 8 on the left and right sides of the barrier layer 7 and the channel layer 6, as shown in FIG. 3g.

Make a mask on the barrier layer 7 for the third time, under the process conditions that the Cl flow rate is _15sccm , the pressure is 10mTorr, and the power is 100W, using reactive ion etching technology, on the barrier layer 7 and the channel layer 6 The left and right sides are etched to form two left and right source grooves 8, and the etching depth of the source grooves is 0.05 μm.

Step 8. Make the source electrode 9, as shown in Figure 3h.

8.1) Make a mask for the fourth time on the top of the two source grooves 8 and the top of the barrier layer 7;

8.2) When the vacuum degree is less than 1.8×10 ^-3 Pa, the power range is 200～1000W, and the evaporation rate is less than Under the process conditions, using electron beam evaporation technology, deposited Ti/Au/Ni combined metal on the top of the two source grooves 8 to form the source electrode 9, wherein: the deposited metal is from bottom to top, and the thickness of Ti is 0.02 μm, the thickness of Au is 0.03 μm, and the thickness of Ni is 0.05 μm.

Step 9. Fabricate the grid 10, as shown in Figure 3i.

9.1) Make a mask for the fifth time on the top of the two source electrodes 9 and the top of the barrier layer 7;

9.2) When the vacuum degree is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than Under certain process conditions, use electron beam evaporation technology to deposit Ni/Au/Ni composite metal on the barrier layer 7 to complete the fabrication of the gate 10, and from bottom to top, the thickness of Ni is 0.02 μm, and the thickness of Au The thickness of Ni is 0.2 μm, the thickness of Ni is 0.04 μm, and the overlapping length between the gate 10 and the two current blocking layers 4 in the horizontal direction is 0.45 μm.

Step 10. Fabricate the drain electrode 11, as shown in Figure 3j.

When the vacuum degree is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than Under the process conditions, using electron beam evaporation technology, metal Ti, Au, Ni are sequentially deposited on the back of the entire substrate 1 to form the drain electrode 11, wherein: the thickness of the deposited metal, Ti is 0.02 μm, Au The thickness of Ni is 0.7 μm, and the thickness of Ni is 0.05 μm.

Step 11. Deposit SiO ₂ insulating dielectric material to form a wrapped passivation layer 12, as shown in FIG. 3k.

Under the process conditions of _N2O flow rate of 850sccm, _SiH4 flow rate of 200sccm, temperature of 250°C, RF power of 25W, and pressure of 1100mTorr, the _SiO2 insulating dielectric material was deposited using plasma enhanced chemical vapor deposition technology. The fabrication of the passivation layer 12 is completed by wrapping all other regions except the bottom of the drain electrode 11 .

Step 12. Etching arc-shaped source steps 13 on the left and right sides of the passivation layer, as shown in FIG. 3l.

12.1) Make a sixth mask on the upper part of the passivation layer 12;

12.2) Under the process conditions of CF ₄ flow of 20sccm, O ₂ flow of 2sccm, pressure of 20mTorr, and bias voltage of 100V, use reactive ion etching technology to etch in the passivation layers on the left and right sides, and complete The manufacture of the arc-shaped source step 13, and any point on the surface of the arc-shaped source step 13 lower than the lower edge of the first barrier layer 41, the vertical distance g from the lower edge of the first barrier layer 41, and the level of the drift layer 2 The distance r approximately satisfies the relationship g=9.5-10.5exp(-0.6r), and the maximum value of g is 5 μm; the surface of the arc-shaped source step 13 is at the same level as the lower edge of the first barrier layer 41, and the level of the drift layer 2 The distance t is 0.18 μm.

Step 13. Make a curved source field plate 14, as shown in Figure 3m.

13.1) Make a seventh mask on the upper part of the passivation layer 12;

13.2) When the vacuum degree is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than Under certain process conditions, using electron beam evaporation technology, metal Ti/Au is deposited on the arc-shaped source steps 13 on the left and right sides of the passivation layer 12 to complete the manufacture of the arc-shaped source field plate 14, and the arc-shaped source field plate The plate is electrically connected to the source, and the height of the upper edge of the arc-shaped source field plate 14 is 0.2 μm higher than the height of the lower edge of the first barrier layer 41 .

Step 14. Deposit SiO ₂ material to make protective layer 15, as shown in Fig. 3n.

Under the process conditions of N ₂ O flow rate of 850 sccm, SiH ₄ flow rate of 200 sccm, temperature of 250°C, RF power of 25W, and pressure of 1100mTorr, using plasma-enhanced chemical vapor deposition technology, two arc source field plates The upper region of 14 is completely filled with SiO ₂ to form a protective layer 15, thereby completing the fabrication of the entire device.

Embodiment 3: Fabricate a vertical structure power electronic device based on an arc-shaped source field plate with a passivation layer of SiO ₂ and a protective layer of SiN.

Step A. Select n ⁺ type GaN as the substrate 1, adopt a temperature of 950°C, a pressure of 40Torr, SiH ₄ as the doping source, a flow rate of hydrogen gas of 4000 sccm, a flow rate of ammonia gas of 4000 sccm, and a flow rate of gallium source of 100 μmol/min Process conditions: use metal-organic chemical vapor deposition technology to epitaxially n ^- type GaN material with a thickness of 50 μm and a doping concentration of 1×10 ¹⁸ cm ^-3 on the substrate to form the drift layer 2 , as shown in Figure 3a.

Step B. Using the process conditions of temperature 950°C, pressure 40Torr, SiH ₄ as doping source, hydrogen gas flow rate 4000 sccm, ammonia gas flow rate 4000 sccm, gallium source flow rate 100 μmol/min, metal organic chemical vapor deposition technology, epitaxial n-type GaN material with a thickness of 3 μm and a doping concentration of 1×10 ¹⁸ cm ^-3 on the drift layer 2 to make an aperture layer 3 , as shown in Figure 3b.

Step C. Make a mask on the aperture layer 3 for the first time, and then use ion implantation technology to implant p-type impurity Mg with a dose of 1×10 ¹⁶ cm ^-2 on both sides of the aperture layer to form a thickness a of 3 μm , two first barrier layers 41 with a width b of 1 μm, as shown in FIG. 3c.

Step D. Make a mask for the second time on the aperture layer 3 and the two first barrier layers 41, and then use ion implantation technology to implant doses on both sides of the aperture layer between the left and right first barrier layers 41 The p-type impurity Mg of 1×10 ¹⁶ cm ^-2 forms two second barrier layers 42 with a thickness d of 1 μm and a width e of 3.3 μm, consisting of two first barrier layers 41 and two second barrier layers 42 There are two current blocking layers 4 with a two-stage stepped structure, and an aperture 5 is formed between the two symmetrical current blocking layers 4, as shown in FIG. 3d.

Step E. Using the process conditions of vacuum degree less than or equal to 1.0×10 ^-10 mbar, radio frequency power of 400W, reactants using N ₂ and high-purity Ga source, using molecular beam epitaxy technology, two first barrier layers 41, two A second barrier layer 42 and a GaN channel layer 6 with a thickness of 0.2 μm are epitaxially formed on the top of the aperture 5 , as shown in FIG. 3 e .

Step F. Using the process conditions of vacuum degree less than or equal to 1.0×10 ^-10 mbar, radio frequency power of 400W, reactants using N ₂ , high-purity Ga source, and high-purity Al source, using molecular beam epitaxy technology, in the channel layer 6 A barrier layer 7 made of Al _0.1 Ga _0.9 N material with a thickness of 50 nm is epitaxially, as shown in FIG. 3f.

Step G. Make a mask on the barrier layer 7 for the third time, and then adopt the process conditions of Cl ₂ flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W, and use reactive ion etching technology to form a mask on the barrier layer 7 and the channel The left and right sides of the layer 6 are etched to a depth of 0.06 μm to form two left and right source grooves 8, as shown in FIG. 3g.

Step H. Make a mask for the fourth time on the top of the two source grooves 8 and the top of the barrier layer 7, and then use a vacuum degree of less than 1.8×10 ^-3 Pa, a power range of 200 to 1000 W, and an evaporation rate of less than Using electron beam evaporation technology, deposit Ti/Au/Ni composite metal on the upper part of the two source grooves 8 to make the source electrode 9, wherein the deposited metal is from bottom to top, and the thickness of Ti is 0.02 μm, The thickness of Au is 0.3 μm, and the thickness of Ni is 0.05 μm, as shown in Figure 3h.

Step I. Make a mask for the fifth time on the top of the source electrode 9 and the top of the barrier layer 7; then use a vacuum degree of less than 1.8 × 10 ^-3 Pa, a power range of 200 to 1000 W, and an evaporation rate of less than According to the process conditions, the electron beam evaporation technology is used to deposit metal on the barrier layer 7 to make the gate 10, wherein the deposited metal is a Ni/Au/Ni metal combination, and the thickness of Ni is 0.02 μm, and the thickness of Au is 0.02 μm. The thickness is 0.2 μm, the thickness of Ni is 0.04 μm, and the overlap length between the gate 10 and the two current blocking layers 4 in the horizontal direction is 0.55 μm, as shown in Fig. 3i.

Step J. The vacuum degree is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than Under the process conditions, electron beam evaporation technology is used to sequentially deposit metal Ti, Au, Ni on the back of the entire substrate 1 to form the drain electrode 11, wherein: the thickness of the deposited metal is 0.02 μm, and the thickness of Au is 0.02 μm. The thickness is 0.7 μm, and the thickness of Ni is 0.05 μm, as shown in Fig. 3j.

Step K. Using the process conditions of N ₂ O flow rate of 850 sccm, SiH ₄ flow rate of 200 sccm, temperature of 250° C., radio frequency power of 25 W, and pressure of 1100 mTorr, use plasma enhanced chemical vapor deposition technology to deposit SiO ₂ insulating medium material, so as to wrap all other regions except the bottom of the drain electrode 11, and complete the fabrication of the passivation layer 12, as shown in FIG. 3k.

Step L. Make a sixth mask on the upper part of the passivation layer 12, and then adopt the process conditions of CF ₄ flow rate of 20 sccm, O ₂ flow rate of 2 sccm, pressure of 20 mTorr, and bias voltage of 100 V, using reactive ion etching technology, Etch in the passivation layer on the left and right sides to form an arc-shaped source step 13, and any point on the surface of the arc-shaped source step 13 that is lower than the lower edge of the first barrier layer 41 is connected to the lower edge of the first barrier layer 41. The vertical distance g and the horizontal distance r from the drift layer 2 approximately satisfy the relationship g=9.5-10.5exp(-0.6r), and g is at most 8.5 μm; the surface of the arc-shaped source step 13 and the lower edge of the first barrier layer 41 are in the For parts at the same level, the horizontal distance t from the drift layer 2 is 0.18 μm, as shown in Figure 3l.

Step M. On the upper part of the passivation layer 12, make a seventh mask, and then use a vacuum degree of less than 1.8×10 ^-3 Pa, a power range of 200-1000W, and an evaporation rate of less than According to the process conditions, electron beam evaporation technology is used to deposit Ti/Au combined metal on each arc source step 13 on the left and right sides to complete the manufacture of arc source field plate 14, and combine the arc source field plate with The source is electrically connected, and the height of the upper edge of the arc-shaped source field plate 14 is 0.7 μm higher than the height of the lower edge of the first barrier layer 41 , as shown in FIG. 3m .

Step N. Use plasma-enhanced chemical vapor deposition technology to completely fill the upper regions of the two arc-shaped source field plates 14 with SiN insulating dielectric material to form a protective layer 15 to complete the fabrication of the entire device, as shown in Figure 3n.

The processing condition of described plasma enhanced chemical vapor deposition is:

The flow rate of NH ₃ gas is 2.5 sccm;

The flow rate of _N2 gas is 950 sccm;

The flow rate of SiH ₄ gas is 250 sccm;

The temperature is 300°C, the RF power is 25W, and the pressure is 950mTorr.

The effect of the present invention can be further illustrated by the following simulation.

Simulation: The breakdown characteristics of the conventional GaN-based current aperture heterojunction field effect device and the device of the present invention were simulated, and the results are shown in FIG. 4 .

It can be seen from Fig. 4 that when the traditional GaN-based current aperture heterojunction field effect device breaks down, that is, the drain-source current increases rapidly, the drain-source voltage is about 520V, while the drain-source voltage when the device of the present invention breaks down It is about 2200V, which proves that the breakdown voltage of the device of the present invention is far greater than that of the traditional GaN-based current aperture heterojunction field effect device.

The above descriptions are only several specific embodiments of the present invention, and do not constitute a limitation to the present invention. Obviously, for those skilled in the art, after understanding the contents and principles of the present invention, they can Various modifications and changes in form and details are made according to the method of the present invention, but these modifications and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims (8)

1. a kind of vertical structure power electronic devices based on arcuate source field plate, comprising: substrate (1), drift layer (2), aperture layer (3), left and right two symmetrical current barrier layers (4), channel layer (6), barrier layer (7) and passivation layer (12), channel layer (6) and The two sides of barrier layer (7) are etched with source slot (8), the potential barrier in two sides source slot (8) there are two deposits source electrode (9), between source electrode (9) Layer is deposited over to be had grid (10), and substrate (1) is deposited with drain electrode (11) below, and passivation layer (12) is completely encapsulated in except drain electrode (11) All areas other than bottom form aperture (5) between two symmetrical current barrier layers (4), it is characterised in that:

Described two current barrier layers (4), using the two stage steps being made of the first barrier layer (41) and the second barrier layer (42) Structure, and the first barrier layer (41) are located at the outside on the second barrier layer (42)；

The passivation layer (12) is carved with arcuate source step (13), arcuate source step on the both sides of passivation layer using arcuate structure On be deposited with metal, form symmetrical two arcuate source field plates (14), the arcuate source field plate and source electrode are electrically connected；

The arcuate source field plate (14), top and passivation layer (12) top are all covered with insulating dielectric materials, form protection Layer (15).

2. device according to claim 1, it is characterised in that the two stage steps structure (41,42) of current barrier layer (4) is equal Using p-type doping, and the thickness a of the first barrier layer (41) is 1.2~3 μm, and width b is 0.2~1 μm, the second barrier layer (42) Thickness d be 0.3~1 μm, width e, and a > d, e=1.1a.

3. device according to claim 1, it is characterised in that the depth of source slot (8) is greater than the thickness of barrier layer (7), but small Overall thickness in channel layer (6) and barrier layer (7).

4. device according to claim 1, it is characterised in that the thickness of source electrode (9) is greater than the depth of source slot (8).

5. device according to claim 1, it is characterised in that arcuate source step (13) surface and the first barrier layer (41) Lower edge is in the position of same level height, and the horizontal distance t with drift layer (2) is 0.18 μm.

6. device according to claim 1, it is characterised in that lower than the first resistance on the surface of the arcuate source step (13) Any point of barrier (41) lower edge, the vertical range with the first barrier layer (41) lower edge are g, the water with drift layer (2) Flat distance is r, and meets relationship g=9.5-10.5exp (- 0.6r), 0 μm < g≤8.5 μm.

7. a kind of method for making the vertical structure power electronic devices based on arcuate source field plate, comprises the following processes:

A. the extension n on substrate (1)^-Type GaN semiconductor material is formed drift layer (2)；

B. the extension N-shaped GaN semiconductor material on drift layer (2), forms that thickness u is 1.2~3 μm, doping concentration is 1 × 10¹⁵ ~1 × 10¹⁸cm^-3Aperture layer (3)；

C. make mask for the first time on aperture layer (3), using two side position implantation dosages of the mask in aperture layer be 1 × 10¹⁵~1 × 10¹⁶cm^-2N-type impurity, production thickness a is identical with aperture layer thickness, and width b is two first of 0.2~1 μm Barrier layer (41)；

D. second of production mask on aperture layer (3) and the first barrier layer (41), using the mask on the first barrier layer of left and right (41) the two sides implantation dosage in the aperture layer between is 1 × 10¹⁵~1 × 10¹⁶cm^-2N-type impurity, production thickness d be 0.3 ~1 μm, width e is equal to two the second barrier layers (42) of 1.1a, two the first barrier layers (41) and two the second barrier layers (42) current barrier layer (4) of two two stage steps structures is constituted, forms aperture between two symmetrical current barrier layers (4) (5)；

E. in two the first barrier layers (41), two the second barrier layers (42) and aperture (5) upper epitaxial GaN semiconductor material, Form the channel layer (6) with a thickness of 0.04~0.2 μm；

F. in channel layer (6) upper epitaxial GaN base semiconductor material with wide forbidden band, the barrier layer (7) with a thickness of 5~50nm is formed；

G. mask is made for the third time on barrier layer (7), performed etching using the mask in barrier layer (7) arranged on left and right sides, and carve The thickness that depth is greater than barrier layer (7) is lost, but is less than the overall thickness of channel layer (6) and barrier layer (7), forms left and right two sources Slot (8)；

H. on two source slot (8) tops and the production mask of the top of barrier layer (7) the 4th time, using the mask in two source slots Metal is deposited, and the thickness of deposited metal is greater than the depth of source slot (8), to make source electrode (9)；

I. on source electrode (9) top and the production mask of barrier layer (7) top the 5th time, using the mask in arranged on left and right sides source electrode (9) Between barrier layer (7) top deposit metal, to make grid (10)；

J. metal is deposited on the back side of substrate (1), (11) is drained with production；

K. insulating dielectric materials are deposited in other all areas other than drain electrode (11) bottom, forms the passivation layer of package (12)；

L. the 6th mask is made on passivation layer (12) top, is carved in the right and left of passivation layer (12) using the mask Erosion is formed arcuate source step (13), any lower than the first barrier layer (41) lower edge on the surface of the arcuate source step (13) It a bit, is g with the vertical range of the first barrier layer (41) lower edge, the horizontal distance with drift layer (2) is r, and meets relationship g =9.5-10.5exp (- 0.6r), 0 μm < g≤8.5 μm；Arcuate source step (13) surface and the first barrier layer (41) lower edge Position in same level height, the horizontal distance t with drift layer (2) are 0.18 μm；

M. the 7th mask is made on the top of passivation layer (12), using the mask on the arcuate source step (13) of the right and left Metal is deposited, forms symmetrical two arcuate source field plates (14), and by the arcuate source field plate (14) of the two sides and source electrode (9) Electrical connection；

N. insulating dielectric materials are deposited, the area on two arcuate source field plate (14) tops and passivation layer (12) top is completely covered Domain makes protective layer (15), completes the production of entire device.

8. according to the method described in claim 7, it is characterized in that the arcuate source field plate (14) formed in step M, top edge Place height is equal to or higher than height where the first barrier layer (41) lower edge.