CN107093988A - The controllable K-band power amplifier of a kind of 7 modal gain and power output - Google Patents

Abstract

The present invention relates to millimeter wave wireless communication technology, in particular to a K-band power amplifier with controllable 7-mode gain and output power, including power supply, control power supply, Vdd terminal, Vb terminal, control terminals Vc1, Vc2, Vc3, input terminal, The output terminal and the ground wire, the Vdd terminal and the ground wire are connected across the positive and negative terminals of the power supply, the Vb terminal is connected to the bias voltage, and the control terminals Vc1, Vc2 and Vc3 are respectively connected to the positive terminal of the control power supply, including the sequentially connected first A balun, a first input matching circuit, a second input matching circuit, a first driving circuit, a second driving circuit, an interstage matching circuit, a gain control stage, an interstage transformer, a power stage circuit, a first output matching circuit, a second Two output matching circuits and the second balun; the first balun and the second balun are respectively connected to the input end and the output end. The amplifier has the characteristics of 7-mode power and gain pseudo-digital controllable, high power gain, high output power and so on. Low transmission loss, small phase error, low return loss, and high port isolation.

Description

A 7-mode K-band power amplifier with controllable gain and output power

technical field

The invention belongs to the technical field of millimeter wave wireless communication, and in particular relates to a K-band power amplifier with controllable gain and output power of 7 modes.

Background technique

With the rapid development of intelligent transportation, radar sensors are more and more widely used in automotive driving assistance systems. 24GHz radar sensors have quickly become the most widely used in automotive driving assistance systems due to their advantages such as small beam angle, high sensitivity, and small size. Radar sensor, 24GHz power amplifier is the key component of 24GHz radar sensor, as the last stage of amplification of the transmitter in the sensor, its performance directly affects the signal transmission range and signal anti-interference ability of the whole system. The silicon-based CMOS process is the most compatible process in the semiconductor process, but its limited process limitations have led to the slow development of research on silicon-based CMOS power amplifiers, research on high-gain, high-output power, and high-efficiency silicon-based CMOS power amplifiers became a technical problem. At the same time, the 24GHz radar sensor itself needs to control the signal transmission range in order to ensure its wide application, resulting in increased system complexity, and the 7-mode gain and output power controllable power amplifier has the potential to reduce system complexity. As an important device in the passive part of the system, the inductance element has a large area that has always restricted the development of chip miniaturization. Replacing redundant inductance with a single transformer with a small size will simplify the system structure. Reduce loss. Designing a new type of power amplifier with controllable gain and output power will effectively expand the application background and is of great significance to the development of modern automotive radar sensor systems.

Contents of the invention

The purpose of the present invention is to provide a power amplifier which realizes seven different gain modes by controlling the voltage and can effectively improve the linearity and output power of the amplifier at the same time.

To achieve the above object, the technical solution adopted in the present invention is: a K-band power amplifier with controllable 7-mode gain and output power, including power supply, control power supply, Vdd end, Vb end, control terminals Vc1, Vc2, Vc3, input Terminal, output terminal and ground wire, Vdd terminal and ground wire are connected across the positive and negative terminals of the power supply, Vb terminal is connected to the bias voltage, and the control terminals Vc1, Vc2 and Vc3 are respectively connected to the positive terminal of the control power supply, including sequential connection The first balun, the first input matching circuit, the second input matching circuit, the first driving circuit, the second driving circuit, the interstage matching circuit, the gain control stage, the interstage transformer, the power stage circuit, and the first output matching circuit , the second output matching circuit and the second balun; the first balun and the second balun are respectively connected to the input terminal and the output terminal.

In the above-mentioned 7-mode gain and output power controllable K-band power amplifier,

The first input matching circuit includes a T-shaped matching circuit connected with inductor L ₁ , capacitors C ₁ , and C ₂ ; the second input matching circuit includes a T-shaped matching circuit connected with inductor L ₂ , capacitors C ₃ , and C ₄ ;

The first drive circuit includes MOS transistors M ₁ and M ₂ connected in a cascode manner, the gate of the MOS transistor M ₂ is connected to a bias resistor R ₁ , and the second drive circuit includes MOS transistors connected in a cascode manner M ₃ and M ₄ , a bias resistor R ₂ is connected to the gate of the MOS transistor M ₃ ;

The inter-stage matching circuit includes a first inter-stage matching circuit and a second inter-stage matching circuit, the first inter-stage matching circuit includes an L _- shaped inductor L3 and a capacitor C5 , and the second inter _- stage matching circuit includes an L-shaped L-connected Inductance L ₄ and capacitance C ₆ ;

The gain control stage includes a first gain control circuit and a second gain control circuit, and the first gain control circuit includes cascode -connected MOS transistors _M5 and M6 , _MOS transistors M7 and _M8 , _MOS transistors _M9 and M ₁₀ , the bias resistor R3 is connected to the gate _of the MOS transistor _M6 , and the second gain control circuit includes cascode -connected MOS transistors M11 and M12 , MOS _{transistors M13} and _M14 , and _{MOS transistors} M15 and M ₁₆ ; the gate of the _MOS transistor M11 is connected to a bias resistor R4 _;

The interstage transformer includes a first transformer and a second transformer;

The power stage circuit includes a first power stage and a second power stage. The first power stage includes MOS transistors M ₁₇ and M ₁₈ respectively connected in a common source manner. The gate of the MOS transistor M ₁₇ is connected to a bias resistor R ₅ . The gate of M ₁₈ is connected with a bias resistor R ₆ ; the second power stage includes MOS transistors M ₁₉ and M ₂₀ respectively connected in common source; the gate of MOS transistor M ₁₉ is connected with a bias resistor R ₇ , and the gate of MOS transistor M ₂₀ A bias resistor R8 is connected to the _gate ;

The first transformer is connected between the gain control stage and the first power stage, and the second transformer is connected between the first power stage and the second power stage _; a coupling capacitor C7 and a coupling capacitor C7 are connected between the first transformer and the first power stage C ₈ ; coupling capacitors C ₉ and C ₁₀ are connected between the second transformer and the second power stage;

The first output matching circuit includes a matching circuit connected with inductor L ₅ , L ₇ and capacitor C ₁₁ , and C ₁₂ , and the second output matching circuit includes a matching circuit connected with inductor L ₆ , L ₈ and capacitor C ₁₃ , and C ₁₄ .

In the above-mentioned 7-mode gain and output power controllable K-band power amplifier, the first transformer and the second transformer are designed based on 0.13um CMOS process, the topmost metal in the process is used as the transformer coil a, and the metal thickness is 2.5um. In the process, the second-top metal is used as the transformer coil b, the thickness is 0.534um, and the distance between the two layers of metal is 0.9um. In the process, the bottom metal is used as the metal layer of the transformer. The transformer coil a contains two symmetrical RF input ports. Port II, also contains 2 symmetrical DC ports Transformer DC ports , Transformer DC port ; The RF input port is located directly above the transformer, the DC port is located on both sides of the transformer, and the metal wire is drawn from the midpoint of the transformer coil a; the transformer coil b contains two symmetrical RF output ports Transformer ports , transformer port , is located directly below the transformer, and the midpoint of the transformer coil b is connected to the metal layer of the transformer through a through hole.

In the above-mentioned 7-mode gain and output power controllable K-band power amplifier, the first balun and the second balun both use variable baluns with impedance matching and power combining functions, and are designed based on 0.13um CMOS technology. In the process, the topmost metal is used as the top metal coil of the balun, and the metal thickness is 2.5um. In the process, the second top metal is used as the top metal coil of the balun, with a thickness of 0.534um, and the distance between the two layers of metal is 0.9um; each balun has 3 ports, balun port , Balun port , Balun port , balun port As RF input port, balun port , Balun port As a radio frequency output port, the midpoint of the coil where the output port is located is connected to the balundi metal layer.

In the above-mentioned 7-mode gain and output power controllable K-band power amplifier, the inductors L ₁ , L ₂ , L ₃ , L ₄ , L ₅ , L ₆ , L ₇ , and L ₈ are all single-layered in 0.13um CMOS technology. The octagonal ring inductor uses the topmost metal in the process as the top metal coil of the inductor, the second top metal as the second top metal coil of the inductor, and the bottom metal as the metal layer of the inductor; the inductor port is set on the top metal coil of the inductor , the inductance port is set on the metal coil on the second top layer of the inductance , The metal layer of the inductor directly below the inductor is dug with deformation grooves of the same size as the periphery of the inductor.

In the above 7-mode gain and output power controllable K-band power amplifier, the inductance parameters are: L ₁ = 165 pH, L ₂ = 165 pH, L ₃ = 120 pH, L ₄ =120 pH, L ₅ = 100 pH, L ₆ =100 pH, L ₇ = 70 pH, L ₈ = 70 pH;

The capacitance parameters are: C ₁ =100 fF, C ₂ =300 fF, C ₃ =100 fF, C ₄ =300 fF, C ₅ =300 fF, C ₆ =300 fF, C ₇ = 300 fF, C ₈ = 300 fF, C ₉ = 300 fF, C ₁₀ = 300 fF, C ₁₁ = 300 fF, C ₁₂ = 300 fF, C ₁₃ = 300 fF, C ₁₄ = 300 fF;

MOS transistor parameters are: MOS transistor length L= 130nm, width: W ₁ = 2um x 46, W ₂ = 2um x46, W ₃ = 2um x 46, W ₄ =2um x 46, W ₅ =2um x 15, W ₆ = 2um x 15, W ₇ = 2um x 30, W ₈ = 2um x 30, W ₉ = 2um x 45, W ₁₀ = 2um x 45, W ₁₁ = 2um x 15, W ₁₂ = 2um x 15, W ₁₃ = 2um x 30, W ₁₄ = 2um x30, W ₁₅ = 2um x 45, W ₁₆ = 2um x 45, W ₁₇ = 2um x 42 x2, W ₁₈ = 2um x 42 x2, W ₁₉ = 2um x 42x2, W ₂₀ = 2um x 42 x2;

The resistance parameters are: R ₁ = R ₂ = R ₃ = R ₄ = R ₅ = R ₆ = R ₇ = R ₈ = 5Kohm;

The working voltage Vdd is 1.5V;

The voltage of the bias terminal Vb is 0.95V.

The beneficial effect of the invention is that it has the characteristics of 7-mode power and pseudo digital controllable gain, high power gain, high output power and the like. The 50 ohm matching characteristics of each port are good, which can well realize the compatibility and construction of the system. And the transmission loss is low, the phase error is small, the return loss is low, and the port isolation is high.

Description of drawings

Fig. 1 is a schematic diagram of a circuit module of an embodiment of the present invention;

Fig. 2 is a circuit diagram of an embodiment of the present invention;

Fig. 3 is the schematic diagram of the inductor 3D model of an embodiment of the present invention;

Among them, 31-inductance port , 32-inductance port , 33-inductance top layer metal coil, 34-inductance second top layer metal coil, 35-inductance ground metal layer;

Fig. 4 is the transformer 3D model schematic diagram of an embodiment of the present invention;

Among them, 41-transformer port I, 42-transformer port II, 43-transformer port , 44-transformer port , 45-transformer DC port , 46-transformer DC port , 47-transformer coil a, 48-transformer coil b, 49-transformer ground metal layer;

Fig. 5 is a schematic diagram of a balun 3D model of an embodiment of the present invention;

Among them, 51-balun port , 52-balun port , 53-balun port , 54-Balent top metal coil, 55-Balent top metal coil, 56-Balun ground metal layer;

Fig. 6 is a high gain, high output power mode S parameter simulation curve of an embodiment of the present invention;

Fig. 7 is a low gain, low output power mode S parameter simulation curve of an embodiment of the present invention;

Fig. 8 is a high gain, high output power mode linearity simulation curve of an embodiment of the present invention;

Fig. 9 is a low gain, low output power mode linearity simulation curve of an embodiment of the present invention;

FIG. 10 is a power gain simulation curve of seven working modes under different voltage combinations according to an embodiment of the present invention;

FIG. 11 is a linearity simulation curve of seven working modes under different voltage combinations according to an embodiment of the present invention.

detailed description

Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Examples of the described embodiments are shown in the drawings, wherein like or similar reference numerals designate like or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. They are examples only and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific examples of processes and materials are provided herein, but one of ordinary skill in the art may recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

In the description of the present invention, it should be noted that, unless otherwise specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, and it can also be the internal communication of two elements. It may be directly connected or indirectly connected through an intermediary. Those of ordinary skill in the related art can understand the specific meanings of the above terms according to specific situations.

This embodiment adopts the following scheme to realize, a K-band power amplifier with controllable 7-mode gain and output power, including power supply, control power supply, Vdd terminal, Vb terminal, control terminals Vc1, Vc2, Vc3, input terminal, output terminal and The ground wire, the Vdd terminal and the ground wire are connected across the positive and negative terminals of the power supply, the Vb terminal is connected to the bias voltage, the control terminals Vc1, Vc2 and Vc3 are respectively connected to the positive terminal of the control power supply, and the first balun connected in sequence , a first input matching circuit, a second input matching circuit, a first driving circuit, a second driving circuit, an interstage matching circuit, a gain control stage, an interstage transformer, a power stage circuit, a first output matching circuit, and a second output matching circuit The circuit and the second balun; the first balun and the second balun are respectively connected to the input end and the output end.

Further, the first input matching circuit includes a T-shaped matching circuit connected with inductor L ₁ , capacitors C ₁ , and C ₂ ; the second input matching circuit includes a T-shaped matching circuit connected with inductor L ₂ , capacitors C ₃ , and C ₄ ;

The first drive circuit includes MOS transistors M ₁ and M ₂ connected in a cascode manner, the gate of the MOS transistor M ₂ is connected to a bias resistor R ₁ , and the second drive circuit includes MOS transistors connected in a cascode manner M ₃ and M ₄ , a bias resistor R ₂ is connected to the gate of the MOS transistor M ₃ ;

The inter-stage matching circuit includes a first inter-stage matching circuit and a second inter-stage matching circuit, the first inter-stage matching circuit includes an L _- shaped inductor L3 and a capacitor C5 , and the second inter _- stage matching circuit includes an L-shaped L-connected Inductance L ₄ and capacitance C ₆ ;

The gain control stage includes a first gain control circuit and a second gain control circuit, and the first gain control circuit includes cascode -connected MOS transistors _M5 and M6 , _MOS transistors M7 and _M8 , _MOS transistors _M9 and M ₁₀ , the bias resistor R3 is connected to the gate _of the MOS transistor _M6 , and the second gain control circuit includes cascode -connected MOS transistors M11 and M12 , MOS _{transistors M13} and _M14 , and _{MOS transistors} M15 and M ₁₆ ; the gate of the _MOS transistor M11 is connected to a bias resistor R4 _;

The interstage transformer includes a first transformer and a second transformer;

The power stage circuit includes a first power stage and a second power stage. The first power stage includes MOS transistors M ₁₇ and M ₁₈ respectively connected in a common source manner. The gate of the MOS transistor M ₁₇ is connected to a bias resistor R ₅ . The gate of M ₁₈ is connected with a bias resistor R ₆ ; the second power stage includes MOS transistors M ₁₉ and M ₂₀ respectively connected in common source; the gate of MOS transistor M ₁₉ is connected with a bias resistor R ₇ , and the gate of MOS transistor M ₂₀ A bias resistor R8 is connected to the _gate ;

The first transformer is connected between the gain control stage and the first power stage, and the second transformer is connected between the first power stage and the second power stage _; a coupling capacitor C7 and a coupling capacitor C7 are connected between the first transformer and the first power stage C ₈ ; coupling capacitors C ₉ and C ₁₀ are connected between the second transformer and the second power stage;

The first output matching circuit includes a matching circuit connected with inductor L ₅ , L ₇ and capacitor C ₁₁ , and C ₁₂ , and the second output matching circuit includes a matching circuit connected with inductor L ₆ , L ₈ and capacitor C ₁₃ , and C ₁₄ .

Furthermore, both the first transformer and the second transformer are designed based on 0.13um CMOS process. The topmost metal in the process is used as the transformer coil a with a metal thickness of 2.5um, and the subtop metal in the process is used as the transformer coil b with a thickness of 0.534um. The metal layer spacing is 0.9um, and the bottom metal in the process is used as the metal layer of the transformer. The transformer coil a contains two symmetrical RF input ports, transformer port I and transformer port II, and two symmetrical DC ports. Transformer DC port , Transformer DC port ; The RF input port is located directly above the transformer, the DC port is located on both sides of the transformer, and the metal wire is drawn from the midpoint of the transformer coil a; the transformer coil b contains two symmetrical RF output ports Transformer ports , transformer port , is located directly below the transformer, and the midpoint of the transformer coil b is connected to the metal layer of the transformer through a through hole.

Furthermore, both the first balun and the second balun use variable baluns with impedance matching and power combining functions, and are designed based on a 0.13um CMOS process. The topmost metal in the process is used as the top metal coil of the balun, and the metal thickness is 2.5 um, the sub-top metal in the process is used as the balun sub-top metal coil, the thickness is 0.534um, and the distance between the two layers of metal is 0.9um; each balun has 3 ports, and the balun port , Balun port , Balun port , balun port As RF input port, balun port , Balun port As a radio frequency output port, the midpoint of the coil where the output port is located is connected to the balundi metal layer.

Furthermore, the inductors L ₁ , L ₂ , L ₃ , L ₄ , L ₅ , L ₆ , L ₇ , and L ₈ all use 0.13um CMOS process single-layer octagonal ring inductors, and use the topmost metal in the process as the top metal coil of the inductor. The sub-top metal is used as the sub-top metal coil of the inductor, and the bottom metal is used as the metal layer of the inductor; the inductor port is set on the top metal coil of the inductor , the inductance port is set on the metal coil on the second top layer of the inductance , The metal layer of the inductor directly below the inductor is dug with deformation grooves of the same size as the periphery of the inductor.

Furthermore, the inductance parameters are: L ₁ = 165 pH, L ₂ = 165 pH, L ₃ = 120 pH, L ₄ = 120 pH, L ₅ = 100 pH, L ₆ = 100 pH, L ₇ = 70 pH, L ₈ = 70pH;

The capacitance parameters are: C ₁ =100 fF, C ₂ =300 fF, C ₃ =100 fF, C ₄ =300 fF, C ₅ =300 fF, C ₆ =300 fF, C ₇ = 300 fF, C ₈ = 300 fF, C ₉ = 300 fF, C ₁₀ = 300 fF, C ₁₁ = 300 fF, C ₁₂ = 300 fF, C ₁₃ = 300 fF, C ₁₄ = 300 fF;

MOS transistor parameters are: MOS transistor length L= 130nm, width: W ₁ = 2um x 46, W ₂ = 2um x46, W ₃ = 2um x 46, W ₄ =2um x 46, W ₅ =2um x 15, W ₆ = 2um x 15, W ₇ = 2um x 30, W ₈ = 2um x 30, W ₉ = 2um x 45, W ₁₀ = 2um x 45, W ₁₁ = 2um x 15, W ₁₂ = 2um x 15, W ₁₃ = 2um x 30, W ₁₄ = 2um x30, W ₁₅ = 2um x 45, W ₁₆ = 2um x 45, W ₁₇ = 2um x 42 x2, W ₁₈ = 2um x 42 x2, W ₁₉ = 2um x 42x2, W ₂₀ = 2um x 42 x2;

The resistance parameters are: R ₁ = R ₂ = R ₃ = R ₄ = R ₅ = R ₆ = R ₇ = R ₈ = 5Kohm;

The working voltage Vdd is 1.5V;

The voltage of the bias terminal Vb is 0.95V.

During specific implementation, the 7-mode gain and output power controllable K-band power amplifier includes sequentially connected input terminals, a first balun, a first input matching circuit, a second input matching circuit, a first driving circuit, and a second driving circuit , an interstage matching circuit, a gain control stage, an interstage transformer, a power stage circuit, a first output matching circuit, a second output matching circuit, a second balun, and an output terminal. The first input matching circuit is a T-shaped matching circuit composed of inductor L ₁ , capacitors C ₁ and C ₂ , the second input matching circuit is a T-shaped matching circuit composed of inductor L ₂ , capacitors C ₃ and C ₄ ; the first input matching The circuit, the second input matching circuit and the balun B1 realize the conjugate matching of the 50 ohm impedance of the input end and the input impedance of the driver stage, so as to ensure the maximum efficiency of signal transmission and reduce loss. _The first output matching circuit is an output matching circuit composed _of inductors L5 and _L7 , _capacitors C11 and C12 , and the second output matching circuit is an output _matching circuit composed of inductors L6 and L8 _, capacitors _C13 and C14 _; The first output matching circuit, the second output matching circuit and balun B2 realize the impedance matching between the optimal load impedance of the power stage and the 50 ohm impedance of the output end, and realize the maximum output of the output power. Among them, balun B1 and B2 are both selected The balun with impedance matching and power combining functions is designed based on 0.13um CMOS process. The top metal coil of the balun adopts the top metal design in the process, and the metal thickness is 2.5um. The top metal coil of the balun adopts the second top metal design in the process. , the thickness is 0.534um, and the distance between the two layers of metal is 0.9um. The RF signal input by the dual port is coupled to the top metal coil of the balun through the top metal coil of the balun, realizing the conversion and power combination of the signal from double-ended to single-ended. _The first driving circuit is composed _of MOS transistors M1 and M2 connected in _a cascode manner, and the _second driving circuit is composed of MOS transistors M3 and M4 connected in a cascode manner, which can ensure that the power amplifier has a large enough gain . The inter-stage matching circuit is respectively composed of an L-type matching network consisting of inductor L ₃ and capacitor C ₅ , inductor L ₄ and capacitor C ₆ to achieve matching, complete the conjugate matching from the output impedance of the driver stage to the input impedance of the gain control stage, and ensure the maximum power transmission. The gain control stage and the power stage circuit and the impedance matching between the two power stages are realized by a specific transformer to ensure the maximum transmission of power. The transformer has the functions of impedance matching, signal coupling and radio frequency choke coil; it includes traditional transformers and connections in The inductance of the RF input end, the transformer is designed based on 0.13um CMOS process, the transformer coil a is designed with the top metal in the process, the metal thickness is 2.5um, the transformer coil b is designed with the second top metal in the process, the thickness is 0.534um, two layers The metal spacing is 0.9um, and the bottom metal is used as the metal layer of the transformer. It has low transmission loss near the center frequency, small phase error, low return loss, and high port isolation. With the help of inductance, the signal coupling between stages is well realized. And impedance matching, effectively reduce the loss. The first and second gain control circuits respectively consist of cascode structure MOS transistors M ₅ and M ₆ , MOS transistors M ₇ and M ₈ , MOS transistors M ₉ and M ₁₀ , MOS transistors M ₁₁ and M ₁₂ , MOS Transistors M ₁₃ and M ₁₄ , MOS transistors M ₁₅ and M ₁₆ are composed, by changing the bias voltages of the gates of MOS transistors M ₅ , M ₇ , M ₉ , and MOS transistors M ₁₂ , M ₁₄ , and M ₁₆ gates, the selection conduction Through the branch circuit, the transconductance control of the gain control stage is completed to achieve the purpose of gain and output power control. In the case of ensuring that the amplifier of this embodiment can work, Vc1, Vc2 and Vc3 can realize 7 kinds of voltage combination modes , Vc1=1.5V, Vc2=1.5V and Vc3=1.5V; Vc1=1.5V, Vc2=1.5V and Vc3=0V; Vc1=1.5V, Vc2=0V and Vc3=1.5V; Vc1=0V, Vc2= 1.5V and Vc3=1.5V; Vc1=0V, Vc2=0V and Vc3=1.5V; Vc1=1.5V, Vc2=0V and Vc3=10V; Vc1=0V, Vc2=1.5V and Vc3=0V; final power Amplifier 7 modes of operation for gain and power.

Describe the implementation of this embodiment in detail below in conjunction with accompanying drawing, as shown in Figure 1, present embodiment 7 mode gain and output power controllable K-band power amplifier circuit frame diagram, comprise Vdd end, Vb end, Vc1, Vc2, Vc3 , Input terminal, Output terminal and ground wire, Vdd terminal and ground wire are connected across the positive and negative terminals of the power supply, Vb is connected to the bias voltage, the control terminals Vc1, Vc2 and Vc3 are respectively connected to the positive terminal of the control power supply, and the Input terminal and The output terminals are the RF signal input and RF signal output terminals of the amplifier, the first balun, the first input matching circuit, the second input matching circuit, the first driver stage circuit, the second driver stage circuit, the interstage matching circuit, the gain A control stage, an interstage transformer, a power stage circuit, a first output matching circuit, a second output matching circuit, and an output terminal. The signal enters the power amplifier from the input terminal, through the first balun and the first and second input matching circuits, the single-channel signal is converted into two-channel, and the maximum efficiency is transmitted to the driver stage to realize the pre-amplification of power; the amplified signal Enter the gain control stage through the interstage matching circuit, and further complete the power amplification of a specific multiple under the operation of the gain control voltage; the amplified signal enters the power stage circuit through the interstage transformer, and the power stage circuit can effectively ensure the voltage swing strength of the signal , and achieve a weak power gain effect, the large signal output by the final power stage is output from the output terminal through the first and second output matching circuits and the second balun. High power output with high gain, high linearity and high anti-interference ability.

As shown in Figure 2, the circuit diagram of the K-band power amplifier with controllable mode gain and output power in the present embodiment includes 20 MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 , M11, M12, M13, M14, M15, M16, M17, M18, M19, M20; 14 capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14; 8 inductors L1, L2, L3, L4, L5, L6, L7, L8; 8 resistors R1, R2, R3, R4, R5, R6, R7, R8. Among them, MOS transistors M1 and M2 are connected in a cascode manner to form a first drive circuit, and MOS transistors M3 and M4 are connected in a cascode manner to form a second drive circuit; MOS transistors M5 and M6, MOS transistors M7 and M8, MOS Transistors M9 and M10 are respectively connected in a cascode manner to form a first gain control circuit, and MOS transistors M11 and M12, MOS transistors M13 and M14, and MOS transistors M15 and M16 are respectively connected in a cascode manner to form a second gain control circuit ; The MOS transistors M17 and M18 are respectively connected to form the first power stage in a common source manner, and the MOS transistors M19 and M20 are respectively connected in a common source manner to form a second power stage. Among them, the T-shaped matching circuit formed by the inductor L1, the capacitors C1 and C2 is used as the first input matching circuit, and is located between the input terminal and the first driving circuit; the T-shaped matching circuit formed by the inductor L2, the capacitors C3 and C4 is used as the first input matching circuit. The two-input matching circuit is located between the input terminal and the second drive circuit; the inductor L3 and the capacitor C5 form the first inter-stage matching circuit, the inductor L4 and the capacitor C6 form the second inter-stage matching circuit; the capacitor C7 and the capacitor C8 serve as the inter-stage The coupling capacitor is located between the gain control stage and the first power stage. Capacitor C9 and capacitor C10 are used as interstage coupling capacitors and are located between the first power stage and the second power stage; inductors L5, L7, capacitors C11 and C12 form the first An output matching circuit, inductors L6, L8, capacitors C13 and C14 form a second output matching circuit. Eight resistors R1, R2, R3, R4, R5, R6, R7, and R8 are used as bias resistors in the circuit, and are respectively connected to the gates of MOS transistors M2, M3, M6, M11, M17, M18, M19, and M20 . The power amplifier of this embodiment also includes passive components first balun B1, second balun B2, first transformer T1, second transformer T2, and the first balun B1 is connected to the input terminal to match the first and second inputs Between the circuits, the second balun B2 is connected between the first and second output matching circuits and the output terminals, the first transformer T1 is connected between the gain control stage and the first power stage, and the second transformer T2 is connected between the first between the power stage and the second power stage.

The components and circuit parameters of the power amplifier of this embodiment are as follows:

Inductance parameters are: L ₁ = 165 pH, L ₂ = 165 pH, L ₃ = 120 pH, L ₄ = 120 pH, L ₅ = 100 pH, L ₆ = 100 pH, L ₇ = 70 pH, L ₈ = 70 pH;

The capacitance parameters are: C ₁ =100 fF, C ₂ =300 fF, C ₃ =100 fF, C ₄ =300 fF, C ₅ =300 fF, C ₆ =300 fF, C ₇ = 300 fF, C ₈ = 300 fF, C ₉ = 300 fF, C ₁₀ = 300 fF, C ₁₁ = 300 fF, C ₁₂ = 300 fF, C ₁₃ = 300 fF, C ₁₄ = 300 fF;

Transistor parameters are: total transistor length L= 130nm, width: W ₁ = 2um x 46, W ₂ = 2um x 46, W ₃ =2um x 46, W ₄ =2um x 46, W ₅ =2um x 15, W ₆ = 2um x 15, W ₇ = 2um x 30, W ₈ = 2um x 30, W ₉ = 2um x 45, W ₁₀ = 2um x 45, W ₁₁ = 2um x 15, W ₁₂ = 2um x 15, W ₁₃ = 2um x 30, W ₁₄ = 2um x 30, W ₁₅ = 2um x 45, W ₁₆ = 2um x 45, W ₁₇ = 2um x 42 x2, W ₁₈ = 2um x 42 x2, W ₁₉ = 2um x 42 x2, W ₂₀ = 2um x 42 x2;

Resistance parameters: R ₁ = R ₂ = R ₃ = R ₄ = R ₅ = R ₆ = R ₇ = R ₈ = 5Kohm;

The power supply voltage Vdd is 1.5V;

The bias voltage at terminal 1 Vb is 0.95V.

As shown in Figure 3, the 3D model of the K-band power amplifier inductor with controllable 7-mode gain and output power in this embodiment is a single-layer octagonal ring designed with a professional 3D electromagnetic wave full-wave simulation software under a specific 0.13um CMOS process. Inductance, the inductance uses the topmost metal in the process as the inductance top metal coil 33, and the inductance port is set on the inductance top metal coil 33 32, the sub-top metal is used as the inductance sub-top metal coil 34, and the inductance port is set on the inductance sub-top metal coil 34 31. The metal layer 35 of the inductor uses the bottom metal in the process. The distance between the two metal layers is the largest among the metal layers of the process, which can effectively reduce the coupling loss of the signal. The metal layer located directly below the inductor Digging out the deformation slots of the same size as the periphery of the inductor can effectively reduce the eddy current effect of the inductor, reduce the loss of the inductor, and improve the quality factor of the inductor.

As shown in Figure 4, the 3D model of the transformer with matching function in the K-band power amplifier with controllable mode gain and output power in this embodiment adopts a transformer with impedance matching function and is designed based on 0.13um CMOS process. The topmost metal is used as the transformer coil a47, the metal thickness is 2.5um, the second top metal in the process is used as the transformer coil b48, the thickness is 0.534um, the distance between the two layers of metal is 0.9um, the bottom metal is used as the metal layer 49 of the transformer, and the transformer shares 6 ports, transformer coil a47 includes 2 symmetrical RF input ports transformer port I41, transformer port II 42, also includes 2 symmetrical DC ports transformer DC port 45. Transformer DC port 46, where the RF port is located directly above the transformer, the DC port is located on both sides of the transformer, and the metal wire is drawn from the midpoint of the transformer coil a; the transformer coil b contains two symmetrical RF output ports and transformer ports 43. Transformer port 44, located directly below the transformer, the midpoint of the transformer coil b is connected to the metal layer of the transformer through a through hole.

As shown in Figure 5, the 3D model of the balun in the K-band power amplifier with controllable mode gain and output power in this embodiment, the first and second baluns both adopt variable baluns with impedance matching and power combining functions, Based on the 0.13um CMOS process design, the topmost metal in the process is used as the balun top metal coil with a metal thickness of 2.5um, and the second top metal in the process is used as the balun top metal coil with a thickness of 0.534um, and the distance between the two metal layers is 0.9 um, balun has 3 ports balun port 51. Balun port 52. Balun port 53, Barron Port 51 as RF input port, balun port 52. Balun port 53 serves as a radio frequency output port, and the midpoint of the coil where the output port is located is connected to the balundi metal layer.

As shown in FIG. 6 , in the S-parameter simulation curve of the high gain and high output power mode of this embodiment, S21 is the power small signal gain, S11 is the return loss of the input port, and S22 is the return loss of the output port. It can be seen from the figure that the return loss S11 and S22 are both less than -10dB near the center frequency point, and can reach -15dB at the operating frequency of 25GHz; the 25dB bandwidth of the power small signal gain S21 is 22.5GHz-27.5GHz, and can reach 30dB.

As shown in FIG. 7 , in the S-parameter simulation curve of the low gain and low output power mode of this embodiment, S21 is the power small signal gain, S11 is the return loss of the input port, and S22 is the return loss of the output port. It can be seen from the figure that the return loss S11 and S22 are both less than -10dB near the center frequency point, and can reach -15dB at the operating frequency of 25GHz; the 10dB bandwidth of the power small signal gain S21 is 22.5GHz-27.5GHz, and can reach 14dB.

As shown in FIG. 8 , in the high gain, high output power mode linearity simulation curve of this embodiment, the output power P _1dB compression point is 16.7 dBm, and the output saturation power P _sat = 20.5 dBm.

As shown in FIG. 9 , in the linearity simulation curve of the low gain and low output power mode of this embodiment, the output power P _1dB compression point is 8.7 dBm, and the output saturation power P _sat = 12.5 dBm.

As shown in Figure 10, the power gain simulation curves of the seven working modes under different voltage combinations in this embodiment, the power amplifier will have seven working modes under different combinations of the control voltages Vc1, Vc2, Vc3, as can be seen from the figure, The 7-mode power amplifier has a power gain range of 14dB - 30dB.

As shown in Figure 11, the linearity simulation curves of the 7 operating modes of this embodiment under different voltage combinations, the power amplifier will have 7 operating modes under different combinations of the control voltages Vc1, Vc2, Vc3, as can be seen from the figure, The output power P _1dB compression point of the 7-mode power amplifier ranges from 8.7dBm to 16.7dBm, and the output saturation power P _sat ranges from 12.5dBm to 20.5dBm.

It should be understood that the parts not described in detail in this specification belong to the prior art.

Although the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, those of ordinary skill in the art should understand that these are only examples, and various variations or modifications can be made to these embodiments without departing from the principles and principles of the present invention. substance. The scope of the invention is limited only by the appended claims.

Claims (6)

1. a kind of 7 modal gain and the controllable K-band power amplifier of power output, comprising power supply, control power supply, Vdd terminal, Vb End, control end Vc1, Vc2, Vc3, input, output end and ground wire, Vdd terminal and ground cross power supply positive and negative terminal, Vb ends with Bias voltage is connected, and control end Vc1, Vc2 and Vc3 are connected with the anode for controlling power supply respectively, it is characterized in that, in addition to connect successively Between the first balun for connecing, the first input matching circuit, the second input matching circuit, the first drive circuit, the second drive circuit, level Match circuit, gain control stages, interstage transformer, power stage circuit, the first output matching circuit, the second output matching circuit and Second balun；First balun, the second balun connect input and output end respectively.

2. 7 modal gain as claimed in claim 1 and the controllable K-band power amplifier of power output, it is characterized in that,

First input matching circuit includes inductance L₁, electric capacity C₁、C₂The T-shaped match circuit of connection；Second input matching circuit includes Inductance L₂, electric capacity C₃、C₄The T-shaped match circuit of connection；

First drive circuit includes the MOS transistor M connected by cascade mode₁And M₂, MOS transistor M₂Connected on grid Biasing resistor R₁, the second drive circuit includes the MOS transistor M that is connected by cascade mode₃And M₄, MOS transistor M₃Grid Upper connection biasing resistor R₂；

Intervalve matching circuit includes the first intervalve matching circuit and the second intervalve matching circuit, and the first intervalve matching circuit includes connecting It is connected into the inductance L of L-type₃With electric capacity C₅, inductance L of second intervalve matching circuit including connecting l-shaped₄With electric capacity C₆；

Gain control stages includes the first gain control circuit and the second gain control circuit, and the first gain control circuit includes common source The MOS transistor M of common gate connection₅And M₆, MOS transistor M₇And M₈, MOS transistor M₉And M₁₀, MOS transistor M₆Connected on grid Biasing resistor R₃, the MOS transistor M that the second gain control circuit is connected including cascade₁₁And M₁₂, MOS transistor M₁₃With M₁₄, MOS transistor M₁₅And M₁₆；MOS transistor M₁₁Biasing resistor R is connected on grid₄；

Interstage transformer includes the first transformer and the second transformer；

Power stage circuit includes the first power stage and the second power stage, and the first power stage includes what is connected respectively in common source mode MOS transistor M₁₇And M₁₈, MOS transistor M₁₇Biasing resistor R is connected on grid₅, MOS transistor M₁₈Biased electrical is connected on grid Hinder R₆；Second power stage includes the MOS transistor M connected respectively in common source mode₁₉And M₂₀；MOS transistor M₁₉Connected on grid Biasing resistor R₇, MOS transistor M₂₀Biasing resistor R is connected on grid₈；

First transformer is connected between gain control stages and the first power stage, and the second transformer is connected to the first power stage and Between two power stages；Coupled capacitor C is connected between first transformer and the first power stage₇And C₈；Second transformer and the second work( Coupled capacitor C is connected between rate level₉And C₁₀；

First output matching circuit includes inductance L₅、L₇Electric capacity C₁₁、C₁₂The match circuit of connection, the second output matching circuit includes Inductance L₆、L₈Electric capacity C₁₃、C₁₄The match circuit of connection.

3. 7 modal gain as claimed in claim 2 and the controllable K-band power amplifier of power output, it is characterized in that, first Transformer, the second transformer are designed using based on 0.13um CMOS technologies, and top metal is used as transformer coil in technique A, metal thickness is that time top-level metallic is as transformer coil b in 2.5um, technique, and thickness is 0.534um, double layer of metal spacing Bottom metal includes 2 symmetrical rf inputs as transformer ground metal level on transformer coil a in 0.9um, technique Mouth transformer port I, transformer port II, also comprising 2 symmetrical DC port transformer DC ports I, transformer dc ends Mouth II；Rf inputs mouthful are located at directly over transformer, and DC ports are located at transformer both sides, transformer coil a midpoint metals Line is drawn；Comprising 2 symmetrical radio frequency output port transformer port III, transformer port IV on transformer coil b, it is located at The underface of transformer, transformer coil b midpoints by through hole and transformer metal level be connected.

4. 7 modal gain as claimed in claim 1 and the controllable K-band power amplifier of power output, it is characterized in that, first Balun, the second balun are from the change balun acted on impedance matching and power combing, and using based on 0.13um CMOS works Skill is designed, and top metal is as balun top-level metallic coil in technique, and metal thickness is time top-level metallic in 2.5um, technique As balun time top-level metallic coil, thickness is 0.534um, double layer of metal spacing 0.9um；There are 3 ports in each balun, Balun port I, balun port II, balun port III, balun port I are used as rf inputs mouthful, balun port II, balun end Mouthful III as radio frequency output port, coil midpoint where output port and balun metal level be connected.

5. 7 modal gain as claimed in claim 2 and the controllable K-band power amplifier of power output, it is characterized in that, inductance L₁、L₂、L₃、L₄、L₅、L₆、L₇、L₈Using the anistree ring-shaped inductors of 0.13um CMOS technologies individual layer, top gold in technique is utilized Category is as inductance top-level metallic coil, and secondary top-level metallic is as inductance time top-level metallic coil, and bottom metal is as inductively Metal level；Set on inductance top-level metallic coil and inductance port I, position are set on inductance port II, inductance time top-level metallic coil Inductively metal level immediately below inductance digs the deformation trough having with the peripheral equidimension of inductance.

6. 7 modal gain as claimed in claim 2 and the controllable K-band power amplifier of power output, it is characterized in that, inductance Parameter is respectively：L₁=165pH, L₂=165pH, L₃=120pH, L₄=120pH, L₅=100pH, L₆=100pH, L₇= 70pH, L₈=70pH；

Capacitance parameter is respectively：C₁=100fF, C₂=300fF, C₃=100fF, C₄=300fF, C₅=300fF, C₆=300fF, C₇=300fF, C₈=300fF, C₉=300fF, C₁₀=300fF, C₁₁=300fF, C₁₂=300fF, C₁₃=300fF, C₁₄= 300fF；

MOS transistor parameter is respectively：MOS transistor length L=130nm, width is：W₁=2umx46, W₂=2umx46, W₃ =2umx46, W₄=2umx46, W₅=2umx15, W₆=2umx15, W₇=2umx30, W₈=2umx30, W₉=2umx45, W₁₀= 2umx45, W₁₁=2umx15, W₁₂=2umx15, W₁₃=2umx30, W₁₄=2umx30, W₁₅=2umx45, W₁₆=2umx45, W₁₇ =2umx42x2, W₁₈=2umx42x2, W₁₉=2umx42x2, W₂₀=2umx42x2；Resistance parameter is respectively：R₁=R₂=R₃= R₄=R₅=R₆=R₇=R₈=5Kohm；

Operating voltage Vdd is 1.5V；

Offset side Vb voltages are 0.95V.