CN107066707B - A kind of adjustable design method for tracing and device using snapshot - Google Patents

Abstract

The present invention proposes that a kind of adjustable using snapshot designs method for tracing and device, it is related to integrated circuit adjustable design field, the method comprising the steps of 1, the capacity of setting trace cache and snapshot caching, and the width of the width limitation and snapshot signal that determine trace signals limits；Step 2, it is limited according to the width of the trace signals and the snapshot signal, generates register cluster and iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；Step 3, according to the trace signals and the snapshot signal, setting tracking structure, wherein the tracking structure includes tracking controller, trigger, tracking bus, trace cache, snapshot caching.The present invention can significantly improve the state recovery rate of tune-up data, increase the observability of silicon post debugging, shorten the silicon post debugging time；Present invention may determine that the recovery key signal of property；The present invention can reduce the runing time of trace signals selection method.

Description

A method and apparatus for debuggable design tracing using snapshots

technical field

The present invention relates to the technical field of debuggable design of integrated circuits, and in particular, to a method and device for traceability of debuggable designs using snapshots.

Background technique

With the increase in the complexity of integrated circuit design and the pressure for rapid productization, debuggable design has become a supporting technology for post-silicon debugging. Due to factors such as high design complexity, slow software simulation speed, and low accuracy of time-delay models, pre-silicon verification cannot guarantee the correctness of hardware design. It causes huge losses. As the last quality control link before mass production, post-silicon debugging can verify the correctness of the chip after tape-out, and detect, locate and diagnose errors that are missed before the silicon. Due to the poor observability of the chip after tape-out, the silicon Post-debugging has become an important bottleneck in the development process of integrated circuits, and even takes more than half of the development time. The debuggability design improves the observability of the chip during post-silicon debugging by adding a debugging circuit to assist post-silicon debugging in the chip design stage. performance, reducing post-silicon debug time.

Trace-based debuggability design is a mainstream design solution. By adding trace buffers in the chip, it can provide continuous multi-shot real-time trace capabilities during post-silicon debugging. It has become one of the main technologies for post-silicon debugging, and has been widely used. It is used in commercial processors, such as ARM-based processors and IBM Power series processors. A complete trace design usually includes: trigger module, trace controller, trace buffer, as shown in Figure 1. The trigger module is used to monitor the trigger event or trigger sequence in debugging. When the specified trigger event or sequence occurs, the trigger unit will monitor the trigger information and inform the tracking controller. The tracking controller receives the trigger signal from the trigger module, starts the signal tracking, and stores the tracking data in the tracking buffer. The trace controller can also configure debugging parameters such as trigger events in the trigger unit according to the debugging requirements. The trace cache stores trace data in real time. When the trace buffer is full of trace data, the data in the trace buffer can be output to off-chip through the debug interface for subsequent state recovery and error debugging.

The existing method of trace design in the industry is to select important functional signals or functional signals related to the instruction stream of the processor, and connect these functional signals to the trace cache through the debug bus. For example, the debug architecture of ARM generally stores the processor's instruction counter, instructions, etc. in the on-chip trace cache. Such methods are helpful for software-level debugging, but have limited help in debugging circuit-level errors. How to accurately find, diagnose, and locate design errors after tape-out has become a bottleneck for post-silicon debugging.

State recovery is the main technology of circuit-level error detection and location. It uses the known circuit logic state to recover the unknown circuit logic state. Through state recovery, more state values of the internal signals of the circuit can be known, thereby improving the observability of the circuit. , to assist in the diagnosis and localization of errors in post-silicon debugging. The basic principle is to use the logic function of the logic unit for logic derivation, and use the known signal state to restore the unknown signal state. There are generally three recovery strategies for logic gates: forward recovery, backward recovery and combined recovery. Forward recovery is to use the input of the logic gate to infer the output of the logic gate, backward recovery is to use the output of the logic gate to infer the input of the logic gate, and combinatorial recovery is to combine the output of the logic gate and part of the input to infer the unknown input. These recovery operations are shown in Figure 2. For sequential logic gates, recovery operations are also possible, but timing relationships need to be considered. Using these recovery principles, a state recovery simulator can be constructed, which takes the tracking data obtained from the tracking cache as input, recovers the untracked data, and learns more gate-level signal states. Detect, locate and diagnose pre-silicon design errors at the circuit level. The state recovery rate is an index to evaluate the recovery ability of the tracked signal to the untracked signal. The state recovery rate is defined as the ratio of the total number of all known register states after state recovery to the total number of tracked register states. Under the same number of trace signals and the same trace period, a large state recovery rate means that more internal register states can be known, and internal observability is greater, which is more helpful for circuit-level error debugging.

Researchers at home and abroad have proposed to analyze the circuit and select some signals that are important for state recovery as the tracking signal. The multiplexing network is connected to the trace cache. When a trace cycle begins, the data for the debug-related trace signals is stored in the trace buffer. During the tracking period, each beat data of the tracking signal is stored in the tracking buffer until the tracking buffer has no free storage space. During debugging data analysis, it is necessary to export the trace data of each clock cycle stored in the trace cache, and perform state recovery, thereby assisting error debugging. At present, there are many methods of tracking signal selection based on state recovery rate, which are mainly divided into two categories: probability-based tracking signal selection and simulation-based tracking signal selection. The probability-based selection method uses the probability analysis method to estimate the state recovery rate by comprehensively considering the topological structure of the combinatorial circuit between the registers and the logic characteristics of the logic gate, and iteratively selects the tracking signal that maximizes the state recovery rate. Simulation-based selection methods use actual simulation data to estimate state recovery rates and select tracking signals accordingly.

Existing state recovery methods only perform logical derivation from the topology of a simple combinational circuit, which is limited by complex logic structures, has a low state recovery rate, and is of limited help for post-silicon debugging. The existing debugging technology based on state recovery takes the tracking data of the tracking signal in the tracking period as the known signal, and then recovers other signals iteratively through the logic derivation of the logic gate. The recovery of the signal is based on the recovery operation of the logic gate. Complex logic gate structures, such as multi-input NAND or NOR gates, have a low probability of recovering otherwise unknown signals with a single known input or output. This method is limited by the structure of combinational logic and the logic complexity of basic logic gates, and the state recovery rate obtained by using the tracking signal for state recovery in complex circuits is low.

In addition, the existing tracking signal selection method based on state recovery cannot obtain a tracking signal with a high state recovery rate in a relatively short time. The probability-based method runs fast, but the probability estimation accuracy is low, and the obtained state recovery rate is lower than that of the simulation method; the simulation-based method can achieve a higher state recovery rate, but the running time is too long. These deficiencies restrict the application of the selection method based on the state recovery rate in practice.

SUMMARY OF THE INVENTION

In view of the deficiencies of the prior art, the present invention proposes a method and device for debuggable design tracing using snapshots.

The present invention proposes a debuggable design tracking method using snapshots, including:

Step 1, set the capacity of the tracking buffer and the snapshot buffer, and determine the width limit of the tracking signal and the width limit of the snapshot signal;

Step 2, according to the width limitation of the tracking signal and the snapshot signal, generate a register cluster and iteratively select the register cluster, thereby determining the tracking signal and the snapshot signal;

Step 3, setting a tracking structure according to the tracking signal and the snapshot signal, wherein the tracking structure includes a tracking controller, a trigger, a tracking bus, a tracking buffer, and a snapshot buffer.

The tracking buffer is used to store the tracking signal, and the tracking buffer includes the width and depth of the tracking buffer, wherein the width is the number of signals simultaneously tracking the tracking signal, and the depth is the clock that tracks the tracking signal number of cycles.

The snapshot cache is used for storing the snapshot signal, wherein the snapshot signal is connected to the snapshot cache through a transmission network.

The snapshot signal includes a cluster snapshot, wherein the cluster state is a state set of all intra-cluster registers in the current clock cycle.

Also included is the step of selecting a tracking signal, wherein register clusters are generated by forward searching, the global state recovery rate brought by each of the register clusters is estimated, and the register cluster that improves the state recovery rate the most is selected as the tracking cluster, and The cluster input is used as the tracking signal, and the registers within the register cluster are used as the snapshot signal, until the width of the tracking signal is preset to the threshold.

The present invention also provides a debuggable design tracking device using snapshots, including:

Determine the width limit module, which is used to set the capacity of the tracking buffer and the snapshot buffer, and determine the width limit of the tracking signal and the width limit of the snapshot signal;

A determining signal module, for generating a register cluster and iteratively selecting a register cluster according to the width limitation of the tracking signal and the snapshot signal, thereby determining the tracking signal and the snapshot signal;

A tracking structure setting module is configured to set a tracking structure according to the tracking signal and the snapshot signal, wherein the tracking structure includes a tracking controller, a trigger, a tracking bus, a tracking buffer, and a snapshot buffer.

The tracking buffer is used to store the tracking signal, and the tracking buffer includes the width and depth of the tracking buffer, wherein the width is the number of signals simultaneously tracking the tracking signal, and the depth is the clock that tracks the tracking signal number of cycles.

The snapshot cache is used for storing the snapshot signal, wherein the snapshot signal is connected to the snapshot cache through a transmission network.

The snapshot signal includes a cluster snapshot, wherein the cluster state is a state set of all intra-cluster registers in the current clock cycle.

Also includes selecting a tracking signal module, wherein, generating register clusters through forward search, estimating the global state recovery rate brought by each of the register clusters, and selecting the register cluster that improves the state recovery rate the most as the tracking cluster, and The cluster input is used as the tracking signal, and the registers within the register cluster are used as the snapshot signal, until the width of the tracking signal is preset to the threshold.

As can be seen from the above scheme, the advantages of the present invention are:

First, the present invention can significantly improve the state recovery rate of debugging data, increase the observability of post-silicon debugging, and shorten the time of post-silicon debugging. By tracking the input of the snapshot signal and the initial state of the snapshot signal, the present invention can deterministically restore the state value of the snapshot signal in the entire debugging cycle, and these restored state values can also restore other unknown signals, thereby improving the The state recovery rate of the entire tracking scheme is calculated.

Second, the present invention can deterministically restore key signals. In traditional tracking design and state recovery, except for tracking data, other signals that can be recovered are extremely limited. By acquiring the initial state of the snapshot signal and combining the tracking signal, the present invention can deterministically restore the state of the snapshot signal in the tracking period.

Third, the present invention can reduce the running time of the tracking signal selection method. The present invention determines the tracking signal and the snapshot signal by selecting the register cluster. Selecting a register bank can determine multiple trace signals at the same time, speeding up the speed of trace signal selection. Due to the short selection time, multiple iterative optimizations can be performed for the selection results.

Description of drawings

Figure 1 is a framework diagram of trace-based debuggability design;

Fig. 2 is an example diagram of state recovery;

Fig. 3 is the example circuit diagram of cluster recovery;

4 is a diagram of a tracking device using snapshots proposed by the present invention;

Figure 5 is a snapshot tracking example diagram;

6 is a flowchart of a tracking signal selection method;

Figure 7 is a flow diagram of a trace design using snapshots.

Detailed ways

The method for state recovery using snapshots of the present invention is specifically as follows: for a selected register cluster, the entire register can be recovered by combining the cluster input of the register cluster and the snapshot of the register within the cluster, that is, the initial state of the register within the cluster. The state of the cluster throughout the tracking period. A register cluster is composed of several registers extracted from the circuit, and these registers are called intra-cluster registers. The cluster state represents the state set of all the registers in the cluster in the current clock cycle, also known as the cluster snapshot, and the precursor register of the register in the cluster is called the cluster input, and the precursor original input of the register in the cluster directly affected by the combinational logic is also called the cluster input. . Figure 3 shows a register cluster extracted from the circuit, which includes 4 intra-cluster registers, namely {B, C, D, E}, and the cluster input set is {A}. By obtaining the initial state of the cluster and the cluster input The state value of the register cluster in all tracking periods can be recovered, because according to the initial state of the cluster and the initial input of the cluster, the cluster state of the next tracking period can be known, and by recursion, we can get Know the cluster states of all subsequent tracking cycles, as shown in Table 1, if the initial state of the cluster is known, that is, the state of {B, C, D, E} in cycle 0 is known, and the cluster input is continuously tracked, that is, A is known From the values of period 0 to period 4, the states of {B, C, D, E} in periods 1 to 5 can be recovered by using these values, and all cluster states in the tracking period can be recovered, as shown in the gray shade in Table 1. As shown in part, if the traditional state recovery method is adopted, that is, the initial state of the cluster is not used, then selecting any one in Figure 3 as the tracking signal cannot completely recover all the states of the register cluster in the tracking period.

Table 1

Compared with the traditional tracking design, the tracking scheme of the present invention has obvious improvements in hardware design. As shown in Figure 4, the present invention needs to capture two different types of signals: tracking signals and snapshot signals, while the traditional tracking design does not capture Snapshot signal, the tracking signal needs to be captured every cycle in the tracking period, and only its initial state is captured for the snapshot signal. In order to meet the capture requirements, the tracking design scheme of the present invention needs to increase the snapshot cache, that is, there are two types of caches: Trace cache and snapshot cache.

The trace buffer is used to store trace signals. Generally, its width and depth are limited. The width represents the number of signals that can be traced at the same time, and the depth represents the number of clock cycles that can be traced. For example, a 16*1024 trace buffer can simultaneously trace 16 bits of trace. signal, and continues to track 1024 cycles.

The snapshot cache is a newly added cache in the tracking design of the present invention, which is used to store the snapshot signal, that is, the initial state of the selected tracking register cluster. The selected snapshot signal is connected to the snapshot cache through the transmission network, and the snapshot signals of each different cluster are It can be captured successively in different trace cycles. If these register banks have no timing dependency, and the sum of the number of snapshot signals is not greater than the width of the snapshot cache, the snapshots of multiple register banks can also be captured at the same time.

As shown in Figure 5, the snapshots of the three register banks {A, B, C} are stored in the snapshot cache, and the snapshots of the register banks A, B and C can be captured successively in three tracking cycles, if the snapshot cache width constraint is satisfied , it is also possible to capture snapshots of register banks A, B, and C at the same time.

Since the invention uses the snapshot signal in the snapshot cache to improve the state recovery rate, the corresponding tracking signal selection method is also changed. The tracking signal selection problem using snapshots can be decomposed into the problem of register bank generation and register bank selection, tracking signal and snapshot signal. Determined by the trace register bank, due to the limited debug design overhead, the trace register bank needs to satisfy the constraints of the trace signal width WT and the snapshot signal width _{W S at} the same time.

The tracking signal selection method using snapshots of the present invention can be divided into two steps: register cluster cluster generation and register cluster selection, that is, first generate register clusters through forward search, and then estimate the global state recovery rate that each register cluster can bring. , and select the cluster that improves the state recovery rate the most as the tracking cluster, the cluster input is used as the tracking signal, and the register in the cluster is used as the snapshot signal, until the width of the tracking signal meets the design requirements (that is, the width meets a preset threshold), the tracking signal The selection method flow is shown in Figure 6.

The specific design steps of the tracking scheme using snapshots are:

Step 1: Determine buffer capacity and signal constraints. Design the capacity of the trace buffer and the snapshot buffer, and determine the width limit of the trace signal and the width limit of the snapshot signal.

Step 2: Track signal and snapshot signal selection. According to the width constraints of the trace signal and the snapshot signal, register clusters are generated and selected iteratively to determine the trace signal and the snapshot signal.

Step 3: Design the overall tracking structure. Determine the complete trace scheduling scheme and design the entire trace structure, including trace controllers, triggers, trace buses, trace caches, snapshot caches, etc.

The present invention also provides a debuggable design tracking device using snapshots, including:

Determine the width limit module, which is used to set the capacity of the tracking buffer and the snapshot buffer, and determine the width limit of the tracking signal and the width limit of the snapshot signal;

A determining signal module, for generating a register cluster and iteratively selecting a register cluster according to the width limitation of the tracking signal and the snapshot signal, thereby determining the tracking signal and the snapshot signal;

A tracking structure setting module is configured to set a tracking structure according to the tracking signal and the snapshot signal, wherein the tracking structure includes a tracking controller, a trigger, a tracking bus, a tracking buffer, and a snapshot buffer.

The tracking buffer is used to store the tracking signal, and the tracking buffer includes the width and depth of the tracking buffer, wherein the width is the number of signals simultaneously tracking the tracking signal, and the depth is the clock that tracks the tracking signal number of cycles.

The snapshot cache is used for storing the snapshot signal, wherein the snapshot signal is connected to the snapshot cache through a transmission network.

The snapshot signal includes a cluster snapshot, wherein the cluster state is a state set of all intra-cluster registers in the current clock cycle.

Also includes selecting a tracking signal module, wherein, generating register clusters through forward search, estimating the global state recovery rate brought by each of the register clusters, and selecting the register cluster that improves the state recovery rate the most as the tracking cluster, and The cluster input is used as the tracking signal, and the registers within the register cluster are used as the snapshot signal, until the width of the tracking signal is preset to the threshold.

Claims (8)

1. a kind of adjustable using snapshot designs method for tracing characterized by comprising

Step 1, the capacity of setting trace cache and snapshot caching determines the width of the width limitation and snapshot signal of trace signals Limitation；

Step 2, it is limited according to the width of the trace signals and the snapshot signal, generates register cluster and iteration selection deposit Device cluster, so that it is determined that the trace signals and the snapshot signal；

Step 3, according to the trace signals and the snapshot signal, setting tracking structure, wherein the tracking structure includes chasing after Track controller, trigger, tracking bus, trace cache, snapshot caching；

Wherein further include selection trace signals step, register cluster is generated by sweep forward, estimates each register cluster Bring global state recovery rate, and select to improve the state recovery rate most register clusters as tracking cluster, and will Cluster input is used as trace signals, and register is as snapshot signal in the cluster of register cluster, until the width of trace signals meets one Preset threshold.

2. designing method for tracing using the adjustable of snapshot as described in claim 1, which is characterized in that the trace cache For storing the trace signals, the trace cache includes the width and depth of trace cache, wherein the width is simultaneously The signal number of the trace signals is tracked, the depth is to track the clock periodicity of the trace signals.

3. designing method for tracing using the adjustable of snapshot as described in claim 1, which is characterized in that the snapshot is slow It deposits, for storing the snapshot signal, wherein the snapshot signal is connected on the snapshot caching by transmission network.

4. designing method for tracing using the adjustable of snapshot as described in claim 1, which is characterized in that the snapshot signal In include cluster snapshot, wherein the tufted state be all clusters in register present clock period state set.

5. a kind of adjustable using snapshot designs follow-up mechanism characterized by comprising

It determines that width limits module, for the capacity of trace cache and snapshot caching to be arranged, determines the width limitation of trace signals It is limited with the width of snapshot signal；

It determines signaling module, for limiting according to the width of the trace signals and the snapshot signal, generates register cluster simultaneously Iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；

Setting tracking construction module, for according to the trace signals and the snapshot signal, setting tracking structure, wherein described Tracking structure includes tracking controller, trigger, tracking bus, trace cache, snapshot caching；

Trace signals module is selected, for generating register cluster by sweep forward, estimates each register cluster bring Global state recovery rate, and select to improve the state recovery rate most register clusters as tracking cluster, and cluster is inputted As trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals meets a default threshold Value.

6. designing follow-up mechanism using the adjustable of snapshot as claimed in claim 5, which is characterized in that the trace cache For storing the trace signals, the trace cache includes the width and depth of trace cache, wherein the width is simultaneously The signal number of the trace signals is tracked, the depth is to track the clock periodicity of the trace signals.

7. designing follow-up mechanism using the adjustable of snapshot as claimed in claim 5, which is characterized in that the snapshot is slow It deposits, for storing the snapshot signal, wherein the snapshot signal is connected on the snapshot caching by transmission network.

8. designing follow-up mechanism using the adjustable of snapshot as claimed in claim 5, which is characterized in that the snapshot signal In include cluster snapshot, wherein the tufted state be all clusters in register present clock period state set.