CN105094949B - A kind of analogy method and system based on instruction computation model and feedback compensation - Google Patents

Abstract

The invention belongs to the technical field of processor software simulation, and specifically relates to a simulation method and system based on an instruction calculation model and feedback compensation. The simulation process of the present invention is carried out around the instruction sequence, and the simulation method of calculating the sequence information of the instructions one by one is adopted. The simulator obtains the launch cycle and the completion cycle of the instructions flowing through the functional components through the calculation method; the multi-threaded parallel acceleration calculation process is used, and the processor is for the shared Resource access is carried out in the way of speculative execution; in the process of speculative execution, each private resource module sends the access information to the shared resource module, and the timing correction algorithm performs timing calculation. If the speculative execution timing is inconsistent with the actual shared resource calculation timing, the cumulative error is calculated, and the cumulative error is fed back and compensated to the processor core that generated the error after the program simulation ends. The invention can be used for framework simulation of hardware production and evaluation of application programs and systems, can quickly and accurately obtain the simulation results of each application program under the target system structure, and is convenient for fast and accurate evaluation of applications and systems.

Description

A simulation method and system based on command calculation model and feedback compensation

technical field

The invention belongs to the technical field of processor software simulation, and in particular relates to a method and system for simulating the operation of a processor.

Background technique

Human beings have entered the era of information explosion, and the relationship between information and human life has become increasingly close. With the continuous development of information technology, the types of new electronic products are constantly enriched, and the number of electronic products per capita is also increasing. The electronic products that people use daily have transitioned from simple mobile phones and MP3 to powerful MP4, e-books, smart phones and smart wearable devices. According to the latest data from IDC, China's smartphone shipments will increase by 13% year-on-year in 2014, reaching 420 million units. With the rapid development of network technology, various new applications and application modes have sprung up, such as cloud computing, intelligent computing, graph computing, mobile computing and wearable computing.

With the great enrichment of applications, higher and higher requirements are put forward for the underlying processing platform, resulting in the continuous enrichment of various processor products, which also means that the competitive pressure of processor products from all aspects is increasing, leaving The hardware and software development cycle for processor products is getting shorter and shorter. Due to the increasing competition, the design and development cycle of hardware chip products is usually 8 months to 1 year. The shorter the development cycle, the more competitive the product and the greater the profit margin. However, statistics from the Intel SoC design department show that the cycle from the beginning of design to the completion of production of general processor products is generally 9 months, and the development cycle of the corresponding software part is also 9 months. In this context, on the one hand, hardware engineers are required to complete chip design and evaluation as soon as possible; on the other hand, it is also required to provide software designers and developers with available simulation tests as early as possible in the early stages of chip design (such as 3 months). platform.

In order to improve the efficiency of architecture design and development and save development costs, simulators are currently used to simulate the operation of the overall architecture through software. As an architecture research and system evaluation tool, simulators are widely used in industrial production and research fields, which can improve the production and development efficiency of hardware and architecture, shorten the development cycle, and at the same time improve the efficiency of related research and shorten unnecessary waiting time.

In order to ensure the accuracy of the simulation results during the simulation process, the existing simulation models usually simulate each functional unit in a clock-driven manner. Although this tightly coupled approach ensures the accuracy of the simulation results, it causes the simulation model to face serious performance challenges. In order to increase the simulation speed, there have been many related researches on simulator acceleration. According to different acceleration methods, analog acceleration technology can be roughly divided into FPGA-based acceleration technology, sampling technology and parallel acceleration.

FPGA-based acceleration technology: This technology mainly uses the high efficiency and parallelism of FPGA and other hardware platforms to improve the running speed of the simulator, and its simulation speed can generally reach the order of magnitude of 10 MIPS. Because it can be 10-100 orders of magnitude faster than software simulators, this technology has been widely used by some famous foreign universities and research institutions. However, the parameter adjustment of the simulator system developed based on FPGA is complicated, and the FPGA netlist file needs to be regenerated every time the parameter is adjusted. However, in the process of netlist file generation and mapping to FPGA, the debugging of the system is very complicated, which limits the ease of use of this method. At the same time, although FPGA is a kind of hardware simulation, since the main frequency of the current FPGA system is more than an order of magnitude slower than that of mainstream general-purpose processors, the low main frequency of FPGA also causes the simulation speed of this technology to be limited. There are certain limitations in lifting.

Sampling acceleration technology: Sampling technology is another commonly used simulator acceleration technology. The principle of sampling technology is to infer the characteristics of the whole by obtaining the characteristics of the subset of simulated test program instructions. The key to obtaining more accurate simulation results for this type of technology is to ensure that the characteristics of the selected subset can fully represent the overall characteristics of the test program. feature. Although sampling techniques can increase simulation speed, sampling techniques need to sacrifice simulation accuracy while improving performance. At the same time, due to the complexity of parallel programs, sampling technology can only improve the performance of multi-core simulators. Currently, typical multi-core sampling simulators can only achieve a simulation speed of several MIPS.

Parallel simulation technology: With the popularity of multi-core hardware platforms, the underlying hardware environment provides more computing resources. How to use the computing resources of the underlying hardware as much as possible to accelerate the execution speed of the simulator has gradually attracted people's attention. In existing research on simulator parallelism, one approach is to manually parallelize existing multi-core simulators. Although this method can obtain a relatively good acceleration effect, it is very cumbersome. Another method is to design a new programming model for the simulator, and then write the simulator program based on the model, and then automatically divide the simulator in parallel on this basis. Although this method provides an automatic parallel method, it cannot be applied to various simulators developed based on the serial model that are still widely used at present because of the specific programming model. Although parallel simulation can improve simulation performance, the current parallel simulation is also facing great challenges. In a multi-core processor, there are usually shared hardware resources between cores, such as a shared Cache or an on-chip network. In order to ensure the accuracy of the simulation, the parallel simulation threads need frequent synchronization to ensure the accuracy of the simulation results. However, this approach leads to poor parallel scalability. Some parallel methods improve parallel performance by reducing synchronization, but lead to a loss of simulation accuracy.

In view of the fact that these technical solutions cannot perform fast simulation while ensuring accuracy, the present invention proposes a method for constructing a simulation system platform based on instruction calculation simulation model and speculative execution technology, which improves the performance and usability of the processor simulation system. At the same time, the present invention can run on any computer of the existing corresponding system, and can accurately and quickly simulate different hardware structures, systems and applications that can be supported. The application of this system is conducive to improving the efficiency of processor design and corresponding software development, and reducing development costs; this system greatly advances software development, effectively shortens the development cycle of computer software and hardware products, and is beneficial to the development of computer software and hardware development industry. It is of great significance. At the same time, this system can be widely used in the research field to improve the efficiency of processor design and related software and hardware research.

Contents of the invention

The purpose of the present invention is to provide a processor software simulation method and system that can improve the development efficiency of the processor and its corresponding software, reduce the development cost, and shorten the development cycle.

The processor software simulation method provided by the present invention is based on an instruction calculation model, including:

First of all, the simulation process is carried out around the instruction sequence, and the simulation method of calculating the timing information of the instructions one by one replaces the simulation method of the traditional simulator updating the state of the functional module based on the clock cycle. The simulator obtains the emission of the instructions flowing through the functional components through calculation. cycles and completed cycles rather than by simulating the execution of processor components on a per-cycle basis.

Secondly, using multi-threaded parallelism to accelerate the computing process, the processor accesses shared resources in a speculative manner, that is, private resources maintain a backup of shared resources. When the system needs to access shared resources, it first bases Shared resource information speculates the actual access cycle for its own subsequent calculations, thereby reducing synchronization operations and improving performance. In the process of speculative execution, in order to ensure the accuracy of the timing information of accessing shared resources, each private resource module will send the access information to the shared resource module, and a global timing correction algorithm will perform correct execution timing calculations. If the speculative execution timing is inconsistent with the actual shared resource calculation timing, the timing correction algorithm calculates the accumulated error, and feeds back the accumulated error to the processor core that generated the error after the program simulation ends. This feedback mechanism can eliminate the error caused by Errors caused by private cores interactively accessing shared resources.

The specific process of the method of the present invention is as follows: the system simulates running the target system image and application program through binary translation, extracts the instruction flow and memory access information; according to the extracted instruction flow and memory access information, calculates the timing information of the instruction during execution, When it comes to access to shared resources, use the speculative execution method of virtual shared resource calculation simulation to reduce synchronous operations, collect shared resource access information, uniformly perform correct shared resource timing calculations and accumulate correction results, and perform feedback compensation after system execution. Timing results and microarchitecture information are eventually returned at the end of execution.

For traditional simulators, the simulation process is mainly based on the execution process of processor components in each clock cycle. For each processor core of the target architecture, it is necessary to maintain the state information of each core processor component and the corresponding input Output information. At each clock cycle during the simulation, all components on each core need to check the input information storage block to determine the instruction that the component will execute, then simulate the behavior of this instruction in the component, update the component status and then Store it to the output information storage block. This approach has some drawbacks in the simulation process. First of all, each core needs to maintain a large number of information storage blocks, and each component needs to access the corresponding information storage blocks in each clock cycle to determine its input instructions, status updates, and output instruction execution status, which will generate many memory accesses operation, resulting in the reduction of continuous reuse of memory information, increasing the clock cycle required for access and thus affecting performance; secondly, since each component will determine the operation performed in its simulation according to the information of the input instruction, since these information check operations are input-related, Therefore, many jump operations that fail to predict will be brought, which will affect the simulation efficiency; in addition, because there is a process of information transfer between different components on the processor every clock cycle, there is a tight coupling between these components, and it is difficult to take advantage of multi-core The platform performs simulation acceleration. Due to the above defects, the traditional simulation method has great limitations in the performance of the simulator, and cannot effectively improve the execution speed.

The main advantage of this method is that the timing information of the simulated instruction stream is obtained by calculating the instruction clock cycle, which replaces the simulation method in which the original simulator updates the state of the processor components for each clock cycle, and finally obtains the timing information of the instruction stream. Significantly improves the simulation efficiency.

For an instruction, after the decoding work is completed, the execution process and the involved components have been clarified, and the number of timings required for each stage of the instruction execution can be determined by calculation. An ideal processor only needs to consider the component resources required for instruction execution. For the actual execution process, various factors need to be considered. The first is data dependence. During the simulation process, there may be register dependence and memory access queues. In addition, resource competition needs to be considered, including resources such as functional units, launch widths, instruction windows, and reordering queues; jump prediction results are also will have an impact on instruction timing. For each instruction, taking the above conditions into the calculation process, the timing calculation can be performed, and the timing changes in the overall execution process can be accurately simulated by calculation, thereby greatly improving the simulation efficiency.

For the jump instruction, the calculation method can ignore the calculation of the wrong path and reduce unnecessary calculation overhead. Due to the fact that the instruction sequence may be inconsistent with the actual execution sequence in the out-of-order execution of the calculation based on the instruction flow, the method records the latest calculated instruction flow through the sequence instruction window. , recalculate from the conflicting instruction. Cache replacement also has a similar situation. The method records the access clock cycle of the cache line, and replaces the cache line with the later clock cycle first when replacing.

Because traditional simulators share resources and private resources in a tightly coupled manner, when traditional simulators are accelerated by multi-core platforms, a large number of synchronous operations are required to ensure correct timing, which greatly limits the acceleration effect of multi-core platforms. This method uses a multi-core platform for acceleration. When it comes to the access simulation of shared resources, the tight coupling between private resources and shared resources is released. In the private resource part, each core virtual maintains the access to shared resources, so that private resource access can be achieved. Conduct reasonable speculative execution. When the private resource module judges that it needs to access the shared resource, it first guesses the number of clock cycles that the shared resource needs to spend based on the information it maintains, and continues its subsequent calculations based on the result. Afterwards, the relevant information is passed to the shared resource module for unified calculation, and the shared module receives all simulated checks of shared resource access and calculates the correct shared resource access timing. When the calculated result of the shared resource is inconsistent with the guessed result of the private resource, it means that the guess of the private resource is wrong. In order to avoid interrupting the simulation process of each processor core, the shared resource module only accumulates the number of clock cycles that each core needs to compensate, and feeds back the accumulated results for compensation when the system execution ends. This method improves the modularity of the overall structure while improving the simulation performance, making it easier to optimize.

The simulation system based on the above simulation method is divided into three parts, the function simulation subsystem, the timing instruction calculation simulation subsystem, and the timing correction subsystem. Among them, the functional simulation subsystem corresponds to the generation of instruction sequences in the simulation process, simulates the operation of the target system image and application program through binary translation, and extracts the instruction flow and memory access information; the timing instruction calculation simulation subsystem corresponds to the instruction sequence in the simulation process Calculation of stream timing information; the timing correction subsystem corresponds to the timing correction calculation, and is responsible for compensating and correcting errors caused by speculative execution during the simulation process. Based on the instruction flow and memory access information extracted by the functional simulation subsystem, the timing instruction calculation simulation subsystem calculates the clock cycle of each instruction flowing through various functional components and the timing information when it is completed, and the calculation involving shared resources is executed through speculation The timing required for accessing shared resources is speculated in the same way; the timing instruction calculation simulation subsystem transmits the shared resource access information to the timing correction subsystem, and the timing correction subsystem uniformly performs the correct shared resource timing calculation, compares the speculative execution timing with the correct timing and accumulates Error timing, feedback compensation is performed after the system execution ends, and the timing results and microarchitecture information are finally returned when the system execution ends.

The simulation system constructed based on this method can be installed on any computer of the existing corresponding system.

A method for triggering an analog system based on a command center, specifically comprising the following:

(1) When it is necessary to test a certain system architecture or an application program, the user specifies an operating system image and application program; the user uses the corresponding target operating system image to start the system;

(2) Select the application program to be executed, and the function simulation subsystem simulates the execution of the target program under the target system through binary translation, and collects instruction flow information and memory access information;

(3) The timing simulation subsystem obtains the instruction flow, calculates the cycle and completion cycle of the current instruction flowing through the functional component according to the status and timing of the functional component, and updates the status and timing of the functional component to ensure the correct calculation of the subsequent instruction flow;

(4) The simulation involving shared resources removes the tight coupling between private resources and shared resources. In the private resource part, each core virtual maintains access to shared resources, so that private resource access can be reasonably speculatively executed, and the Access instructions and speculative execution results are passed to the timing correction subsystem;

(5) The shared module receives all simulated accesses to the shared resources and calculates the correct access timing of the shared resources. When the calculated result of the shared resource is inconsistent with the guessed result of the private resource, it means that the guess of the private resource is wrong. In order to avoid interrupting the simulation process of each processor core, the shared resource module only accumulates the number of clock cycles that need to be compensated for each core, and feeds back the accumulated results for compensation at the end of the system execution;

(6) When the system finishes executing, return timing calculation results and microarchitecture information.

Preferably, the system-wide multi-core parallel method is used to perform function simulation and timing calculation results to provide the impact of the system on the execution of the application system.

Preferably, state compression is used to reduce the amount of information transmission between subsystems and improve overall execution efficiency.

The benefits of this method are: a simulation system based on the command center can be constructed, the simulation and evaluation of the architecture can be accelerated, the efficiency of the software and hardware testing and evaluation of the architecture can be improved, the development cycle can be shortened, and the demand for increasingly rapid software and hardware development can be met.

The system has strong usability and is easy to use and popularize. The main performances are: (1) The simulation system can run on any corresponding system computer; (2) The logic of the simulation method is clear, easy to understand, and can be used quickly for architecture development; (3) The coupling of the simulation system is small, and it is easy to use various This method improves performance and further shortens the development cycle; (4) The application program is easy to deploy, and can quickly execute new applications and give accurate evaluation. (5) It can shorten the development cycle of the system structure and corresponding software and hardware, and further improve product competitiveness.

Description of drawings

Fig. 1 is the essential difference between the present invention and the traditional simulation method.

Figure 2 is a schematic diagram of the structure of the speculative execution model.

Fig. 3 is a structural schematic diagram of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to the accompanying drawings and examples. What needs to be explained before this is that the terms or words used in this specification and claims should not be limitedly interpreted as the usual meaning or the meaning in the dictionary, but should be based on the best way for the inventor to explain the term. The principle of properly defining the concepts is interpreted as meanings and concepts consistent with the technical idea of the present invention. Subsequently, the embodiment described in this description and the structure shown in the drawings are only one of the best embodiments of the present invention, and cannot fully represent the technical ideas of the present invention, so it should be understood that there may be possible Various equivalents and modifications are substituted.

One of the specific implementation manners is a multi-core full-system simulator for instruction calculation simulation.

In this implementation case, the simulation system is deployed on a local multi-core development machine, and the system-wide functional simulation subsystem can adopt single-thread or multi-thread configuration to perform functional simulation and collect instruction flow and memory access information; the timing simulation subsystem adopts the number of threads and Corresponding to the functional simulator; the timing correction subsystem uses a separate thread to simulate the access execution of shared resources and perform timing correction. The main workflow of the system is as follows:

(1) The user uses the corresponding target operating system image to start the system;

(2) Select the application program to be executed, and the function simulation subsystem simulates the execution of the target program under the target system through binary translation, and collects instruction flow information and memory access information;

(3) The timing simulation subsystem obtains the instruction flow, calculates the cycle and completion cycle of the current instruction flowing through the functional component according to the status and timing of the functional component, and updates the status and timing of the functional component to ensure the correct calculation of the subsequent instruction flow;

(4) The simulation involving shared resources removes the tight coupling between private resources and shared resources. In the private resource part, each core virtual maintains access to shared resources, so that private resource access can be reasonably speculatively executed, and the Access instructions and speculative execution results are passed to the timing correction subsystem;

(5) The shared module receives all simulated accesses to the shared resources and calculates the correct access timing of the shared resources. When the calculated result of the shared resource is inconsistent with the guessed result of the private resource, it means that the guess of the private resource is wrong. In order to avoid interrupting the simulation process of each processor core, the shared resource module only accumulates the number of clock cycles that need to be compensated for each core, and feeds back the accumulated results for compensation at the end of the system execution;

(6) After the execution of the system, the timing calculation result information and micro-architecture information are returned, including the impact of the system on the application program, so as to guide further development.

The above steps (2) and (3) can allocate resources according to the number of physical cores of the development computer, which can effectively use physical resources and further improve simulation efficiency.

The second specific embodiment is a user state simulator for instruction calculation simulation.

In this implementation case, the simulation system only simulates the user mode application, and the developer can specify the operating system image or put the application executable file into the operating system image provided by the simulation system. The main workflow of the system is as follows:

(1) The user uses the corresponding target operating system image to start the system;

(2) Select the application program to be executed, and the function simulation subsystem simulates the execution of the target program under the target system through binary translation, and collects instruction flow information and memory access information;

(3) The timing simulation subsystem obtains the instruction flow, calculates the cycle and completion cycle of the current instruction flowing through the functional component according to the status and timing of the functional component, and updates the status and timing of the functional component to ensure the correct calculation of the subsequent instruction flow;

(4) The simulation involving shared resources removes the tight coupling between private resources and shared resources. In the private resource part, each core virtual maintains access to shared resources, so that private resource access can be reasonably speculatively executed, and the Access instructions and speculative execution results are passed to the timing correction subsystem;

(5) The shared module receives all simulated accesses to the shared resources and calculates the correct access timing of the shared resources. When the calculated result of the shared resource is inconsistent with the guessed result of the private resource, it means that the guess of the private resource is wrong. In order to avoid interrupting the simulation process of each processor core, the shared resource module only accumulates the number of clock cycles that need to be compensated for each core, and feeds back the accumulated results for compensation at the end of the system execution;

(6) After the execution of the system, the timing calculation result information and micro-architecture information are returned, and the developers can guide further development according to the execution status of the user-mode application based on the information.

It should be noted that although the present invention has been described and illustrated with reference to specific embodiments, it does not mean that the present invention is limited to these described embodiments, and those skilled in the art can derive many different variants therefrom, for example, the system Deploying the cloud, etc., they will all be covered in the true spirit and scope of the claims of the present invention.

Claims (3)

1. A simulation method based on command calculation model and feedback compensation, characterized in that: First of all, the simulation process is carried out around the instruction sequence, and the simulation method of calculating the timing information of the instructions one by one replaces the simulation method of the traditional simulator updating the state of the functional module based on the clock cycle. The simulator obtains the emission of the instructions flowing through the functional components through calculation. cycles and completed cycles, rather than by simulating the execution of processor components at each cycle; Secondly, using multi-threaded parallelism to accelerate the computing process, the processor accesses shared resources in a speculative manner, that is, private resources maintain a backup of shared resources. When the system needs to access shared resources, it first bases Shared resource information guesses the actual access cycle for its own subsequent calculations, thereby reducing synchronous operations to improve performance; in the process of speculative execution, in order to ensure the accuracy of access to shared resource timing information, each private resource module sends access information to For the shared resource module, a global timing correction algorithm is used to calculate the correct execution timing; if the speculative execution timing is inconsistent with the actual shared resource calculation timing, the global timing correction algorithm calculates the accumulated error and feeds back the accumulated error to compensate after the program simulation ends to the processor core that generated the error; The specific process is: the system simulates running the target system image and application program through binary translation, and extracts the instruction flow and memory access information; according to the extracted instruction flow and memory access information, calculates the timing information of the instruction during execution; The access to shared resources reduces synchronous operations through the speculative execution method of virtual shared resource calculation simulation, collects shared resource access information, uniformly performs correct shared resource timing calculations and accumulates correction results, and performs feedback compensation after system execution ends, and system execution ends eventually returns timing results and microarchitecture information. 2. A simulation system based on the simulation method of claim 1, characterized in that it comprises: a functional simulation subsystem, a timing instruction calculation simulation subsystem, and a timing correction subsystem; wherein the timing correction subsystem corresponds to timing correction calculation, Responsible for compensating and correcting errors caused by speculative execution during the simulation process; the functional simulation subsystem corresponds to the generation of instruction sequences during the simulation process, simulates and runs the target system image and application program through binary translation, and extracts the instruction stream and memory Access information; timing instruction calculation simulation subsystem corresponds to the calculation of instruction flow timing information in the simulation process; based on the instruction flow and memory access information extracted by the functional simulation subsystem, calculate the clock cycle and completion of each instruction flowing through various functional components The timing information of the time sequence information, and the calculation involving shared resources speculatively executes the timing required for shared resource access; the timing instruction calculation simulation subsystem transmits the shared resource access information to the timing correction subsystem, and the timing correction subsystem uniformly performs correct Timing calculation of shared resources, compare speculative execution timing with correct timing and accumulate error timing, perform feedback compensation after system execution ends, and finally return timing results and microarchitecture information at the end of system execution. 3. A trigger method based on the analog system described in claim 2, characterized in that the specific steps are as follows: (1) When it is necessary to test a system architecture or an application, the user specifies an operating system image and application; (2) Select the application program to be executed, and the function simulation subsystem simulates the execution of the target program under the target system through binary translation, and collects instruction flow information and memory access information; (3) The timing simulation subsystem obtains the instruction flow, calculates the cycle and completion cycle of the current instruction flowing through the functional component according to the status and timing of the functional component, and updates the status and timing of the functional component to ensure the correct calculation of the subsequent instruction flow; (4) The simulation involving shared resources removes the tight coupling between private resources and shared resources. In the private resource part, each core virtual maintains access to shared resources, so that private resource access can be reasonably speculatively executed, and the Access instructions and speculative execution results are passed to the timing correction subsystem; (5) The shared module receives all simulated and checked shared resource accesses and calculates the correct shared resource access timing; when the calculated results of the shared resources are inconsistent with the guessed results of the private resources, it means that the private resources are wrongly guessed; in order to avoid interrupting each processor In the core simulation process, the shared resource module only accumulates the number of clock cycles that need to be compensated for each core, and feeds back the accumulated results for compensation at the end of the system execution; (6) When the system finishes executing, return timing calculation results and microarchitecture information.