CN107046163A - Mesa-shaped active area solid plasma diode fabricating method for preparing holographic antenna - Google Patents

Abstract

The present invention relates to a kind of mesa-shaped active area solid plasma diode fabricating method for being used to prepare holographic antenna.The manufacture method includes：(a) SOI substrate is chosen；(b) etching SOI substrate formation mesa-shaped active area；(c) p-type Si materials and N-type Si materials formation P areas and N areas are deposited respectively using doping process in situ to the mesa-shaped active area surrounding；(d) polycrystalline Si material is deposited in the mesa-shaped active area surrounding；(e) make lead and photoetching PAD to form the solid plasma diode in the polycrystalline Si material surface.The embodiment of the present invention can be prepared using doping process in situ and provide the solid plasma diode of the high-performance mesa-shaped active area suitable for forming holographic antenna.

Description

Fabrication method of solid-state plasma diode with terrace-shaped active region for preparing holographic antenna

technical field

The invention relates to the technical field of semiconductor device manufacturing, in particular to a method for manufacturing a solid-state plasma diode in a table-shaped active region for preparing a holographic antenna.

Background technique

Due to its relatively large weight and volume, the traditional metal antenna is inflexible in design and manufacture, and its self-reconfiguration and adaptability are poor, which seriously restricts the development and performance improvement of radar and communication systems. Therefore, in recent years, the theory of antenna broadband, miniaturization, and reconfiguration and multiplexing has become increasingly active.

Against this background, the researchers proposed a new antenna concept-plasma antenna, which is a radio-frequency antenna that uses plasma as a guiding medium for electromagnetic radiation. The plasma antenna can change the instantaneous bandwidth of the antenna by changing the plasma density, and has a large dynamic range; it can also adjust the frequency, beam width, power, gain and direction of the antenna by changing the plasma resonance, impedance and density, etc. In addition, when the plasma antenna is not excited, the radar cross section is negligible, while the antenna is only excited during the short time of communication transmission or reception, which improves the concealment of the antenna. These properties can be widely used Used in various reconnaissance, early warning and countermeasure radars, spaceborne, airborne and missile antennas, microwave imaging antennas, microwave communication antennas with high signal-to-noise ratio, etc., it has greatly attracted the attention of researchers at home and abroad, and has become a field of antenna research. hotspots.

However, most of the current research is limited to gaseous plasma antennas, and the research on solid-state plasma antennas is almost blank. Solid-state plasma generally exists in semiconductor devices, and it does not need to be wrapped in a dielectric tube like gaseous plasma, which has better safety and stability. Theoretical studies have found that when a solid-state plasma diode is biased with DC, the DC current will form a solid-state plasma composed of free carriers (electrons and holes) on its surface. The plasma has metal-like properties, that is, it has Reflection, its reflection characteristics are closely related to the microwave transmission characteristics, concentration and distribution of surface plasmons.

Therefore, how to make a solid-state plasmonic diode to apply to the holographic antenna becomes particularly important.

Contents of the invention

Therefore, in order to solve the technical defects and deficiencies existing in the prior art, the present invention proposes a method for manufacturing a solid-state plasma diode in a mesa-shaped active region for preparing a holographic antenna.

Specifically, an embodiment of the present invention proposes a method for manufacturing a solid-state plasma diode in a table-shaped active region for preparing a holographic antenna. The solid-state plasma diode is used for manufacturing a holographic antenna. The manufacturing method includes steps:

(a) select SOI substrate;

(b) using a CVD process to form a first protective layer on the surface of the SOI substrate;

(c) using a first mask plate to form an active region pattern on the first protective layer by using a photolithography process;

(d) using a dry etching process to etch the first protective layer and the top Si layer of the SOI substrate around the designated position of the active region pattern to form the mesa-shaped active region;

(e) Depositing a P-type Si material and an N-type Si material around the mesa-shaped active region by an in-situ doping process to form a P region and an N region;

(f) depositing polycrystalline Si material around the terrace-shaped active region;

(g) making leads on the surface of the polycrystalline Si material and photoetching the PAD to form the solid-state plasma diode.

In one embodiment of the present invention, after step (d), also include:

(x1) using an oxidation process to oxidize the sidewalls of the mesa-shaped active region to form an oxide layer on the sidewalls of the mesa-shaped active region;

(x2) Etching the oxide layer by using a wet etching process to planarize the sidewall of the mesa-shaped active region.

In one embodiment of the invention, step (e) includes:

(e1) depositing a second protective layer on the entire substrate surface;

(e2) using a second mask plate to form a P-region pattern on the surface of the second protective layer by photolithography;

(e3) using a wet etching process to remove the second protective layer on the pattern in the P region;

(e4) Depositing a P-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process to form the P region;

(e5) depositing a third protective layer on the entire substrate surface;

(e6) using a third mask to form an N-region pattern on the surface of the third protective layer by photolithography;

(e7) using a wet etching process to remove the third protective layer on the N-region pattern;

(e8) Depositing N-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process to form the N region.

In one embodiment of the invention, step (e4) includes:

(e41) Depositing a P-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process;

(e42) Etching the P-type Si material by using a fourth mask using a dry etching process to form the P region on the sidewall of the mesa-shaped active region;

(e43) Using a selective etching process to remove the second protective layer on the entire surface of the substrate.

In one embodiment of the invention, step (e8) includes:

(e81) Depositing N-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process;

(e82) Etching the N-type Si material by using a fifth mask using a dry etching process to form the N region on the other sidewall of the mesa-shaped active region;

(e83) Using a selective etching process to remove the third protection layer on the entire surface of the substrate.

In one embodiment of the invention, step (f) includes:

(f1) depositing the polycrystalline Si material around the mesa-shaped active region by using a CVD process;

(f2) Depositing a fourth protective layer on the entire substrate surface by using a CVD process;

(f3) activating impurities in the P region and the N region by an annealing process.

In one embodiment of the invention, step (g) comprises:

(g1) using a sixth mask plate to form a lead hole pattern on the surface of the fourth protective layer by using a photolithography process;

(g2) using an anisotropic etching process to etch the polycrystalline Si material in the leaked part of the fourth protective layer to form the lead hole;

(g3) sputtering a metal material on the lead hole to form a metal silicide;

(g4) Passivate and photolithographically PAD to form the solid state plasma diode.

In one embodiment of the present invention, the antenna module (13) includes a first solid-state plasma diode antenna arm (1301), a second solid-state plasma diode antenna arm (1302), a coaxial feeder (1303), a first DC Bias line (1304), second DC bias line (1305), third DC bias line (1306), fourth DC bias line (1307), fifth DC bias line (1308), sixth DC bias line Bias line (1309), seventh DC bias line (1310), eighth DC bias line (1311).

In one embodiment of the present invention, the first solid-state plasma diode antenna arm (1301) includes the first solid-state plasma diode string (w1), the second solid-state plasma diode string (w2) and the third solid-state plasma diode string A solid-state plasma diode string (w3), the second solid-state plasma diode antenna arm (1302) includes a fourth solid-state plasma diode string (w4), a fifth solid-state plasma diode string (w5) and the sixth solid-state plasma diode string (w5) sequentially connected in series The plasma diode string (w6) and the first solid state plasma diode string (w1) and the sixth solid state plasma diode string (w6), the second solid state plasma diode string (w2) and the fifth solid state plasma diode string The string (w5), said third solid state plasma diode string (w3) and said fourth solid state plasma diode string (w4) each comprise an equal number of solid state plasma diodes.

It can be seen from the above that the embodiment of the present invention can avoid the adverse effects caused by ion implantation by using in-situ doping, and can control the doping concentration of the material by controlling the gas flow rate, which is more conducive to obtaining a steep doping interface. So as to obtain better device performance. The solid-state plasma diode plasma reconfigurable antenna can be composed of SOI-based solid-state plasma diodes arranged in an array, and the solid-state plasma diodes in the array are selectively turned on by external control, so that the array forms dynamic solid-state plasma stripes and has an antenna It has the function of transmitting and receiving specific electromagnetic waves, and the antenna can change the shape and distribution of solid-state plasma stripes through the selective conduction of solid-state plasma diodes in the array, so as to realize the reconstruction of the antenna. It is used in national defense communication and radar technology has important application prospects.

Other aspects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. It should be understood, however, that the drawings are designed for purposes of illustration only and not as a limitation of the scope of the invention since reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale and are merely intended to conceptually illustrate the structures and processes described herein.

Description of drawings

The specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a holographic antenna according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a holographic antenna module according to an embodiment of the present invention;

3 is a flow chart of a method for manufacturing a solid-state plasma diode in a table-shaped active region of a holographic antenna according to an embodiment of the present invention;

4a-4s are schematic diagrams of another method for manufacturing a solid-state plasma diode in a table-shaped active region for preparing a holographic antenna according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another device structure of a solid-state plasma diode in a mesa-shaped active region for preparing a holographic antenna according to an embodiment of the present invention.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

The invention proposes a platform-shaped active region solid-state plasma diode suitable for forming a holographic antenna and a manufacturing method thereof. The solid-state plasma diode can be a lateral pin diode based on Silicon-On-Insulator (SOI) on an insulating substrate. When a DC bias is applied, the DC current will form free carriers (electrons and The solid-state plasma composed of holes) has metal-like characteristics, that is, it has a reflection effect on electromagnetic waves, and its reflection characteristics are closely related to the microwave transmission characteristics, concentration and distribution of surface plasmons.

Hereinafter, the process flow for preparing the solid-state plasma diode in the mesa-shaped active region of the holographic antenna manufactured by the present invention will be further described in detail. In the drawings, the thicknesses of layers and regions are enlarged or reduced for convenience of description, and the shown sizes do not represent actual sizes.

Embodiment one

Please refer to Fig. 3. Fig. 3 is a flowchart of a method for manufacturing a solid-state plasma diode in a table-shaped active region of a holographic antenna according to an embodiment of the present invention. This method is suitable for preparing a holographic antenna, and the solid-state plasma diode is mainly used for making Solid state plasma antenna. The method comprises the steps of:

(a) select SOI substrate;

Among them, for step (a), the reason for using SOI substrate is that solid-state plasma antennas require good microwave characteristics, and solid-state plasma diodes need to have good carriers, that is, solid-state plasmas, in order to meet this requirement. ability, and silicon dioxide (SiO ₂ ) can confine carriers, that is, solid-state plasma, in the top layer of silicon, so SOI is preferably used as the substrate of solid-state plasma diodes.

(b) using a CVD process to form a first protective layer on the surface of the SOI substrate;

(c) using a first mask plate to form an active region pattern on the first protective layer by using a photolithography process;

(d) using a dry etching process to etch the first protective layer and the top Si layer of the SOI substrate around the designated position of the active region pattern to form the mesa-shaped active region;

(e) Depositing a P-type Si material and an N-type Si material around the mesa-shaped active region by an in-situ doping process to form a P region and an N region;

(f) depositing polycrystalline Si material around the terrace-shaped active region;

(g) making leads on the surface of the polycrystalline Si material and photoetching the PAD to form the solid-state plasma diode.

Wherein, after step (d), also include:

(x1) using an oxidation process to oxidize the sidewalls of the mesa-shaped active region to form an oxide layer on the sidewalls of the mesa-shaped active region;

(x2) Etching the oxide layer by using a wet etching process to planarize the sidewall of the mesa-shaped active region.

The advantage of doing this is that it can prevent the protrusion of the trench side wall from forming an electric field concentration area, causing breakdown of the Pi and Ni junctions.

Furthermore, step (e) includes:

(e1) depositing a second protective layer on the entire substrate surface;

(e2) using a second mask plate to form a P-region pattern on the surface of the second protective layer by photolithography;

(e3) using a wet etching process to remove the second protective layer on the pattern in the P region;

(e4) Depositing a P-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process to form the P region;

(e5) depositing a third protective layer on the entire substrate surface;

(e6) using a third mask to form an N-region pattern on the surface of the third protective layer by photolithography;

(e7) using a wet etching process to remove the third protective layer on the N-region pattern;

(e8) Depositing N-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process to form the N region.

It should be noted that in the conventional manufacturing process of the P-region and N-region of solid-state plasma diodes, the implantation process is used to form. This method requires a large implantation dose and energy, requires high equipment, and is incompatible with the existing process; However, although the diffusion process is used, although the junction depth is deeper, the area of the P region and the N region is relatively large, the degree of integration is low, and the doping concentration is uneven, which affects the electrical performance of the solid-state plasma diode, resulting in the uncertainty of the concentration and distribution of the solid-state plasma. Poor control.

The use of in-situ doping can avoid the adverse effects of ion implantation and other methods, and can control the doping concentration of the material by controlling the gas flow rate, which is more conducive to obtaining a steep doping interface, thereby obtaining better device performance.

Wherein, step (e4) comprises:

(e41) Depositing a P-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process;

(e42) Etching the P-type Si material by using a fourth mask using a dry etching process to form the P region on the sidewall of the mesa-shaped active region;

(e43) Using a selective etching process to remove the second protective layer on the entire surface of the substrate.

In one embodiment of the invention, step (e8) includes:

(e81) Depositing N-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process;

(e82) Etching the N-type Si material by using a fifth mask using a dry etching process to form the N region on the other sidewall of the mesa-shaped active region;

(e83) Using a selective etching process to remove the third protection layer on the entire surface of the substrate.

Furthermore, step (f) includes:

(f1) depositing the polycrystalline Si material around the mesa-shaped active region by using a CVD process;

(f2) Depositing a fourth protective layer on the entire substrate surface by using a CVD process;

(f3) activating impurities in the P region and the N region by an annealing process.

Furthermore, step (g) includes:

(g1) using a sixth mask plate to form a lead hole pattern on the surface of the fourth protective layer by using a photolithography process;

(g2) using an anisotropic etching process to etch the polycrystalline Si material in the leaked part of the fourth protective layer to form the lead hole;

(g3) sputtering a metal material on the lead hole to form a metal silicide;

(g4) Passivate and photolithographically PAD to form the solid state plasma diode.

The embodiment of the present invention can prepare and provide a solid-state plasma diode suitable for forming a high-performance mesa-shaped active region of a holographic antenna by using an in-situ doping process.

Embodiment two

Please refer to Fig. 4a-Fig. 4s. Fig. 4a-Fig. 4s are schematic diagrams of another method for manufacturing a solid-state plasma diode in a table-shaped active region for preparing a holographic antenna according to an embodiment of the present invention. On the basis of the first embodiment above, the The preparation of a mesa-shaped active region solid-state plasma diode with a solid-state plasma region length of 100 μm is described in detail as an example, and the specific steps are as follows:

S10, selecting an SOI substrate.

Referring to FIG. 4a, the crystal orientation of the SOI substrate 101 is (100). In addition, the doping type of the SOI substrate 101 is p-type, and the doping concentration is 10 ¹⁴ cm ⁻³ . The thickness of the top layer Si is, for example, 20 μm.

S20, depositing a layer of silicon nitride on the surface of the SOI substrate.

Referring to FIG. 4 b , a silicon nitride layer 201 is deposited on an SOI substrate 101 by a chemical vapor deposition (Chemical vapor deposition, CVD for short) method.

S30, etching the SOI substrate to form trenches in the active region.

Please refer to FIG. 4c-1, a mesa active region pattern is formed on the silicon nitride layer by photolithography, and the protective layer and The top layer of silicon forms a mesa active region 301 , please refer to FIG. 4c-2 for a top view.

S40 , planarizing the periphery of the active area of the mesa.

Referring to FIG. 4d-1, the sidewalls around the active region of the mesa are oxidized to form an oxide layer 401 on the sidewalls around the active region of the mesa. See FIG. 4d-2 for a top view;

Referring to FIG. 4e-1, the sidewall oxide layer around the mesa active region is etched by a wet etching process to complete the planarization of the sidewall around the mesa active region. See 4e-2 for the top view.

S50. Deposit a layer of SiO ₂ on the surface of the substrate.

Referring to FIG. 4f, a layer of silicon dioxide 601 is deposited on the substrate by CVD.

S60, photoetching the SiO ₂ layer.

Referring to FIG. 4g, a P region pattern is formed on the SiO ₂ layer by a photolithography process, and the SiO ₂ layer on the P region pattern is removed by a wet etching process.

S70, forming a P region.

Please refer to Fig. 4h, the specific method may be: use the in-situ doping method to deposit p-type silicon on the P-region pattern on the surface of the SOI substrate to form the P-region 801, and control the doping of the P-region by controlling the gas flow rate. impurity concentration.

S80, planarizing the surface of the substrate.

Please refer to FIG. 4i , the specific method may be: first use a dry etching process to flatten the surface of the P region, and then use a wet etching process to remove the SiO ₂ layer on the substrate surface.

S90, depositing a layer of SiO ₂ on the surface of the substrate.

Referring to FIG. 4j , the specific method may be: deposit a silicon dioxide layer 1001 on the surface of the substrate by CVD.

S100, photoetching the SiO ₂ layer.

Referring to FIG. 4k, a photolithography process is used to form an N region pattern on the SiO ₂ layer; a wet etching process is used to remove the SiO ₂ layer on the N region.

S110, forming an N region.

Referring to Fig. 4l, using in-situ doping method, n-type silicon is deposited on the N-region pattern on the surface of the SOI substrate to form an N-region 1201, and the doping concentration of the N-region is controlled by controlling the gas flow.

S120, planarizing the surface of the substrate.

Please refer to Fig. 4m, the surface of N region is flattened by dry etching process, and then the SiO ₂ layer on the substrate surface is removed by wet etching process.

S130, depositing a polysilicon layer.

Referring to FIG. 4n, the metal layer 1401 can be sputtered in the trench by CVD.

S140, forming a silicon dioxide (SiO ₂ ) layer on the surface.

Referring to FIG. 4o, a silicon dioxide (SiO ₂ ) layer 1501 can be deposited on the surface by CVD with a thickness of 500nm.

S150, flat surface.

Referring to FIG. 4p, the surface silicon dioxide and silicon nitride (SiN) layers can be removed by CMP to make the surface smooth.

S160, impurity activation.

Anneal at 950-1150° C. for 0.5-2 minutes to activate the ion-implanted impurities and advance the impurities in the active region.

S170, photoetching lead holes.

Referring to FIG. 4q, a wiring hole 1701 is photolithographically etched on the silicon dioxide (SiO ₂ ) layer.

S180, forming leads.

Referring to FIG. 4r , metal can be sputtered on the surface of the substrate, alloyed to form a metal silicide, and the metal on the surface can be etched away; then metal 1801 can be sputtered on the surface of the substrate to lithographically lead wires.

S190, passivation treatment, photolithography PAD.

Referring to FIG. 4s, the passivation layer 1901 can be formed by depositing silicon nitride (SiN), and the PAD is photoetched. Finally, a solid-state plasma diode is formed as a material for preparing a solid-state plasma antenna.

Embodiment three

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of another device structure of a solid-state plasma diode in a mesa-shaped active region for preparing a holographic antenna according to an embodiment of the present invention. The solid-state plasma diode is manufactured by the above-mentioned manufacturing method as shown in FIG. 3 . Specifically, the solid-state plasma diode is formed on an SOI substrate 301, and the P region 303, the N region 304 of the pin diode, and the I region laterally located between the P region 303 and the N region 304 are all located on the SOI substrate within the top layer of silicon 302 .

In summary, the principle and implementation of the solid-state plasma diode and its manufacturing method of the present invention have been described by using specific examples in this paper. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time For those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the present invention. The scope of protection should be determined by the appended claims.

Claims (9)

1. a method for manufacturing a table-shaped active region solid-state plasma diode for preparing a holographic antenna, characterized in that, the solid-state plasma diode is used to make a holographic antenna, and the holographic antenna comprises: a semiconductor substrate (11), an antenna Module (13), the first holographic ring (15) and the second holographic ring (17); the antenna module (13), the first holographic ring (15) and the second holographic ring ( 17) All are fabricated on the semiconductor substrate (11) by semiconductor technology; wherein, the antenna module (13), the first holographic ring (15) and the second holographic ring (17) are all It includes solid-state plasma diode strings connected in series in sequence. The manufacturing method comprises the steps of: (a) select SOI substrate; (b) using a CVD process to form a first protective layer on the surface of the SOI substrate; (c) using a first mask plate to form an active region pattern on the first protective layer by using a photolithography process; (d) using a dry etching process to etch the first protective layer and the top Si layer of the SOI substrate around the designated position of the active region pattern to form the mesa-shaped active region; (e) Depositing a P-type Si material and an N-type Si material around the mesa-shaped active region by an in-situ doping process to form a P region and an N region; (f) depositing polycrystalline Si material around the terrace-shaped active region; (g) making leads on the surface of the polycrystalline Si material and photoetching the PAD to form the solid-state plasma diode. 2. manufacturing method as claimed in claim 1, is characterized in that, after step (d), also comprises: (x1) using an oxidation process to oxidize the sidewalls of the mesa-shaped active region to form an oxide layer on the sidewalls of the mesa-shaped active region; (x2) Etching the oxide layer by using a wet etching process to planarize the sidewall of the mesa-shaped active region. 3. The manufacturing method according to claim 1, wherein step (e) comprises: (e1) depositing a second protective layer on the entire substrate surface; (e2) using a second mask plate to form a P-region pattern on the surface of the second protective layer by photolithography; (e3) using a wet etching process to remove the second protective layer on the pattern in the P region; (e4) Depositing a P-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process to form the P region; (e5) depositing a third protective layer on the entire substrate surface; (e6) using a third mask to form an N-region pattern on the surface of the third protective layer by photolithography; (e7) using a wet etching process to remove the third protective layer on the N-region pattern; (e8) Depositing N-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process to form the N region. 4. manufacturing method as claimed in claim 3, is characterized in that, step (e4) comprises: (e41) Depositing a P-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process; (e42) Etching the P-type Si material by using a fourth mask using a dry etching process to form the P region on the sidewall of the mesa-shaped active region; (e43) Using a selective etching process to remove the second protective layer on the entire surface of the substrate. 5. manufacturing method as claimed in claim 3, is characterized in that, step (e8) comprises: (e81) Depositing N-type Si material on the sidewall of the mesa-shaped active region by using an in-situ doping process; (e82) Etching the N-type Si material by using a fifth mask using a dry etching process to form the N region on the other sidewall of the mesa-shaped active region; (e83) Using a selective etching process to remove the third protection layer on the entire surface of the substrate. 6. The manufacturing method according to claim 1, wherein step (f) comprises: (f1) depositing the polycrystalline Si material around the mesa-shaped active region by using a CVD process; (f2) Depositing a fourth protective layer on the entire substrate surface by using a CVD process; (f3) activating impurities in the P region and the N region by an annealing process. 7. The manufacturing method according to claim 6, wherein step (g) comprises: (g1) using a sixth mask plate to form a lead hole pattern on the surface of the fourth protective layer by using a photolithography process; (g2) using an anisotropic etching process to etch the polycrystalline Si material in the leaked part of the fourth protective layer to form the lead hole; (g3) sputtering a metal material on the lead hole to form a metal silicide; (g4) Passivate and photolithographically PAD to form the solid state plasma diode. 8. The manufacturing method according to claim 1, characterized in that, the antenna module (13) comprises a first solid-state plasma diode antenna arm (1301), a second solid-state plasma diode antenna arm (1302), a coaxial feeder ( 1303), the first DC bias line (1304), the second DC bias line (1305), the third DC bias line (1306), the fourth DC bias line (1307), the fifth DC bias line (1308), the sixth DC bias line (1309), the seventh DC bias line (1310), and the eighth DC bias line (1311). 9. manufacturing method as claimed in claim 8, is characterized in that, described first solid-state plasma diode antenna arm (1301) comprises the first solid-state plasma diode string (w1), the second solid-state plasma diode string ( w2) and the third solid-state plasma diode string (w3), the second solid-state plasma diode antenna arm (1302) includes the fourth solid-state plasma diode string (w4) and the fifth solid-state plasma diode string (w5) connected in series ) and the sixth solid state plasma diode string (w6) and the first solid state plasma diode string (w1) and the sixth solid state plasma diode string (w6), the second solid state plasma diode string (w2) and The fifth solid-state plasma diode string (w5), the third solid-state plasma diode string (w3) and the fourth solid-state plasma diode string (w4) respectively include the same number of solid-state plasma diodes.