CN107039369A - Encapsulation includes the encapsulation stacking structure and its manufacture method of the encapsulation - Google Patents

Abstract

Provided are a package, a package stack structure including the package, and a manufacturing method of the package and the package stack structure. The package includes: a substrate having a first surface and a second surface facing away from the first surface, and including a first pad and a second pad disposed on the first surface and separated from each other; a chip mounted on the first surface of the substrate a surface and electrically connected to the first pad; a bump, disposed on the second pad, including a first end contacting the second pad and a second end opposite to the first end; and an encapsulation member, enclosing Encapsulating at least a portion of the chip and at least a portion of the bump, and exposing the second end of the bump.

Description

Package, package stack structure including the package and manufacturing method thereof

This application is a divisional application of a patent application with an application date of January 23, 2015, an application number of 201510036267.0, and a patent application titled "Package, Package Stack Structure Including the Package, and Manufacturing Method".

technical field

The present invention relates to the field of semiconductor packaging, more specifically, to a package, a package stack structure including the package, and a manufacturing method of the package and the package stack structure.

Background technique

As electronic devices become smaller in size, high integration density has been achieved by stacking a plurality of chips in one semiconductor package or stacking a plurality of semiconductor packages. For example, in order to reduce the area occupied by the circuit board, a package stack structure (package-on-package, also called package-on-package or package-on-package) in which one package is stacked on another package is currently widely used. Research is ongoing to improve or ensure the manufacturing yield and reliability of package stacks.

Contents of the invention

An object of the present invention is to provide a semiconductor package, a package stack structure including the package, and a method for manufacturing the package and the package stack structure.

Another object of the present invention is to provide a semiconductor package, a package stack structure including the package, and a method for manufacturing the package and the package stack structure, which help to improve or ensure manufacturing yield and/or reliability.

A package is provided, which includes: a substrate having a first surface and a second surface facing away from the first surface, and including a first pad and a second pad disposed on the first surface and separated from each other; a chip , mounted on the first surface of the substrate and electrically connected to the first pad; bumps, disposed on the second pad, including a first end contacting the second pad and a second end opposite to the first end; And an encapsulation member encapsulating at least a part of the chip and at least a part of the bump, and exposing the second end of the bump.

The substrate may include a plurality of second pads separated from each other, and the package may include a plurality of bumps respectively disposed on the plurality of second pads.

The package may further include a bump disposed between the chip and the first pad, and the chip may be electrically connected to the first pad through the bump.

The package may further include a first bonding wire electrically connecting the chip to the first pad. The package may also include a second bonding wire electrically connecting the chip to the bump.

The bump may include a plurality of sub-bumps sequentially stacked on the second pad in a direction substantially perpendicular to the first surface, and at least an uppermost sub-bump among the plurality of sub-bumps may be exposed to the encapsulation member. of the exterior.

The bump may include a first sub-bump and a second sub-bump sequentially stacked on the second pad in a direction substantially perpendicular to the first surface.

The package may further include a first bonding wire electrically connecting the chip to the first pad and a second bonding wire electrically connecting the chip to a joint between the first sub-bump and the second sub-bump.

The bumps may be manufactured by a wire bonding process using a wire bonding machine. Each sub-bump may be fabricated by a wire bonding process using a wire bonding machine.

The bumps may have non-uniform dimensions in a direction substantially perpendicular to the first surface. Each sub-bump may have a non-uniform size in a direction substantially perpendicular to the first surface.

The bump may have a columnar shape in which a middle portion thereof in a direction substantially perpendicular to the first surface is larger in size and first and second ends are smaller in size. Each of the sub-bumps may have a columnar shape in which a middle portion thereof in a direction substantially perpendicular to the first surface has a larger size and an end portion thereof in a direction substantially perpendicular to the first surface has a smaller size.

The bumps may have the shape of a nail head. Each sub-bump may have the shape of a nail head.

The bumps may be formed of gold, silver, copper or alloys thereof.

The second end of the bump may be lower than the top surface of the encapsulation member. The bump may have a height of 80% or more of a height of the encapsulation member.

The enclosing member may include a recess receiving the second end of the bump and having a size greater than that of the second end of the bump. The encapsulation member may include a recess receiving the exposed end of the uppermost sub-bump and having a size larger than that of the exposed end.

The depth of the depression may not exceed half the height of the uppermost sub-bump.

The pitch of the plurality of bumps may not exceed 300 μm.

The package may further include external connection terminals attached to the second surface of the substrate.

There is also provided a method of manufacturing a package, the method comprising: providing a substrate having a first surface and a second surface facing away from the first surface and including a first pad and a second pad disposed on the first surface and separated from each other. Two bonding pads; installing a chip on the first surface of the substrate, and electrically connecting the chip to the first bonding pad; setting a bump on the second bonding pad, so that the bump includes a first end contacting the second bonding pad and contacting the second bonding pad. a second end opposite the first end; encapsulating at least a portion of the chip and the bump with an encapsulation member; and removing a portion of the encapsulation member disposed on the second end of the bump to expose the second end of the bump.

The substrate may include a plurality of second pads separated from each other, and the step of disposing bumps on the second pads may include disposing a plurality of bumps on the plurality of second pads, respectively.

The step of providing bumps may include: sequentially providing a plurality of sub-bumps on the second pad along a direction substantially perpendicular to the first surface.

The step of arranging the plurality of sub-bumps may include arranging a first sub-bump on the second pad and arranging a second sub-bump on the first sub-bump in a direction substantially perpendicular to the first surface, and the method may further include : between setting the first sub-bump and setting the second sub-bump, electrically connecting the chip to the first sub-bump with a bonding wire.

The step of disposing bumps on the second pads may include: disposing bumps on the second pads through a wire bonding process using a wire bonding machine.

The portion of the encapsulation member disposed on the second end of the bump may be removed with a laser.

There is also provided a package stack structure including a first package and a second package stacked on the first package. The first package may include: a first substrate having a first surface and a second surface opposite to the first surface, and including first pads and second pads disposed on the first surface and separated from each other; a first chip , mounted on the first surface of the substrate and electrically connected to the first pad; bumps, disposed on the second pad, including a first end contacting the second pad and a second end opposite to the first end; And a first encapsulation member encapsulating at least a portion of the first chip and at least a portion of the bump, and exposing a second end of the bump. The second package may include: a second substrate having a third surface and a fourth surface facing away from the third surface; a second chip mounted on the third surface and electrically connected to the second substrate; a second encapsulation member encapsulating encapsulating at least a portion of the second chip; and an external connection member attached to the fourth surface. External connection members are fixed on the bumps so that the second package is electrically connected to the first package.

The first substrate may include a plurality of second pads separated from each other, the first package may include a plurality of bumps respectively arranged on the plurality of second pads, and the second package may include bumps respectively fixed on the plurality of bumps. Multiple external connection components.

The bump may include a plurality of sub-bumps sequentially stacked on the second pad in a direction substantially perpendicular to the first surface, and the external connection member may be fixed on an uppermost sub-bump among the plurality of sub-bumps .

The bumps may be manufactured by a wire bonding process using a wire bonding machine. Each sub-bump may be fabricated by a wire bonding process using a wire bonding machine.

The first enclosing member may include a recess receiving the second end of the bump and having a size greater than that of the second end of the bump. The external connection member may include at least a portion disposed within the recess.

There is also provided a method of manufacturing a package stack structure, the method including providing a first package, providing a second package, and stacking the second package on the first package. The step of providing the first package may include: providing a first substrate having a first surface and a second surface facing away from the first surface and including a first pad and a second pad disposed on the first surface and separated from each other ; install the first chip on the first surface of the first substrate, and electrically connect the first chip to the first pad; set the bump on the second pad, so that the bump includes a first pad contacting the second pad; end and a second end opposite to the first end; encapsulating at least a part of the chip and the bump with a first encapsulation member; and removing a portion of the first encapsulation member disposed on the second end of the bump to expose The second end of the bump. The step of providing the second package may include: providing a second substrate having a third surface and a fourth surface facing away from the third surface; mounting a second chip on the third surface of the second substrate, and electrically connecting the second chip to the second substrate; encapsulating at least a part of the second chip with the second encapsulation member; and attaching the external connection terminal to the fourth surface of the second substrate. Stacking the second package on the first package may include: disposing external connection terminals on the bumps; and performing reflow on the external connection terminals so that the external connection terminals become external connections fixed on the bumps. member.

The first substrate may include a plurality of second pads separated from each other, the step of arranging bumps on the second pads may include arranging a plurality of bumps on the plurality of second pads respectively, and the step of attaching external connection terminals may include: Including attaching the plurality of external connection terminals, the step of stacking the second package on the first package may include disposing the plurality of external connection terminals on the plurality of bumps, respectively.

The step of arranging bumps on the second pad may include sequentially stacking a plurality of sub-bumps on the second pad in a direction substantially perpendicular to the first surface, and the step of arranging external connection terminals on the bumps may include An external connection terminal is provided on an uppermost sub-bump among the plurality of sub-bumps.

The bumps may be fabricated by a wire bonding process using a wire bonding machine. Each sub-bump may be fabricated by a wire bonding process using a wire bonding machine.

The step of removing the portion of the first encapsulating member disposed on the second end of the bump may include forming a recess in the first enclosing member that accommodates the second end of the bump and has a size greater than that of the second end of the bump. . The external connection member may include at least a portion disposed within the recess.

There is also provided a package, which includes: a substrate; a chip mounted on the substrate and electrically connected to the substrate; a bump mounted on the substrate and electrically connected to the substrate, and located at a side of the chip; and an encapsulation member encapsulating the substrate. At least a portion of the chip and at least a portion of the bump, and the top of the bump is exposed.

There is also provided a package, which includes: a substrate; a chip mounted on the substrate and electrically connected to the substrate; a plurality of bumps mounted on the substrate and electrically connected to the substrate, and located around the chip; and an encapsulation member encapsulating the At least a portion of the chip and at least a portion of each of the plurality of bumps are encapsulated, and a top of each bump is exposed.

There is also provided a package including: a substrate; a chip mounted on the substrate and electrically connected to the substrate; an encapsulation member encapsulating at least a part of the chip; and a bump provided on the substrate and embedded in the encapsulation member , wherein the encapsulation member has an opening exposing the bump.

Description of drawings

The above and/or other aspects and advantages of the present invention will become clear and easier to understand through the following description of the embodiments in conjunction with the accompanying drawings, in which:

1 is a schematic cross-sectional view illustrating a package stack structure of the related art;

2 is a schematic cross-sectional view illustrating a package stack structure according to an exemplary embodiment of the present invention;

3 is a schematic top view illustrating a substrate of a lower package included in the package stack structure according to an exemplary embodiment of the present invention shown in FIG. 2;

4 is a partial cross-sectional view illustrating a lower package included in the package stack structure according to an exemplary embodiment of the present invention shown in FIG. 2;

5 is a schematic cross-sectional view illustrating a package stack structure according to another exemplary embodiment of the present invention;

6 is a schematic cross-sectional view illustrating a package stack structure according to still another exemplary embodiment of the present invention;

7A to 7F are schematic cross-sectional views illustrating a method of manufacturing a package (ie, a lower package included in a package stack structure) according to an exemplary embodiment of the present invention;

8A to 8E are schematic cross-sectional views illustrating a method of manufacturing a sub-bump included in a package according to an exemplary embodiment of the present invention;

8F to 8H are schematic cross-sectional views partially illustrating a method of manufacturing a sub-bump included in a package according to another exemplary embodiment of the present invention;

9A to 9D are schematic cross-sectional views illustrating a method of manufacturing an upper package included in a package stack structure according to an exemplary embodiment of the present invention;

10A to 10C are schematic cross-sectional views at least partially illustrating a method of manufacturing a package stack structure according to an exemplary embodiment of the present invention; and

11A to 11F are schematic cross-sectional views illustrating a method of manufacturing a package (ie, a lower package included in a package stack structure) according to another exemplary embodiment of the present invention.

detailed description

Hereinafter, the inventive concept will be described in detail by explaining exemplary embodiments with reference to the accompanying drawings. However, the inventive concepts may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will inform the present Those of ordinary skill in the art fully convey the inventive concept. In the drawings, the same reference numerals denote the same elements. Furthermore, various elements and regions are shown schematically. Accordingly, the inventive concepts are not limited to the relative sizes or distances shown in the drawings.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from teaching of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the inventive concepts. As used herein, the singular forms "a", "an", "the", and "said" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "comprising" and/or "comprising" when used in this specification indicate the presence of stated features, integers, steps, operations, elements and/or components but do not exclude the presence of Or add one or more other features, integers, steps, operations, elements, components and/or groups thereof.

For the convenience of description, spatially relative terms may be used herein to describe the relationship of one element or feature to other elements or features shown in the figures, such as "under", "beneath", "beneath" ", "above" and "above" etc. It will be understood that these spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of "below" and "above". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Exemplary embodiments are described with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

Unless otherwise defined, the terms (including technical terms and scientific terms) used in this specification have the same meaning as commonly understood by those of ordinary skill in the art. Terms defined in general dictionaries should be construed to have the same meanings as in the context of related art, and they should not be construed in idealized or overly formalized meanings unless defined in this specification.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

FIG. 1 is a schematic cross-sectional view illustrating a package stack structure of the related art. Referring to FIG. 1 , a related art package stack structure 10 includes a lower package 11 and an upper package 12 stacked on each other. Both the lower package 11 and the upper package 12 may be ball grid array (BGA) semiconductor packages. Each of the lower package 11 and the upper package 12 may include: a substrate having a plurality of pads disposed on upper and lower surfaces thereof and a plurality of patterned wires disposed therein; a semiconductor chip mounted on an upper surface of the substrate. and electrically connected to pads on the upper surface of the substrate through bonding wires; an encapsulating member encapsulating the semiconductor chip, the bonding wires, and at least a part of the upper surface of the substrate; and a plurality of external connection terminals attached to the pads on the lower surface of the substrate pad. Each of the external connection terminals may be a solder ball.

A plurality of external connection terminals 13 of the upper package 12 are arranged on the pads not encapsulated by the encapsulation member on the upper surface of the substrate of the lower package 11 and are electrically connected to these pads, thereby realizing the connection between the upper package 12 and the lower package 11. electrical connection between. As the size of the electronic device to which the package stack structure 10 is applied becomes smaller and more functional, the size of the package stack structure 10 becomes smaller and more functional, so that the external connection terminal 13 The pitch (pitch) is also getting smaller and smaller. Since the external connection terminals 13 such as solder balls become soft and are easily deformed or collapsed during high-temperature reflow, short circuits between the external connection terminals 13 are likely to occur when the pitch of the external connection terminals 13 becomes small, such as crossover between solder balls. couplet. Therefore, the manufacturing yield and reliability of the package stack structure 10 will be reduced.

Hereinafter, a package and a package stack structure including the package according to exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a schematic cross-sectional view illustrating a package stack structure according to an exemplary embodiment of the present invention. 3 is a schematic top view illustrating a substrate of a lower package included in a package stack structure according to an exemplary embodiment of the present invention. 4 is a partial cross-sectional view illustrating a lower package included in a package stack structure according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , a package 110 according to an exemplary embodiment of the present invention is included in a package stack structure 100 according to an exemplary embodiment of the present invention. The package stack structure 100 according to an exemplary embodiment of the present invention includes a package (hereinafter referred to as a “lower package” for convenience of description) 110 and an upper package 120 stacked on each other.

2 to 4, the lower package 110 includes: a substrate 111; a chip 112 mounted on the substrate 111 and electrically connected to the substrate 111; a bump 115 disposed on the substrate 111 and electrically connected to the substrate 111; and an encapsulation member 114 , encapsulating at least a portion of the chip 112 and at least a portion of each of the bumps 115 , and exposing an upper end of each of the bumps 115 .

The substrate 111 may have an upper surface 111a on which the chips 112 and bumps 115 are disposed, and a lower surface 111b facing away from the upper surface 111a. The substrate 111 may have a chip area DA in which the chip 112 is disposed and a peripheral area PA outside the chip area DA, and include a plurality of first pads P1 (see FIG. ) and a plurality of second pads P2 (see FIG. 3 ) disposed on the upper surface 111a and located in the peripheral area PA. The substrate 111 may further include a plurality of pads (not shown) disposed on the lower surface 111b and an inner portion of the pads disposed inside the substrate 111 to connect the first pad P1 and the second pad P2 to the lower surface 111b. leads (not shown). The substrate 111 may be a printed circuit board (PCB).

Although FIG. 3 shows that the peripheral area PA surrounds the chip area DA, the present invention is not limited thereto. The peripheral area PA may be disposed on at least one side of the chip area DA. Although FIG. 3 shows that the plurality of second pads P2 surrounds the plurality of first pads P1, the present invention is not limited thereto. The plurality of second pads P2 may be disposed on at least one side of the plurality of first pads P1.

The chip 112 is flip-chip mounted on the substrate 111 and electrically connected to the substrate 111 . In this case, the chip 112 has an active surface facing the substrate 111 and an inactive surface facing away from the substrate 111 . The chip 112 is mounted on the plurality of first pads P1 of the substrate 111 using a plurality of bumps 113 disposed between the active surface of the chip 112 and the plurality of first pads P1 of the substrate 111 .

The bump 115 is located in the peripheral area PA of the substrate 111 and disposed on each of the plurality of second pads P2. Each bump 115 includes two sub-bumps stacked in sequence, ie, a first sub-bump 115a disposed on the second pad P2 and a second sub-bump 115b disposed on the first sub-bump 115a. The first sub-bump 115a is completely encapsulated by the encapsulation member 114, and the lower part of the second sub-bump 115b in contact with the first sub-bump 115a is encapsulated by the encapsulation member 114, and the upper part of the second sub-bump 115b is not It is encapsulated by the encapsulation member 114 and exposed to the outside. That is, each bump 115 is embedded in the encapsulation member 114 and has a top (eg, a top surface) exposed to the outside of the encapsulation member 114 .

In one exemplary embodiment, each of the first sub-bump 115 a and the second sub-bump 115 b may be manufactured by wire bonding (also referred to as “wire bonding”) at low cost using a wire bonding machine. Each of the first sub-bump 115a and the second sub-bump 115b may have a non-uniform size (for example, width or diameter) in its height direction, that is, the first sub-bump 115a and the second sub-bump Each of the bumps 115b may have at least one largest dimension and at least one smallest dimension in its height direction. The first sub-bump 115a and the second sub-bump 115b may have substantially the same height, or different heights. In an exemplary embodiment, each of the first sub-bump 115a and the second sub-bump 115b may have a columnar shape in which the middle portion in the height direction is larger in size and the two ends in the height direction are smaller in size. . In another exemplary embodiment, each of the first sub-bump 115a and the second sub-bump 115b may have a nail head shape. However, the shape of each of the first sub-bump 115a and the second sub-bump 115b is not particularly limited.

Each of the first sub-bump 115a and the second sub-bump 115b may be formed of at least one of gold, silver, and copper, however, the material used to form the first sub-bump 115a and the second sub-bump 115b is different. subject to specific restrictions.

The encapsulation member 114 encapsulates at least a portion of the chip 112 and at least a portion of each of the bumps 115 to protect these members from an external environment or external impact. The encapsulation member 114 may further enclose the plurality of bumps 113 and at least a portion of the upper surface 111 a of the substrate 111 . As shown in FIG. 2 , the inactive surface of the chip 112 is not encapsulated by the encapsulation member 114 and exposed to the outside; however, the present invention is not limited thereto, and the inactive surface of the chip 112 may be encapsulated by the encapsulation member 114 .

The encapsulation member 114 further includes a plurality of recesses C for accommodating the exposed end of each second sub-bump 115b and having a size (eg, width) larger than that of the exposed end of the second sub-bump 115b. , so that the second sub-bump 115b has a lower portion enclosed by the encapsulation member 114 and an upper portion not enclosed by the encapsulation member 114 but exposed to the outside. That is, the second sub-bump 115b is exposed to the outside through the recess C. Referring to FIG.

Referring to FIG. 4, the first sub-bump 115a and the second sub-bump 115b have substantially the same height. In an exemplary embodiment, each of the first sub-bump 115a and the second sub-bump 115b has a height not exceeding 100 μm, for example, a height not exceeding 75 μm, a height not exceeding 50 μm, a height not exceeding 25 μm. height, etc. The first sub-bump 115a and the second sub-bump 115b have substantially the same diameter or width. In an exemplary embodiment, each of the first sub-bump 115a and the second sub-bump 115b has a diameter or width of not more than 200 μm, more specifically, a diameter or width of not more than 175 μm, and a diameter of not more than 150 μm. Diameter or width, diameter or width not exceeding 125 μm, diameter or width not exceeding 100 μm, diameter or width not exceeding 75 μm, or diameter or width not exceeding 50 μm, etc.

The total height h _B of the bump 115 is smaller than the height h _E of the encapsulation member 114 , so that the top surface of the second sub-bump 115 b is lower than the top surface of the encapsulation member 114 . In an exemplary embodiment, the total height h _B of the bump 115 may be more than 80%, more specifically, more than 85%, more than 90%, or more than 95% of the height h _E of the encapsulation member 114 . In an exemplary embodiment, the difference between the overall height h _B of the bump 115 and the height h _E of the encapsulation member 114 may not exceed 75 μm, eg, not exceed 50 μm, not exceed 25 μm, not exceed 10 μm, and so on.

The depth _DR of the recess C may not exceed half of the height of the second sub-bump 115b, more specifically, 1/3, 1/4; and may not exceed 1/3 of the height h _E of the encapsulation member 114, more specifically , 1/5, 1/7, 1/9. In an exemplary embodiment, the depth _DR of the recess C may not exceed 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or the like.

The pitch of the plurality of bumps 115 (ie, the distance between corresponding points on adjacent bumps 115 among the plurality of bumps 115 ) may be small. In an exemplary embodiment, the plurality of bumps 115 have a pitch not exceeding 300 μm, more specifically, not exceeding 250 μm, not exceeding 200 μm, not exceeding 175 μm, not exceeding 150 μm, not exceeding 125 μm, not exceeding 100 μm, not exceeding 75μm, or not more than 50μm, etc.

Although FIG. 2 and FIG. 4 show that the encapsulation member 114 includes an exposed end portion for accommodating each second sub-bump 115b and has a size (eg, width) greater than that of the exposed end portion of the second sub-bump 115b. The plurality of depressions C of the size of the portion, and the top surface of the second sub-bump 115b is lower than the top surface of the encapsulation member 114, but the present invention is not limited thereto. In another exemplary embodiment, the encapsulation member includes only through-holes for accommodating the exposed ends of each bump and having a size (eg, width) equal to the size of the exposed ends of the bumps, such that All parts (eg sides) of the bump at its height are in contact with the encapsulating member and are encapsulated. In this case, the top surface of the bump may have the same height as the top surface of the encapsulation member, ie the top surface of the bump is flush with the top surface of the encapsulation member. In yet another exemplary embodiment, the bump has a portion protruding beyond the top surface of the encapsulation member such that the top surface of the bump is higher than the top surface of the encapsulation member.

Although FIG. 3 shows that each bump 115 includes two sub-bumps, the present invention is not limited thereto. A bump may include only one sub-bump or more than two sub-bumps. The overall height of the bump can be adjusted by adjusting the size of each sub-bump and/or the number of sub-bumps.

Although FIGS. 2 and 4 illustrate that the lower package 110 includes the plurality of bumps 115 corresponding to the plurality of second pads P2, the present invention is not limited thereto. The lower package may include only one bump corresponding to one second pad P2. Although FIG. 2 shows that the lower package 110 includes one chip 112, the present invention is not limited thereto. The lower package may include multiple chips.

The lower package 110 may further include external connection terminals 116 attached to a plurality of pads (not shown) on the lower surface 111 b of the substrate 111 . Each of the external connection terminals 116 may be a solder ball. Accordingly, the chip 112 may be electrically connected to external devices through the first pad P1 , the inner leads, the plurality of pads on the lower surface 111 b and the external connection terminal 116 . In the lower package 110, the external connection terminal 116 is not an essential member.

The upper package 120 includes: a substrate 121 with an upper surface 121a and a lower surface 121b facing away from the upper surface 121a; a first chip 122a and a second chip 122b, the first chip 122a is attached to the upper surface of the substrate 121 by a chip adhesive film 127a 121a and is electrically connected to the pad (not shown) on the upper surface 121a of the substrate 121 through the bonding wire 128, the second chip 122b is attached to the active surface of the first chip 122a through the chip adhesive film 127b and is connected to the active surface of the first chip 122a through the bonding wire 129a and 129b are electrically connected to the pads (not shown) on the upper surface 121a of the substrate 121; the encapsulation member 124 encloses the first chip 122a, the second chip 122b and the bonding wires 128, 129a and 129b; and more An external connection member 126 ′ is attached to the pad on the lower surface 121b of the substrate 121 .

The substrate 121 may further include internal leads (not shown) disposed inside the substrate 121 to connect the pads on the upper surface 121a to the pads on the lower surface 121b. The substrate 121 may be a printed circuit board (PCB). The first chip 122a and the second chip 122b may be electrically connected to external devices such as the lower package 110 through pads on the upper surface 121a, internal leads, pads on the lower surface 121b, and external connection members 126'.

Although FIG. 2 shows that the upper package 120 includes two chips mounted on the substrate 121 by wire bonding, the present invention is not limited thereto. The upper package may include at least one chip flip-chip mounted on the substrate or mounted on the substrate by wire bonding.

A plurality of external connection members 126 ′ are disposed on each of the plurality of bumps 115 and are electrically connected to each bump 115 , thereby achieving electrical connection between the upper package 120 and the lower package 110 . The first chip 122 a and the second chip 122 b may be electrically connected to the external connection terminal 116 and/or the chip 112 through at least the external connection member 126 ′ and the bump 115 .

Each of the plurality of external connection members 126 ′ has at least a portion disposed in the recess C of the enclosing member 114 . Each of the plurality of external connection members 126' may be manufactured by reflow with solder balls, as explained later when describing a method of manufacturing a package stack structure according to an exemplary embodiment of the present invention.

Since the lower package 110 has the bumps 115 exposed to the outside of the encapsulation member 114 and the external connection members 126' of the upper package 120 are disposed on the bumps 115 and electrically connected to each bump 115, the same as shown in FIG. Compared with the package stack structure 10 of the related art, the size (such as thickness or width) of the external connection terminals 126 (see FIG. 9D ) (such as solder balls) (such as solder balls) of the upper package 120 to be used to form the external connection members 126' can be reduced. . Therefore, even if the pitch of the external connection terminals 126 of the upper package 120 becomes smaller, the problem of a short circuit between the external connection terminals caused by deformation or collapse of the external connection terminals can be prevented or suppressed due to the small size of the external connection terminals, Thereby improving manufacturing yield and reliability.

The pitch of the external connection terminals 126 (see FIG. 9D ) of the upper package 120 may be equal to the pitch of the plurality of bumps 115 . In an exemplary embodiment, the pitch of the external connection terminals 126 (see FIG. 9D ) exceeds 300 μm, more specifically, does not exceed 250 μm, does not exceed 200 μm, does not exceed 175 μm, does not exceed 150 μm, does not exceed 125 μm, does not exceed 100 μm , not exceeding 75 μm, or not exceeding 50 μm, etc.

FIG. 5 is a schematic cross-sectional view illustrating a package stack structure according to another exemplary embodiment of the present invention. A package stack structure 200 according to another exemplary embodiment of the present invention shown in FIG. 5 has substantially the same or similar configuration as the package stack structure 100 described with reference to FIGS. Reference numerals denote the same elements as those in the package stack structure 100 , and detailed descriptions thereof are omitted. The following description will focus on the differences between the package stack structure 200 and the package stack structure 100 .

5, the lower package 210 includes: a substrate 211 with an upper surface 211a and a lower surface 211b facing away from the upper surface 211a; a chip 212 attached to the upper surface 211a of the substrate 211 by a chip adhesive film 217 and connected by a bonding wire 218 A pad (not shown) electrically connected to the upper surface 211a of the substrate 211; a plurality of bumps 215 disposed on the substrate 211 and electrically connected to the substrate 211; and an encapsulation member 214 encapsulating at least a part of the chip 212 and at least a portion of each of the bumps 215 and the bonding wire 218 , and expose an upper end of each of the bumps 215 .

FIG. 6 is a schematic cross-sectional view illustrating a package stack structure according to still another exemplary embodiment of the present invention. A package stack structure 300 according to yet another exemplary embodiment of the present invention shown in FIG. 6 has substantially the same or similar configuration as the package stack structure 200 described with reference to FIG. The same elements as those in the package stack structure 200 are denoted, and their detailed descriptions are omitted. The following description will focus on the differences between the package stack structure 300 and the package stack structure 200 .

6, the lower package 310 includes: a substrate 311 with an upper surface 311a and a lower surface 311b facing away from the upper surface 311a; a chip 312 attached to the upper surface 311a of the substrate 311 by a chip adhesive film 317 and connected by a bonding wire 318 Electrically connected to pads (not shown) on the upper surface 311a of the substrate 311; a plurality of bumps 315 disposed on the substrate 311 and electrically connected to the substrate 311; and an encapsulation member 314 encapsulating at least a part of the chip 312 and at least a portion of each of the bumps 315 and the bonding wire 318 , and expose an upper end of each of the bumps 315 .

Lower package 310 also includes bond wires 319 electrically connecting chip 312 to bumps 315 . More specifically, the lower package 310 includes a bonding wire 319 electrically connecting the chip 312 to a connection portion between the first sub-bump 315a and the second sub-bump 315b. Accordingly, the chip 312 may be electrically connected to the external connection terminal 316 through at least the bonding wire 319 and the first sub-bump 315a. That is to say, it is not necessary to directly connect all the pads on the active surface of the chip 312 to the pads on the upper surface 311a of the substrate 311, but at least one pad on the active surface of the chip 312 can be connected to the bump 315 . Therefore, the number of pads and wiring density of the substrate 311 can be reduced.

7A to 7F are schematic cross-sectional views illustrating a method of manufacturing a package (for example, the lower package 110 included in the package stack structure 100 ) according to an exemplary embodiment of the present invention. Hereinafter, a method of manufacturing a package according to an exemplary embodiment of the present invention will be described with reference to FIGS. 7A to 7F .

Referring to FIG. 7A , a substrate 111 is provided, and a chip 112 is mounted on the substrate 111 and electrically connected to the substrate 111 . Specifically, the substrate 111 has an upper surface 111a on which the chip 112 is disposed and a lower surface 111b facing away from the upper surface 111a, and has a chip area DA in which the chip 112 is disposed and a peripheral area PA located outside the chip area DA. The chip 112 is mounted on the plurality of first pads P1 of the substrate 111 using a plurality of bumps 113 disposed between the active surface of the chip 112 and the plurality of first pads P1 (see FIG. 3 ) of the substrate 111 . The bump 113 may be a solder bump, an Au bump, or a conductive polymer flexible bump.

Referring to FIG. 7B, a first sub-bump 115a is provided on a plurality of second pads P2 (see FIG. 3) on the upper surface 111a of the substrate 111 and in the peripheral area PA and electrically connected to the first sub-bump 115a. to the substrate 111. Each of the first sub-bumps 115 a may be manufactured on the substrate 111 through a wire bonding process using a wire bonding machine at low cost.

8A to 8E are schematic cross-sectional views illustrating a method of manufacturing a sub-bump included in a package according to an exemplary embodiment of the present invention. An exemplary process of manufacturing the first sub-bump 115 a on the substrate 111 by wire bonding using a wire bonding machine at low cost is described below with reference to FIGS. 8A to 8E . Referring to FIG. 8A , a ball 31 is formed at the tail end of a wire 30 such as gold, silver or copper extending beyond the exit of the riving knife 20 by means of electric spark discharge. Referring to FIG. 8B , the wire 30 is moved relative to the riving knife 20 such that the ball 31 approaches or contacts the riving knife 20 . Referring to FIG. 8C, the rivet 20 and the wire 30 are moved together toward the second pad P2 of the substrate 111, so that the ball 31 contacts the second pad P2, and then heat is applied through the substrate 111 and a bonding force is applied through the rivet 20, while The riving knife 20 is vibrated under the action of ultrasound, thereby forming the welding spot 31'. Referring to Figure 8D, the riving knife 20 is lifted and the wire clamp (not shown) is kept open to feed out a length of tail. Referring to FIG. 8E , the clamp is closed, and the riving knife 20 is moved upwards to cut the wire 30 by stretching and constricting, thereby forming the first sub-bump 115 a. The thus-manufactured first sub-bump 115a may have a nail head shape.

The first sub-bump 115a manufactured by the method described with reference to FIGS. 8A to 8E may have a wire tail. The line tail can be removed through another process to improve the quality and reliability of the first sub-bump 115a.

8F to 8H are schematic cross-sectional views partially illustrating a method of manufacturing a sub-bump included in a package according to another exemplary embodiment of the present invention. Another exemplary process of manufacturing the first sub-bump 115 a on the substrate 111 by wire bonding using a wire bonding machine at low cost is described below with reference to FIGS. 8A to 8D and 8F to 8H . The process of forming a solder joint 31' on the second pad P2 of the substrate 111 and then maintaining a predetermined length of tail wire between the rivet 20 and the solder joint 31' has been described in detail above with reference to FIGS. Let me repeat. Next, referring to Fig. 8F and Fig. 8G, the capillary knife 20 moves slightly along the direction relative to the substrate 111 horizontally and moves toward the side of the solder joint 31', so that the capillary knife 20 approaches or contacts the solder joint 31', and touches the solder joint The wire above 31' heats and applies pressure. Next, referring to FIG. 8G and FIG. 8H , the rivet 20 moves upwards and closes the clamp to cut the wire 30 , thereby forming the first sub-bump 115 a. The thus-manufactured first sub-bump 115a may have a nail head shape. The first sub-bump 115 a manufactured by the method described with reference to FIGS. 8A to 8D and FIGS. 8F to 8H may have a wire tail. The line tail can be removed through another process to improve the quality and reliability of the first sub-bump 115a.

Referring to FIG. 7C, a second sub-bump 115b is disposed on each of the first sub-bumps 115a. The process for disposing the second sub-bump 115b may be substantially the same as or similar to the manufacturing process of the first sub-bump 115a described above with reference to FIGS. 8A to 8H , and thus a detailed description thereof will not be repeated here.

When using a wire bonding machine to fabricate sub-bumps from wires with a diameter of 50 μm according to the process shown in Figures 8A to 8E or the processes shown in Figures 8A to 8D and Figures 8F to 8H, it is possible to obtain Sub-bumps with a width or diameter of 100 μm-150 μm and a height of up to 75 μm. If the bump includes two sub-bumps thus produced, the pitch of the bump may be 200 μm-250 μm. In this case, the encapsulation member 114 may have a height h _E of 150 μm.

When using a wire bonding machine to fabricate sub-bumps from wires with a diameter of 25 μm according to the process shown in Figures 8A to 8E or the processes shown in Figures 8A to 8D and Figures 8F to 8H, it is possible to obtain Sub-bumps with a width or diameter of 50 μm to 70 μm and a height of up to 30 μm. If the bump includes five sub-bumps thus produced, the pitch of the bump may be 100 μm-150 μm. In this case, the encapsulation member 114 may have a height h _E of 150 μm.

Therefore, the size of the sub-bumps can be adjusted by adjusting at least the diameter of the wire, and the size and pitch of the bumps can be adjusted accordingly.

Although it has been described above that the chip 112 is first mounted on the substrate 111 and then the bumps 115 are provided, the present invention is not limited thereto. That is, the process of providing the bumps 115 described with reference to FIGS. 7B and 7C may be performed first, and then the process of mounting the chip 112 on the substrate 111 described with reference to FIG. 7A may be performed.

Referring to FIG. 7D , the chip 112 , the bump 113 , and the bump 115 including the first sub-bump 115 a and the second sub-bump 115 b are encapsulated with the encapsulation member 114 . In an exemplary embodiment, the product shown in FIG. 7C may be placed in a cavity with a mold, and then an encapsulation member precursor such as epoxy molding compound (EMC) is filled in the cavity of the mold, and then The encapsulation member precursor is cured to form the encapsulation member 114 . Here, the encapsulation member 114 encloses the entirety of each of the bumps 115 . The inactive surface of the chip 112 is not encapsulated by the encapsulation member 114 and is exposed to the outside; however, the present invention is not limited thereto, and the inactive surface of the chip 112 may be encapsulated by the encapsulation member 114 .

Referring to FIG. 7E, a portion of the encapsulation member 114 disposed on each second sub-bump 115b is removed to form a plurality of recesses C, thereby exposing each second sub-bump 115b. Accordingly, the second sub-bump 115b has a lower portion enclosed by the encapsulation member 114 and an upper portion not enclosed by the encapsulation member 114 to be exposed to the outside. In an exemplary embodiment, the portion of the encapsulation member 114 may be removed using a laser. Here, the size of each of the plurality of recesses C may be greater than the size of the exposed end of each second sub-bump 115b.

Referring to FIG. 7F , external connection terminals 116 are provided on a plurality of pads (not shown) on the lower surface 111 b of the substrate 111 , thereby completing the lower package 110 . Each of the external connection terminals 116 may be a solder ball. In one exemplary embodiment, solder is applied on each of the plurality of pads on the lower surface 111b of the substrate 111, and then the external connection terminal 116 is formed by performing reflow on the solder.

9A to 9D are schematic cross-sectional views illustrating a method of manufacturing the upper package 120 included in the package stack structure 100 according to an exemplary embodiment of the present invention. Hereinafter, a method of manufacturing the upper package 120 included in the package stack structure 100 according to an exemplary embodiment of the present invention will be described with reference to FIGS. 9A to 9D .

Referring to FIG. 9A , a substrate 121 is provided, and a first chip 122 a and a second chip 122 b are mounted on the substrate 121 and electrically connected to the substrate 121 . Specifically, the substrate 121 has an upper surface 121a and a lower surface 121b facing away from the upper surface 121a. The first chip 122a is attached to the upper surface 121a of the substrate 121 through the die-attach film 127a and the second chip 122b is attached to the active surface of the first chip 122a through the die-attach film 127b. One chip 122a is electrically connected to the pads (not shown) on the upper surface 121a of the substrate 121 and the second chip 122b is electrically connected to the pads (not shown) on the upper surface 121a of the substrate 121 by bonding wires 129a and 129b. out).

Referring to FIG. 9B , the first chip 122 a , the second chip 122 b and the bonding wires 128 , 129 a and 129 b are encapsulated with the encapsulation member 124 . In an exemplary embodiment, the product shown in FIG. 9A can be placed in a cavity with a mold, and then the cavity of the mold is filled with an encapsulation member precursor such as epoxy molding compound (EMC), after which The encapsulation member precursor is cured to form the encapsulation member 124 .

Referring to FIG. 9C , external connection terminal precursors S such as solder paste are provided on a plurality of pads (not shown) on the lower surface 121 b of the substrate 121 . Specifically, a mask M having a plurality of openings OP corresponding to each of a plurality of pads on the lower surface 121 b of the substrate 121 is placed on the lower surface 121 b of the substrate 121 . Then, the external connection terminal precursor S is applied in each opening OP using a tool T. Then, the mask M is removed so that the external connection terminal precursor S remains on the plurality of pads on the lower surface 121 b of the substrate 121 .

Referring to FIG. 9D , reflow is performed on the external connection terminal precursor S attached to the plurality of pads on the lower surface 121 b of the substrate 121 to form external connection terminals 126 such as solder balls. Thus, the upper package 120 is completed.

10A to 10B are schematic cross-sectional views at least partially illustrating a method of manufacturing a package stack structure 100 according to an exemplary embodiment of the present invention. Hereinafter, a method of manufacturing the package stack structure 100 according to an exemplary embodiment of the present invention will be described with reference to FIGS. 10A to 10B .

Referring to FIG. 10A , flux F is attached to each external connection terminal 126 of the upper package 120 . In an exemplary embodiment, a portion of each external connection terminal 126 of the upper package 120 may be dipped in flux such that the flux F is attached to each external connection terminal 126 .

Referring to FIG. 10B , each external connection terminal 126 to which flux F is attached is disposed on each of the plurality of bumps 115 such that flux F is located between the external connection terminals 126 and the bumps 115 . That is, the upper package 120 is stacked on the lower package 110 in a state where the external connection terminals 126 of the upper package 120 are aligned and connected to the bumps 115 of the lower package 110 .

Referring to FIG. 10C, reflow is performed on the external connection terminals 126 such as solder balls of the upper package 120, so that the external connection terminals 126 become external connection members 126' to be fixedly connected (eg, soldered) to the bumps 115, thereby realizing the upper package. 120 and the lower package 110 are mechanically and electrically connected. In the process of performing reflow on the external connection terminal 126 , at least a portion of the melted external connection terminal 126 enters the recess C of the encapsulation member 114 . Therefore, the sidewall of the recess C may serve as a stopper against the movement of the melted external connection terminal 126 to prevent the melted external connection terminal 126 from contacting the adjacent melted external connection terminal 126 to short circuit.

Thus, the package stack structure 100 including the lower package 110 and the upper package 120 is completed.

Since the lower package 110 has the bumps 115 exposed to the outside of the encapsulation member 114 and the external connection members 126' of the upper package 120 are disposed on the bumps 115 and electrically connected to each bump 115, the same as shown in FIG. Compared with the package stack structure 10 of the related art, the size (such as thickness or width) of the external connection terminals 126 (such as solder balls) of the upper package 120 to be used to form the external connection members 126' can be reduced. Therefore, even if the pitch of the external connection terminals 126 of the upper package 120 becomes smaller, the problem of a short circuit between the external connection terminals caused by deformation or collapse of the external connection terminals can be prevented or suppressed due to the small size of the external connection terminals, Thereby improving manufacturing yield and reliability.

In addition, the sub-bump 115 can be easily manufactured through a wire bonding process using a wire bonding machine at low cost, so the package 110 and the package stack structure 100 including the package 110 according to an exemplary embodiment of the present invention can have a low manufacturing cost.

The difference between the package stack structure 200 shown in FIG. 5 and the package stack structure 100 shown in FIG. pads on the upper surface 211 a of the substrate 211 . The substrate 211 may be provided first and the chip 212 may be mounted on the substrate 211 . Specifically, a substrate 211 having an upper surface 211a and a lower surface 211b facing away from the upper surface 211a is firstly provided, the chip 212 is attached to the upper surface 211a of the substrate 211 by a chip adhesive film 217, and then the chip is attached to the substrate 211 by a bonding wire 218. 212 is electrically connected to a pad on the upper surface 211 a of the substrate 211 . Then, the package stack structure 200 may be manufactured using a process substantially the same as or similar to that described with reference to FIGS. 7B to 10C .

11A to 11F are schematic cross-sectional views illustrating a method of manufacturing a package (for example, the lower package 310 included in the package stack structure 300 ) according to another exemplary embodiment of the present invention. Hereinafter, a method of manufacturing a package according to another exemplary embodiment of the present invention will be described with reference to FIGS. 11A to 11F .

Referring to FIG. 11A , a substrate 311 is provided, and a chip 312 is mounted on the substrate 311 . Specifically, the substrate 311 has an upper surface 311a and a lower surface 311b facing away from the upper surface 311a. The chip 312 is attached to the upper surface 311 a of the substrate 311 by a die attach film 317 .

Referring to FIG. 11B , first sub-bumps 315 a are disposed on a plurality of second pads (not shown) on the upper surface 311 a of the substrate 311 . Each of the first sub-bumps 315a may be manufactured on the substrate 311 through a wire bonding process using a wire bonding machine at low cost. The manufacturing method of the first sub-bump 115a has been described above with reference to FIGS. The manufacturing process of 115a is substantially the same or similar, so the process of disposing the first sub-bump 315a on the substrate 311 will not be described in detail here. Then, the chip 312 is electrically connected to the pad (not shown) on the upper surface 311a of the substrate 311 through the bonding wire 318, and the chip 312 is electrically connected to the top surface of the first sub-bump 315a through the bonding wire 319. . Alternatively, the chip 312 may first be electrically connected to pads (not shown) on the upper surface 311a of the substrate 311 through bonding wires 318 and then placed on a plurality of second pads (not shown) on the upper surface 311a of the substrate 311 ( not shown), and then the chip 312 is electrically connected to the top surface of the first sub-bump 315a through the bonding wire 319 .

Referring to FIG. 11C, a second sub-bump 315b is disposed on each of the first sub-bumps 315a. The process for disposing the second sub-bump 315b may be substantially the same as or similar to the manufacturing process of the first sub-bump 115a described above with reference to FIGS. 8A to 8H , and thus a detailed description thereof will not be repeated here. Accordingly, the bonding wire 319 is electrically connected to the connection portion between the first sub-bump 315a and the second sub-bump 315b.

Referring to FIG. 11D , the chip 312 , the bonding wires 318 , 319 , and the bump 315 including the first sub-bump 315 a and the second sub-bump 315 b are encapsulated with the encapsulation member 314 . The process of providing the encapsulation member 314 may be substantially the same as or similar to the process of providing the encapsulation member 114 described with reference to FIG. 7D , so the process of providing the encapsulation member 314 will not be described in detail here.

Referring to FIG. 11E , a portion of the encapsulation member 314 disposed on each second sub-bump 315b is removed to form a plurality of recesses C, thereby exposing each second sub-bump 315b. Accordingly, the second sub-bump 315b has a lower portion enclosed by the encapsulation member 314 and an upper portion not enclosed by the encapsulation member 314 and exposed to the outside. In one exemplary embodiment, the portion of encapsulation member 314 may be removed using a laser. Here, the size of each of the plurality of recesses C may be greater than the size of the exposed end of each second sub-bump 115b.

Referring to FIG. 11F , external connection terminals 316 are provided on a plurality of pads (not shown) on the lower surface 311 b of the substrate 311 , thereby completing the lower package 310 . Each of the external connection terminals 316 may be a solder ball. In one exemplary embodiment, solder is applied on each of the plurality of pads on the lower surface 311b of the substrate 311, and then the external connection terminal 316 is formed by performing reflow on the solder.

The package stack structure 300 shown in FIG. 6 may be manufactured using substantially the same or similar processes as those described with reference to FIGS. 10A to 10C .

Since a package according to an exemplary embodiment of the present invention has bumps exposed to the outside of its encapsulation member and an external connection member of another package to be stacked on the package may be provided on the bumps and electrically connected to each bump point, it is possible to reduce the size of external connection terminals (eg, solder balls) of the other package to be used to form external connection members, compared with the package stack structure of the related art. Therefore, even if the pitch of the external connection terminals of the other package becomes smaller, the problem of short circuit between the external connection terminals caused by deformation or collapse of the external connection terminals can be prevented or suppressed because the size of the external connection terminals is small. , thereby improving manufacturing yield and reliability.

In addition, the bumps in the package according to the exemplary embodiment of the present invention can be easily manufactured through a wire bonding process using a wire bonding machine at low cost, and thus the package according to the exemplary embodiment of the present invention and the package including the same The stacked structure can have low manufacturing cost.

While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. Change.

Claims (9)

1. A package, characterized in that the package comprises: a substrate having a first surface and a second surface facing away from the first surface, and including a first pad and a second pad disposed on the first surface and separated from each other; a chip mounted on the first surface of the substrate and electrically connected to the first pad; A bump, disposed on the second pad, includes a first end contacting the second pad and a second end opposite to the first end, wherein the bump includes a substantially vertical line through a wire bonding process using a wire bonding machine. a plurality of sub-bumps sequentially stacked on the second pad in the direction of the first surface; and The encapsulation member encapsulates at least a part of the chip and at least a part of the bump, and exposes the second end of the bump. 2. The package according to claim 1, wherein the substrate includes a plurality of second pads separated from each other, and the package includes a plurality of bumps respectively disposed on the plurality of second pads. 3. The package of claim 1, wherein at least an uppermost sub-bump among the plurality of sub-bumps is exposed to the outside of the encapsulation member. 4. The package of claim 1, wherein the bumps have non-uniform dimensions in a direction substantially perpendicular to the first surface. 5. The package of claim 1, wherein the second end of the bump is lower than the top surface of the encapsulation member. 6. The package of claim 1, wherein the encapsulating member comprises a recess receiving the second end of the bump and having a size larger than that of the second end of the bump. 7. A method of manufacturing a package, characterized in that it comprises: providing a substrate, the substrate has a first surface and a second surface facing away from the first surface and includes a first pad and a second pad disposed on the first surface and separated from each other; mounting a chip on the first surface of the substrate, and electrically connecting the chip to the first pad; The bump is provided by sequentially stacking a plurality of sub-bumps on the second pad in a direction substantially perpendicular to the first surface by a wire bonding process using a wire bonding machine so that the bump includes a first end contacting the second pad. and a second end opposite the first end; encapsulating at least a portion of the chip and the bumps with an encapsulation member; and A portion of the encapsulation member disposed over the second end of the bump is removed to expose the second end of the bump. 8. A package stack structure, characterized in that it comprises a first package and a second package stacked on the first package, The first package includes: The first substrate has a first surface and a second surface facing away from the first surface, and includes a first pad and a second pad disposed on the first surface and separated from each other; a first chip mounted on the first surface of the substrate and electrically connected to the first pad; A bump, disposed on the second pad, includes a first end contacting the second pad and a second end opposite to the first end, wherein the bump includes a substantially vertical a plurality of sub-bumps sequentially stacked on the second pad in the direction of the first surface; and a first encapsulation member encapsulating at least a portion of the first chip and at least a portion of the bump, and expose the second end of the bump, The second package includes: The second substrate has a third surface and a fourth surface facing away from the third surface; a second chip mounted on the third surface and electrically connected to the second substrate; a second encapsulation member encapsulating at least a portion of the second chip; and an external connection member, attached to the fourth surface, Wherein, the external connection member is fixed on the bump, so that the second package is electrically connected to the first package. 9. A method of manufacturing a package stack structure, characterized by comprising providing a first package, providing a second package, and stacking the second package on the first package, Wherein, the step of providing the first package includes: providing a first substrate, the substrate has a first surface and a second surface facing away from the first surface and includes a first pad and a second pad disposed on the first surface and separated from each other; installing a first chip on the first surface of the first substrate, and electrically connecting the first chip to the first pad; The bump is provided by sequentially stacking a plurality of sub-bumps on the second pad in a direction substantially perpendicular to the first surface by a wire bonding process using a wire bonding machine so that the bump includes a first end contacting the second pad. and a second end opposite the first end; encapsulating at least a portion of the chip and the bumps with a first encapsulation member; and removing a portion of the first encapsulating member disposed on the second end of the bump to expose the second end of the bump, Wherein, the step of providing the second package includes: providing a second substrate having a third surface and a fourth surface opposite the third surface; mounting a second chip on the third surface of the second substrate, and electrically connecting the second chip to the second substrate; encapsulating at least a portion of the second chip with a second encapsulation member; and attaching external connection terminals to the fourth surface of the second substrate; Wherein, the step of stacking the second package on the first package includes: providing external connection terminals on the bumps; and Reflow is performed on the external connection terminal so that the external connection terminal becomes an external connection member fixed on the bump.