CN107039353B - Array substrate and preparation method thereof - Google Patents

Abstract

The present invention provides an array substrate and a preparation method thereof. The method includes: forming an amorphous silicon layer on a base substrate, wherein the base substrate includes a pixel area and a peripheral driving area; forming an anti-reflection film on the amorphous silicon layer in the peripheral driving area; The polysilicon layer is formed by crystallization treatment, and the grain size of the polysilicon layer in the peripheral driving area is larger than that of the polysilicon layer in the pixel area; the anti-reflection film is removed; the polysilicon layer is patterned to form the first polysilicon corresponding to the pixel area. A silicon active layer and a second polysilicon active layer located in the peripheral driving region; a first insulating layer, a gate, a second polysilicon layer are sequentially formed on the first polysilicon active layer and the second polysilicon active layer insulating layer, source electrode and drain electrode to obtain an array substrate. Based on the arrangement of the anti-reflection film, the invention increases the crystal grain size of the polysilicon layer in the peripheral driving area of the polysilicon thin film transistor, and improves the driving efficiency of the array substrate.

Description

Array substrate and preparation method thereof

technical field

The present invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof.

Background technique

Low temperature poly-silicon (LTPS) TFT liquid crystal displays are different from traditional amorphous silicon TFT liquid crystal displays, and their electron mobility can reach more than 200cm2/V-sec, which can effectively reduce the cost of thin film transistor devices. The area of the display is increased, the aperture ratio of the display is increased, and the overall power consumption of the display can be reduced while improving the brightness of the display. In addition, due to the high electron mobility of the LTPS thin film transistor, part of the driving circuit of the LTPS thin film transistor can be integrated on the glass substrate, thereby saving the space occupied by the driving circuit and greatly improving the reliability of the liquid crystal display panel. , reducing the manufacturing cost of the liquid crystal display panel.

The current process methods for manufacturing low temperature polysilicon thin film transistors mainly include traditional excimer laser annealing (ELA) method without mask and continuous side crystallization method (SLS) using mask to control the laser irradiation area. When the traditional ELA method is used, the grain size of the low-temperature polysilicon obtained is generally less than 0.1um; when the SLS method is used, the crystallization process is induced from the end of the irradiated area to the inside, and finally the crystallization of the center of the irradiated area is carried out. When the temperature is lower than the melting point during the progress of crystallization, if the temperature of the center portion drops, nucleation proceeds, so that large crystal grains cannot be obtained.

It can be seen that the grain size of the polysilicon manufactured by the above two processes is small. When the low temperature polysilicon thin film transistor works, the small grain size of the polysilicon limits the peripheral driving circuit to obtain a small electron mobility, which in turn limits the The peripheral drive circuit has low drive efficiency.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide an array substrate, which can increase the crystal grain size of polysilicon in the peripheral driving area, improve the driving efficiency of the peripheral driving area, and improve the driving efficiency of the array substrate.

In one aspect, a method for preparing an array substrate is provided, the method comprising:

forming an amorphous silicon layer on a base substrate, wherein the base substrate includes a pixel region and a peripheral driving region;

forming an anti-reflection film on the amorphous silicon layer of the peripheral driving region;

crystallizing the amorphous silicon layer to form a polysilicon layer, the grain size of the polysilicon layer in the peripheral driving area is larger than the grain size of the polysilicon layer in the pixel area;

removing the anti-reflection film;

patterning the polysilicon layer to correspondingly form a first polysilicon active layer located in the pixel region and a second polysilicon active layer located in the peripheral driving region;

A first insulating layer, a gate electrode, a second insulating layer, a source electrode and a drain electrode are sequentially formed on the first polysilicon active layer and the second polysilicon active layer to obtain the array substrate.

Further, the forming of the polysilicon layer by crystallizing the amorphous silicon layer includes:

The amorphous silicon layer is crystallized using an excimer laser annealing method or a solid-phase crystallization method.

Further, the thickness of the anti-reflection film is proportional to the wavelength of the laser and inversely proportional to the refractive index of the anti-reflection film.

Further, the thickness of the anti-reflection film is a quarter of the ratio of the wavelength of the laser light to the refractive index of the anti-reflection film.

Further, the refractive index of the anti-reflection film is the geometry of the refractive index of the amorphous silicon layer located under the anti-reflection film and the refractive index of the gas phase medium located above the anti-reflection film when the anti-reflection film is formed. average value.

Further, the material of the anti-reflection film is one of the following:

Aluminum oxide, silicon dioxide, magnesium difluoride or silicon nitride.

Further, forming a first insulating layer, a gate electrode, a second insulating layer, a source electrode and a drain electrode in sequence on the first polysilicon active layer and the second polysilicon active layer , and obtaining the array substrate includes:

forming a first insulating layer, wherein the first insulating layer covers the first polysilicon active layer and the second polysilicon active layer;

forming a first gate electrode in the pixel region and a second gate electrode in the peripheral driving region by patterning on the first insulating layer;

forming a second insulating layer, wherein the second insulating layer covers the first gate and the second gate;

A source via hole and a drain via hole are formed on the first insulating layer and the second insulating layer, and a first via hole in the pixel region is formed in the source via hole and the drain via hole. A source electrode and a first drain electrode and a second source electrode and a second drain electrode in the peripheral drive region.

On the other hand, an array substrate prepared according to the above-mentioned method for preparing an array substrate is also provided, wherein the array substrate includes a pixel polysilicon thin film transistor located in a pixel region and a pixel polysilicon thin film transistor located in a peripheral driving region formed on a base substrate. Driving polysilicon thin film transistors;

The grain size of the first polysilicon active layer in the pixel polysilicon thin film transistor is smaller than the grain size of the second polysilicon active layer in the driving polysilicon thin film transistor.

Further, the pixel polysilicon thin film transistor further includes a first polysilicon active layer, a first insulating layer, a first gate electrode and a second insulating layer stacked in the pixel region on the base substrate, and A first source electrode formed in a source via hole and a first drain electrode formed in a drain via hole, the source via hole and the drain via hole in the pixel area both penetrate the pixel the first insulating layer and the second insulating layer within the region.

Further, the driving polysilicon thin film transistor further includes a second polysilicon active layer, a first insulating layer, a second gate electrode and a second insulating layer stacked in the peripheral driving region on the base substrate, and a second source electrode formed in the source electrode via hole and a second drain electrode formed in the drain electrode via hole, the source electrode via hole and the drain electrode via hole in the peripheral driving region both penetrate through the the first insulating layer and the second insulating layer in the peripheral driving region.

Compared with the prior art, the present invention includes the following advantages:

The present invention provides an array substrate and a preparation method thereof. When preparing the array substrate, an anti-reflection film is formed on the amorphous silicon layer in the peripheral driving area, and when the amorphous silicon layer is crystallized, the energy is The reflection on the surface of the amorphous silicon is greatly weakened. Under the condition of constant transmittance, the energy absorbed by the amorphous silicon layer increases, which can effectively improve the crystallization effect of the amorphous silicon in the peripheral driving area, and obtain a larger Grain size polysilicon layer. Therefore, the present invention is based on forming an anti-reflection film on the amorphous silicon layer in the peripheral driving area of the polysilicon thin film transistor, thereby increasing the grain size of the polysilicon layer in the peripheral driving area, thereby improving the performance of the peripheral driving circuit of the polysilicon thin film transistor. The driving efficiency improves the driving efficiency of the array substrate.

In the present invention, if the refractive index of the anti-reflection film is the geometric mean of the refractive index of the amorphous silicon layer located under the anti-reflection film and the refractive index of the gas phase medium located above the anti-reflection film when the anti-reflection film is formed, then the When the crystalline silicon layer is crystallized, the refraction value of the anti-reflection film to the light is zero, and the anti-reflection film can absorb a large amount of energy, which is beneficial to the crystallization of polysilicon and obtains a polysilicon layer with a larger grain size.

When the invention uses laser to crystallize the amorphous silicon layer, if the thickness of the anti-reflection film is a quarter of the ratio of the wavelength of the laser to the refractive index of the anti-reflection film, the anti-reflection film absorbs the incident laser light the least, The amount of anti-reflection film material used is the least, and the material cost is the lowest.

Description of drawings

FIG. 1 is a flowchart of a method for preparing an array substrate provided by an embodiment of the present invention;

2-8 are schematic structural diagrams of the preparation process of the array substrate in the embodiment shown in FIG. 1;

FIG. 9 is a schematic diagram of light rays of an array substrate provided by an embodiment of the present invention.

Description of reference numbers:

1. Substrate a, pixel area b, peripheral drive area

2. Buffer layer 3. Amorphous silicon layer 4. Anti-reflection film

41. Anti-reflection film in the peripheral driving area 5. Polysilicon layer

51. The polysilicon layer in the pixel region, 52, the polysilicon layer in the peripheral driving region

511, the first polysilicon active layer 522, the second polysilicon active layer

6. The first insulating layer 7. The second insulating layer

8. The first gate 9. The second gate

10. Source vias 11. Drain vias 12. Gas phase dielectric

Detailed ways

In order to make the above objects, features and advantages of the present invention more clearly understood, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

In the description of the present invention, unless otherwise stated, "plurality" means two or more; the terms "upper", "lower", "left", "right", "inner", "outer" The orientation or positional relationship indicated by etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred machine or element must have a specific orientation, with a specific orientation. The orientation configuration and operation are therefore not to be construed as limitations of the present invention.

In the description of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection or electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are intended to illustrate the present invention, but not to limit the scope of the present invention.

When using the existing method to prepare the array substrate, when specifically preparing the thin film transistors in the array substrate, the amorphous silicon layer formed on the base substrate is crystallized to obtain the crystalline silicon layer, and the pixel area in the crystalline silicon layer is The grain size is the same as the grain size in the peripheral driving area, and the grain size is smaller. The driving efficiency of the peripheral driving circuit of the polysilicon thin film transistor is low, and the driving efficiency of the array substrate is low.

In order to increase the grain size in the peripheral driving area of the polysilicon thin film transistor, improve the driving efficiency of the peripheral driving circuit of the polysilicon thin film transistor, and improve the driving efficiency of the array substrate, the embodiment of the present invention provides a preparation method of the array substrate, using In the array substrate manufactured by the method, the polysilicon layer in the peripheral driving region of the polysilicon thin film transistor has a larger crystal grain size.

FIG. 1 is a method flowchart of a method for preparing an array substrate provided by an embodiment of the present invention. The method for preparing an array substrate shown in FIG. 1 includes:

Step 101 , forming an amorphous silicon layer on a base substrate, wherein the base substrate includes a pixel area and a peripheral driving area.

When using the method provided by the embodiment of the present invention to prepare the array substrate, when specifically preparing the polysilicon thin film transistor of the array substrate, the base substrate 1 is selected, and the base substrate 1 may be a glass substrate or a substrate of other suitable materials. Based on the structure and function of the array substrate, the base substrate 1 can be divided into a pixel area a and a peripheral driving area b. After the base substrate 1 is selected, an amorphous silicon layer 3 is formed on the base substrate 1 . Based on the area division of the base substrate 1 , a part of the amorphous silicon layer 3 is formed in the pixel area a, and a part is formed in the peripheral driving area b.

In order to improve the driving performance of the polysilicon thin film transistor, before forming the amorphous silicon layer 3 on the base substrate 1 , the buffer layer 2 may be formed on the base substrate 1 first, and then the amorphous silicon layer may be formed on the buffer layer 2 . The amorphous silicon layer 3 can be formed on the buffer layer 2 by various methods, such as depositing the amorphous silicon layer 3 on the buffer layer 2 by chemical vapor deposition. The structures of the aforementioned base substrate 1 and the buffer layer 2 are shown in FIG. 2 , and the structure of the amorphous silicon layer 3 is shown in FIG. 3 .

Step 102 , forming an anti-reflection film on the amorphous silicon layer in the peripheral driving region.

Anti-reflection film, also known as anti-reflection film, is used to reduce or eliminate the emitted light from optical surfaces such as lenses, cools, flat mirrors, etc., thereby increasing the light transmission of the above components and reducing or eliminating stray light in the system. The simplest antireflection film is a monolayer, which can be a lower refractive index film coated on an optical surface.

In order to increase the grain size of the polysilicon layer 5 in the peripheral driving region b, an anti-reflection film 4 is formed on the amorphous silicon layer 3 in the peripheral driving region b in the embodiment of the present invention. The anti-reflection film 4 can reduce the reflected energy on the surface of the amorphous silicon layer 3 during the crystallization process, and can increase the absorption energy of the amorphous silicon layer 3 under the condition of constant transmittance, thereby improving the performance of the amorphous silicon layer 3. Due to the structural effect, the polysilicon layer 5 with a large grain size is obtained.

In the preparation process, an anti-reflection film 4 can be formed on the surface of the amorphous silicon layer 3 away from the base substrate 1, as shown in FIG. 4, and then the anti-reflection film 4 in the pixel area is removed to obtain a film formed in the peripheral driving area. The anti-reflection film 41 is shown in FIG. 5 .

Step 103 , crystallize the amorphous silicon layer to form a polysilicon layer, and the grain size of the polysilicon layer in the peripheral driving region is larger than the grain size of the polysilicon layer in the pixel region.

After an anti-reflection film 4 is formed on the amorphous silicon layer 3 in the peripheral driving region b, the amorphous silicon layer 3 is crystallized, and the amorphous silicon layer 3 is transformed into a polysilicon layer 5 . Since the anti-reflection film 4 is formed on the amorphous silicon layer 3 of the peripheral driving area b, the amorphous silicon layer 3 of the peripheral driving area b gets more energy absorption during the crystallization process. Layer 5 has a larger grain size. Since the anti-reflection film 4 is not formed on the amorphous silicon layer 3 of the pixel region a, the polysilicon layer 5 of the pixel region a has a smaller grain size after the crystallization process. The structure of the polysilicon layer 5 is shown in FIG. 6 . It can be seen from FIG. 6 that the grain size of the polysilicon layer 5 in the peripheral driving region b is larger than that of the polysilicon layer 5 in the pixel region a.

The amorphous silicon layer 3 may be crystallized using various methods, such as using an excimer laser annealing (ELA) method or a solid phase crystallization (SPC) method to crystallize the amorphous silicon layer 3 . When the amorphous silicon layer 3 is crystallized by the ELA method or the SPC method, the reflection of the laser energy on the surface of the amorphous silicon layer 3 is greatly weakened. When the transmittance remains unchanged, the amorphous silicon layer 3 absorbs The laser energy of the laser increases, so that the crystallization effect of the amorphous silicon layer 3 can be improved, and the polysilicon layer 5 with a larger grain size can be obtained.

FIG. 9 is a schematic diagram of light rays of an array substrate provided by an embodiment of the present invention. As shown in FIG. 9 , during the crystallization process of the amorphous silicon layer 3 of the polysilicon thin film transistor of the array substrate, part of the light is transmitted from the vacuum or air to the anti-reflection film 4 , and is transmitted to the inside of the amorphous silicon layer 3 through the anti-reflection film 4 , part of the light is reflected on the surface of the anti-reflection film 4, and part of the light passes through the anti-reflection film 4 and is reflected on the surface of the amorphous silicon layer 3, and is finally reflected into the vacuum or air.

If the phase of the reflected light reflected from the surface of the amorphous silicon layer 3 to the surface of the anti-reflection film 4 is 180° out of phase with the reflected light reflected from the surface of the anti-reflection film 4, then based on the interference of the light, the reflected light can interact with each other to a certain extent. Cancel, weaken reflected light.

In a normal incident light beam, the proportion of reflected energy reflected from the surface of the anti-reflection film 4 covered with a layer of thickness d ₁ , that is, the reflectivity R is:

Among them, the refractive indices r ₁ , r ₂ and reflection angle θ of different layers can be obtained from the following equations:

Wherein, n ₀ is the refractive index of the air layer or the vacuum layer, n ₁ is the refractive index of the anti-reflection film 4, and n ₂ is the refractive index of the amorphous silicon layer 3;

When the thickness d ₁ of the anti-reflection film 4 satisfies the condition: n ₁ d ₁ =(2x+1)λ/4, where n ₁ is the refractive index of the anti-reflection film 4 , λ is excimer laser annealing (ELA) or solid state The wavelength of the laser used in the phase crystallization (SPC) method, x=0, 1, 2, 3, . When the phase difference of the reflected light on the surface is π, a variety of reflected light will interfere, the reflected light can cancel each other to a certain extent, and the reflectivity of the amorphous silicon layer 3 to the light is the smallest. Based on the principle of saving material, the anti-reflection film 4 has the least absorption of incident laser light and the best anti-reflection effect, preferably, d ₁ =λ/4n ₁ ;

When n ₁ d ₁ =λ/4, the reflectance has a minimum value:

It can be seen from formula (3) that when the refractive index n ₁ of the anti-reflection film 4 is the refractive index n ₂ of the amorphous silicon layer 3 located under the anti-reflection film 4 and the gas phase above the anti-reflection film 4 when the anti-reflection film 4 is formed When the geometric mean of the refractive index n ₀ of the medium, the reflectivity of the light is zero, the anti-reflection effect of the anti-reflection film 4 is the best, and the refraction value of the anti-reflection film 4 to the light is zero. The gas phase medium is vacuum or air.

Since the refractive index of the amorphous silicon layer 3 is generally about 3 to 4, and the refractive index of vacuum or air is 1, the anti-reflection film 4 needs to have high transmittance and meet the requirements of the refractive index. The anti-reflection film 4 can be made of various materials, such as aluminum oxide with a refractive index of 1.8-1.9, silicon dioxide with a refractive index of 1.4-1.5, magnesium difluoride with a refractive index of 1.3-1.4 or a refractive index of 1.9 of silicon nitride. In the embodiment of the present invention, preferably, aluminum oxide Al ₂ O ₃ is selected as the material of the anti-reflection film ₄ , and Al ₂ O ₃ is a new type _III -VI group wide bandgap semiconductor material. It has high transparency and low absorption in the ultraviolet to mid-far infrared spectral range, and has good physical and chemical properties. It is widely used as a refractive index optical material. By controlling the quality of the film, the light absorption rate of the Al ₂ O ₃ film can be extremely small. , the obtained Al ₂ O ₃ film has a very high transmittance.

Step 104, removing the anti-reflection film.

After the crystallization of the amorphous silicon layer 3 is completed, the anti-reflection film 4 on the polysilicon layer 5 in the peripheral driving region b is removed.

Step 105 , patterning the polysilicon layer to correspondingly form a first polysilicon active layer located in the pixel region and a second polysilicon active layer located in the peripheral driving region.

After removing the anti-reflection film 4 on the polysilicon layer 5 in the peripheral driving area b, the polysilicon layer 51 in the pixel area is patterned to obtain a first polysilicon active layer 511, and the polysilicon layer 52 in the peripheral driving area is patterned , the second polysilicon active layer 522 is obtained. The structures of the first polysilicon active layer 511 and the second polysilicon active layer 522 are shown in FIG. 7 .

Step 106, forming a first insulating layer, a gate electrode, a second insulating layer, a source electrode and a drain electrode in sequence on the first polysilicon active layer and the second polysilicon active layer to obtain the array substrate.

In the embodiment of the present invention, after the first polysilicon active layer 511 and the second polysilicon active layer 522 are formed, the first polysilicon active layer 511 and the second polysilicon active layer 522 are sequentially formed on the first polysilicon active layer 511 and the second polysilicon active layer 522 The first insulating layer 6 , the gate electrode, the second insulating layer 7 , the source electrode and the drain electrode are formed to obtain a polysilicon thin film transistor, and an array substrate is further prepared by using the polysilicon thin film transistor provided in the embodiment of the present invention. Except for the structure of the polysilicon thin film transistor prepared in the embodiment of the present invention, other structures of the array substrate are in the prior art, and are not described herein again in the present invention. The structure of the polysilicon thin film transistor of the array substrate prepared in the embodiment of the present invention is shown in FIG. 8 .

The process of sequentially forming a first insulating layer, a gate, a second insulating layer, a source electrode and a drain electrode on the first polysilicon active layer and the second polysilicon active layer in this step may specifically include the following steps: The following steps:

First, a first insulating layer 6 is formed. The first insulating layer 6 covers the first polysilicon active layer 511 and the second polysilicon active layer 522. The active layer 522 of two polysilicon layers is encapsulated in the first insulating layer 6, and the first insulating layer 6 can be formed by various methods, such as chemical vapor deposition.

Next, a gate electrode is formed by patterning on the first insulating layer 6 , specifically, a first gate electrode 8 in the pixel region a and a second gate electrode 9 in the peripheral driving region b are formed by patterning on the first insulating layer 6 .

In practice, magnetron sputtering, photolithography, etching and other processes can be used to form the first gate 8 in the pixel region a and the second gate 9 in the peripheral driving region b on the first insulating layer 6 .

Again, the second insulating layer 7 is formed, and the second insulating layer 7 covers the first gate electrode 8 and the second gate electrode 9 . The second insulating layer 7 can be formed in various ways, such as depositing the second insulating layer 7 on the first gate 8 , the second gate 9 and the first insulating layer 6 by chemical vapor deposition.

Finally, via holes are formed on the first insulating layer 6 and the second insulating layer 7, specifically, source via holes 10 and drain via holes 11 are formed in the pixel region a and the peripheral driving region b, respectively. 10 and the drain via hole 11, a first source electrode and a first drain electrode in the pixel region a and a second source electrode and a second drain electrode in the peripheral driving region b are formed.

A via hole is formed on the first insulating layer 6 and the second insulating layer 7 , the via hole penetrates the first insulating layer 6 and the second insulating layer 7 , and the bottom hole of the via hole is located on the first polysilicon active layer 511 surface or the upper surface of the second polysilicon active layer 522 .

Then, a first source is formed in the source via 10 of the pixel region a, a first drain is formed in the drain via 11 of the pixel region a, and a second drain is formed in the source via 10 of the peripheral driving region b The source electrode, the second drain electrode is formed in the drain via hole 11 of the peripheral driving region b. When fabricating the polysilicon thin film transistor of the array substrate, forming the source electrode and the drain electrode in the source electrode via hole 10 and the drain electrode via hole 11 is the prior art in the art, which is not repeated here in the present invention.

The embodiment of the present invention also provides an array substrate, which is prepared according to the method for preparing the array substrate provided by the embodiment of the present invention. The structure of the array substrate is shown in FIG. 8 . The array substrate includes a pixel polysilicon thin film transistor located in the pixel region a and a driving polysilicon thin film transistor located in the peripheral driving region b formed on the base substrate 1;

The grain size of the first polysilicon active layer 511 in the pixel polysilicon thin film transistor is smaller than the grain size of the second polysilicon active layer 522 in the driving polysilicon thin film transistor.

Since the grain size of the second polysilicon active layer 522 in the driving polysilicon thin film transistor is large, the driving polysilicon thin film transistor has a high driving efficiency, and thus the array substrate has a high driving efficiency.

The pixel polysilicon thin film transistor may further include a first polysilicon active layer 511 , a first insulating layer 6 , a first gate 81 and a second insulating layer in the pixel region a on the base substrate 1 . Layer 7, as well as the first source formed in the source via 10 and the first drain formed in the drain via 11, the source via 10 and the drain via 11 in the pixel region a all pass through The first insulating layer 6 and the second insulating layer 7 in the pixel area a.

The driving polysilicon thin film transistor may further include a second polysilicon active layer 522, a first insulating layer 6, a second gate 9 in the peripheral driving region, and a second polysilicon active layer 522 in the peripheral driving region b on the base substrate 1. Two insulating layers 7, and a second source electrode formed in the source electrode via hole 10 and a second drain electrode formed in the drain electrode via hole 11, the source electrode via hole 10 and the drain electrode via hole in the peripheral driving region b 11 all penetrate through the first insulating layer 6 and the second insulating layer 7 in the peripheral driving region b.

The present invention provides an array substrate and a preparation method thereof. When preparing the array substrate, an anti-reflection film is formed on the amorphous silicon layer in the peripheral driving area, and when the amorphous silicon layer is crystallized, the energy is The reflection on the surface of the amorphous silicon is greatly weakened. Under the condition of constant transmittance, the energy absorbed by the amorphous silicon layer increases, which can effectively improve the crystallization effect of the amorphous silicon in the peripheral driving area, and obtain a larger Grain size polysilicon layer. Therefore, the present invention is based on forming an anti-reflection film on the amorphous silicon layer in the peripheral driving area of the polysilicon thin film transistor, thereby increasing the grain size of the polysilicon layer in the peripheral driving area, thereby improving the performance of the peripheral driving circuit of the polysilicon thin film transistor. The driving efficiency improves the driving efficiency of the array substrate.

In the present invention, if the refractive index of the anti-reflection film is the geometric mean of the refractive index of the amorphous silicon layer located under the anti-reflection film and the refractive index of the gas phase medium located above the anti-reflection film when the anti-reflection film is formed, then the When the crystalline silicon layer is crystallized, the refraction value of the anti-reflection film to the light is zero, and the anti-reflection film can absorb a large amount of energy, which is beneficial to the crystallization of polysilicon and obtains a polysilicon layer with a larger grain size.

When the invention uses laser to crystallize the amorphous silicon layer, if the thickness of the anti-reflection film is a quarter of the ratio of the wavelength of the laser to the refractive index of the anti-reflection film, the anti-reflection film absorbs the incident laser light the least, The amount of anti-reflection film material used is the least, and the material cost is the lowest.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other.

The array substrate provided by the present invention and the preparation method thereof have been introduced in detail above. Specific examples are used to illustrate the principles and implementations of the present invention. Its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. limit.

Claims (8)

1. A preparation method of an array substrate is characterized by comprising the following steps:

forming an amorphous silicon layer on a substrate, wherein the substrate comprises a pixel region and a peripheral driving region;

forming an anti-reflection film on the amorphous silicon layer of the peripheral driving region;

crystallizing the amorphous silicon layer to form a polycrystalline silicon layer, wherein the grain size of the polycrystalline silicon layer in the peripheral driving area is larger than that of the polycrystalline silicon layer in the pixel area;

removing the antireflection film;

patterning the polysilicon layer to correspondingly form a first polysilicon active layer positioned in the pixel region and a second polysilicon active layer positioned in the peripheral driving region;

sequentially forming a first insulating layer, a grid electrode, a second insulating layer, a source electrode and a drain electrode on the first polycrystalline silicon active layer and the second polycrystalline silicon active layer to obtain the array substrate;

the phase difference between the reflected light reflected by the surface of the amorphous silicon layer to the surface of the antireflection film and the reflected light reflected by the surface of the antireflection film is 180 degrees;

wherein the crystallizing the amorphous silicon layer to form a polycrystalline silicon layer comprises:

crystallizing the amorphous silicon layer by using an excimer laser annealing method or a solid-phase crystallization method;

the thickness of the antireflection film is one fourth of the ratio of the wavelength of the laser to the refractive index of the antireflection film;

wherein the refractive index of the antireflection film is a geometric average of the refractive index of the amorphous silicon layer and the refractive index of a gas-phase medium located above the antireflection film;

wherein the step of forming an anti-reflective film on the amorphous silicon layer of the peripheral driving region includes: and forming an antireflection film on the surface of the amorphous silicon layer, which is far away from the substrate base plate, and removing the antireflection film in the pixel area to obtain the antireflection film formed in the peripheral driving area.

2. The method of claim 1, wherein a thickness of the antireflection film is proportional to a wavelength of the laser light and inversely proportional to a refractive index of the antireflection film.

3. The method of claim 1, wherein the refractive index of the anti-reflective film is a geometric average of a refractive index of an amorphous silicon layer located below the anti-reflective film and a refractive index of a gas phase medium located above the anti-reflective film when the anti-reflective film is formed.

4. The method of claim 1, wherein the antireflection film is made of one of:

aluminum oxide, silicon dioxide, magnesium difluoride or silicon nitride.

5. The method of claim 1, wherein the sequentially forming a first insulating layer, a gate electrode, a second insulating layer, a source electrode and a drain electrode on the first polysilicon layer active layer and the second polysilicon layer active layer to obtain the array substrate comprises:

forming a first insulating layer, wherein the first insulating layer covers the first and second polysilicon layer active layers;

patterning a first grid electrode positioned in the pixel area and a second grid electrode positioned in the peripheral driving area on the first insulating layer;

forming a second insulating layer, wherein the second insulating layer covers the first gate and the second gate;

and manufacturing a source through hole and a drain through hole on the first insulating layer and the second insulating layer, and forming a first source and a first drain in the pixel region and a second source and a second drain in the peripheral driving region in the source through hole and the drain through hole.

6. An array substrate prepared by the preparation method of the array substrate according to any one of claims 1 to 5, wherein the array substrate comprises a pixel polysilicon thin film transistor formed on a substrate in a pixel region and a driving polysilicon thin film transistor in a peripheral driving region;

the grain size of the first polycrystalline silicon active layer in the pixel polycrystalline silicon thin film transistor is smaller than that of the second polycrystalline silicon active layer in the driving polycrystalline silicon thin film transistor.

7. The array substrate of claim 6, wherein the pixel polysilicon thin film transistor further comprises a first polysilicon active layer, a first insulating layer, a first gate electrode and a second insulating layer stacked in a pixel region on the substrate, and a first source electrode formed in a source via and a first drain electrode formed in a drain via, the source via and the drain via in the pixel region each passing through the first insulating layer and the second insulating layer in the pixel region.

8. The array substrate of claim 6, wherein the driving polysilicon thin film transistor further comprises a second polysilicon active layer, a first insulating layer, a second gate electrode and a second insulating layer which are stacked in a peripheral driving region on the substrate, and a second source electrode formed in a source via and a second drain electrode formed in a drain via, wherein the source via and the drain via in the peripheral driving region are both through the first insulating layer and the second insulating layer in the peripheral driving region.

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