CN106960881B - Thin film transistor and method of making the same - Google Patents

Abstract

The invention provides a thin film transistor and a preparation method thereof. The thin film transistor includes a gate electrode disposed on a substrate, a gate insulating layer covering the gate electrode, and a first electrode, an active layer and a second electrode sequentially stacked on the surface of the gate electrode away from the substrate. The preparation method includes: forming a gate electrode and a gate insulating layer on a substrate; forming a first electrode, an active layer and a second electrode sequentially stacked on the surface of the gate electrode away from the substrate on the gate insulating layer. In the present invention, the first electrode, the active layer and the second electrode are sequentially stacked on the surface of the gate electrode away from the substrate, and the orthographic projection of the first electrode, the active layer and the second electrode on the substrate is the same as that of the gate electrode on the substrate. The orthographic projections on the TFT overlap at least partially, which effectively reduces the size of the thin film transistor, which not only improves the aperture ratio and realizes high-resolution display, but also ensures the alignment accuracy and line width control, and improves the yield.

Description

Thin film transistor and method of making the same

technical field

The invention relates to the technical field of display, in particular to a thin film transistor and a preparation method thereof.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD), as a flat panel display device, is more and more used because of its small size, low power consumption, no radiation and relatively low production cost. in the field of high-performance displays. The main structure of the TFT-LCD includes a cell-aligned array substrate and a color filter substrate. The array substrate includes a plurality of pixel units arranged in a matrix. The pixel units are defined by a plurality of gate lines and a plurality of data lines that intersect vertically. Thin film transistors are arranged at the intersections of the .

FIG. 1A is a schematic structural diagram of a conventional array substrate, and FIG. 1B is a cross-sectional view taken along the line A-A in FIG. 1A . As shown in FIG. 1A and FIG. 1B , the array substrate includes gate lines 20 , data lines 30 , pixel electrodes 17 and thin film transistors, wherein the thin film transistors and pixel electrodes 17 are located in the pixel unit defined by the vertical intersection of the gate lines 20 and the data lines 30 Inside. The thin film transistor includes: a gate electrode 11 arranged on a substrate 10, a gate insulating layer 12 covering the gate electrode 11, an active layer 13 arranged on the gate insulating layer 12, a source electrode 14 arranged on the active layer 13 and a drain Pole 15. The gate electrode 11 is connected to the gate line 20, the overlapping portion of the data line 30 and the gate electrode 11 is used as the source electrode 14 of the thin film transistor, the drain electrode 15 and the source electrode 14 are arranged opposite to each other, and a horizontal channel is formed in the area therebetween, and the drain electrode 15 passes through The via hole on the passivation layer 16 is connected to the pixel electrode 17 . When the gate electrode is loaded with a gate scan signal, the active layer above the gate electrode will change from a semiconductor state to a conductor state, and the display signal from the data line is loaded onto the pixel electrode through the source electrode, the active layer and the drain electrode.

In recent years, high-resolution display panels have gradually become an industry development trend. Generally, the resolution (Pixels per inch, PPI) of the display panel is related to the pixel aperture ratio of the array substrate, and the pixel aperture ratio of the array substrate is related to the size of the thin film transistor of each pixel unit. The smaller the aperture ratio, the lower the resolution of the display panel, so reducing the size of the thin film transistor is one of the important ways to improve the resolution. However, for the thin film transistor structure in which the source and drain electrodes are arranged in parallel as shown in Figure 1A and Figure 1B, due to the influence of the width of the data line and the alignment accuracy and line width control in the preparation process, reducing the size of the thin film transistor in this structure is greatly restricted. Therefore, it is difficult for the thin film transistor of the existing structure to increase the resolution by reducing the size.

SUMMARY OF THE INVENTION

The technical problem to be solved by the embodiments of the present invention is to provide a thin film transistor and a preparation method thereof, so as to overcome the problem that the existing thin film transistor is difficult to improve the resolution by reducing the size.

In order to solve the above technical problems, an embodiment of the present invention provides a thin film transistor, which includes a gate electrode disposed on a substrate, a gate insulating layer covering the gate electrode, and a thin film transistor sequentially stacked on a surface of the gate electrode away from the substrate. the first electrode, the active layer and the second electrode.

Optionally, the first electrode, the active layer and the second electrode that are sequentially stacked on the surface of the gate electrode away from the substrate include: the first electrode is arranged on the gate insulating layer and is on the substrate. The orthographic projection at least partially coincides with the orthographic projection of the gate electrode on the substrate, the active layer is disposed on the first electrode and its orthographic projection on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate , the second electrode is arranged on the active layer and its orthographic projection on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate, and the first electrode, the active layer and the second electrode are stacked in sequence A vertical channel structure is formed.

Optionally, the orthographic projection of the first electrode, the active layer or the second electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate, including: the first electrode, the active layer or the second electrode The orthographic projection range on the substrate is exactly the same as the orthographic projection range of the gate electrode on the substrate, or the orthographic projection range of the first electrode, the active layer or the second electrode on the substrate is located in the orthographic projection range of the gate electrode on the substrate within.

Optionally, the material of the active layer includes polysilicon or metal oxide, and the thickness is 2000-8000 angstroms.

Optionally, the width of the orthographic projection of the gate electrode on the substrate is 1.2-1.3 times the width of the orthographic projection of the first electrode or the second electrode on the substrate.

In order to solve the above technical problems, an embodiment of the present invention also provides a method for manufacturing a thin film transistor, including:

forming a gate electrode and a gate insulating layer on the substrate;

On the gate insulating layer, a first electrode, an active layer and a second electrode which are sequentially stacked on the surface of the gate electrode away from the substrate are formed.

Optionally, forming the first electrode, the active layer and the second electrode sequentially stacked on the surface of the gate electrode away from the substrate on the gate insulating layer includes:

A first electrode is formed on the gate insulating layer by a patterning process, the orthographic projection of the first electrode on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate; an active electrode is formed on the first electrode by a patterning process layer, the orthographic projection of the active layer on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate; a second electrode is formed on the active layer through a patterning process, and the second electrode is on the substrate The orthographic projection at least partially coincides with the orthographic projection of the gate electrode on the substrate.

Optionally, forming the first electrode, the active layer and the second electrode sequentially stacked on the surface of the gate electrode away from the substrate on the gate insulating layer includes:

A stacked first electrode and an active layer are formed on the gate insulating layer through a patterning process of a half-tone mask or a gray-tone mask, and the orthographic projection of the first electrode and the active layer on the substrate is the same as that of the gate electrode. The orthographic projection on the substrate at least partially overlaps; the second electrode is formed on the active layer through a patterning process, and the orthographic projection of the second electrode on the substrate at least partially overlaps the orthographic projection of the gate electrode on the substrate.

Optionally, forming the first electrode, the active layer and the second electrode sequentially stacked on the surface of the gate electrode away from the substrate on the gate insulating layer includes:

A first electrode is formed on the gate insulating layer through a patterning process, and the orthographic projection of the first electrode on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate; The patterning process forms a stacked active layer and a second electrode on the first electrode, and the orthographic projection of the active layer and the second electrode on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate.

Optionally, the orthographic projection of the first electrode, the active layer or the second electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate, including: the first electrode, the active layer or the second electrode The orthographic projection range on the substrate is exactly the same as the orthographic projection range of the gate electrode on the substrate, or the orthographic projection range of the first electrode, the active layer or the second electrode on the substrate is located in the orthographic projection range of the gate electrode on the substrate within.

Optionally, the width of the orthographic projection of the gate electrode on the substrate is 1.2-1.3 times the width of the orthographic projection of the first electrode or the second electrode on the substrate.

An embodiment of the present invention further provides an array substrate, comprising a gate line, a data line, a pixel electrode and the above-mentioned thin film transistor, the gate line is connected to a gate electrode of the thin film transistor, and the pixel electrode is connected to the thin film transistor The orthographic projection of the data line on the substrate and the orthographic projection of the gate electrode on the substrate have an overlapping area, and the portion of the data line corresponding to the overlapping area serves as the first electrode of the thin film transistor.

Embodiments of the present invention further provide a display panel, including the above-mentioned array substrate.

In the thin film transistor and the preparation method thereof provided by the embodiments of the present invention, the first electrode, the active layer and the second electrode are sequentially stacked on the surface of the gate electrode away from the substrate, and the first electrode, the active layer and the second electrode are stacked in sequence. The orthographic projection of the electrode on the substrate and the orthographic projection of the gate electrode on the substrate at least partially overlap, effectively reducing the size of the thin film transistor, not only improving the aperture ratio, realizing high-resolution display, but also ensuring alignment accuracy and line width. Control and improve the yield.

Of course, it is not necessary for any product or method of the present invention to achieve all of the advantages described above at the same time. Other features and advantages of the present invention will be set forth in the description examples which follow, and, in part, will be apparent from the description examples, or may be learned by practice of the invention. The objectives and other advantages of the embodiments of the invention may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. They are used to explain the technical solutions of the present invention together with the embodiments of the present application, and do not limit the technical solutions of the present invention. The shapes and sizes of the components in the drawings do not reflect the actual scale, and are only intended to illustrate the content of the present invention.

FIG. 1A is a schematic structural diagram of a conventional array substrate, and FIG. 1B is a cross-sectional view taken along the line A-A in FIG. 1A ;

2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;

FIG. 3A is a schematic diagram of a gate electrode and a gate line pattern formed in the first embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the line A-A in FIG. 3A;

FIG. 4A is a schematic diagram of the first embodiment of the present invention after the source electrode and data line patterns are formed, and FIG. 4B is a cross-sectional view taken along the line A-A in FIG. 4A;

FIG. 5A is a schematic diagram after forming an active layer pattern according to the first embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line A-A in FIG. 5A;

FIG. 6A is a schematic diagram after forming a drain electrode pattern according to the first embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along the line A-A in FIG. 6A;

FIG. 7 is a schematic diagram of the second embodiment of the present invention after the pattern of the source electrode, the data line and the active layer is formed;

FIG. 8 is a schematic diagram after forming a drain electrode pattern according to the second embodiment of the present invention;

FIG. 9 is a schematic diagram of the third embodiment of the present invention after forming the pattern of the active layer and the drain electrode;

FIG. 10A is a schematic structural diagram of an array substrate of the present invention, and FIG. 10B is a cross-sectional view taken along the line A-A in FIG. 10A .

Explanation of reference numbers:

10—base; 11—gate electrode; 12—gate insulating layer; 13—active layer; 14—the first (source) electrode; 15—the second (drain) electrode; 16—passivation layer; 17—Pixel electrode.

Detailed ways

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are intended to illustrate the present invention, but not to limit the scope of the present invention. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

At present, the existing thin film transistors usually adopt a horizontal channel structure in which the source and drain electrodes are arranged in parallel. Due to the influence of the width of the data line and the alignment accuracy and line width control in the preparation process, it is difficult for the size of the thin film transistor using this structure to be substantial. Sexual reduction. In order to overcome the problem that the existing thin film transistor is difficult to improve resolution by reducing the size of the thin film transistor, embodiments of the present invention provide a thin film transistor, an array substrate and a display panel.

FIG. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. As shown in FIG. 2 , the thin film transistor includes a gate electrode and a gate insulating layer, and a first electrode, an active layer and a second electrode sequentially stacked on the surface of the gate electrode away from the substrate. Specifically, the thin film transistor includes:

The gate electrode 11 is arranged on the substrate 10;

a gate insulating layer 12, covering the gate electrode 11;

The first electrode 14 is disposed on the gate insulating layer 12, and its orthographic projection on the substrate at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate;

The active layer 13 is disposed on the first electrode 14, and its orthographic projection on the substrate at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate;

The second electrode 15 is disposed on the active layer 13, and its orthographic projection on the substrate at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate.

Wherein, the first electrode 14, the active layer 13 and the second electrode 15 stacked in sequence form a vertical channel structure. The first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode. The thickness of the active layer is 2000-8000 angstroms, and the material of the active layer can be either polysilicon to form a low temperature polysilicon (LTPS) thin film transistor, or metal oxide to form an oxide thin film transistor. The width of the orthographic projection of the first electrode and the second electrode on the substrate is 3 to 5 microns, the width of the orthographic projection of the gate electrode on the substrate is 4 to 6 microns, and the width of the gate electrode is the width of the first electrode or the second electrode. 1.0-2.0 times, preferably, the width of the gate electrode is 1.2-1.3 times the width of the first electrode or the second electrode.

This embodiment provides a thin film transistor with a vertical channel structure. Since the first electrode, the active layer and the second electrode are sequentially stacked on the surface of the gate electrode away from the substrate, the first electrode, the active layer and the The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate, which effectively reduces the size of the thin film transistor. Line width control improves yield.

The technical solutions of the embodiments of the present invention are further described below through the preparation process.

first embodiment

3A to 6B are schematic diagrams of the first embodiment of preparing a thin film transistor according to the present invention. Among them, the "patterning process" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping photoresist, which is an existing mature preparation process. The deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating can use a known coating process, and the etching can use a known method, which is not specifically limited here.

In the first patterning process, gate electrodes and gate line patterns are formed on the substrate through a patterning process. Forming the grid electrode and grid line pattern includes: depositing a first metal film on the substrate 10, coating a layer of photoresist on the first metal film, exposing and developing the photoresist by using a single-tone mask, The gate electrode and gate line pattern position form an unexposed area, and the photoresist is retained, and a fully exposed area is formed at other positions. The photoresist is removed, and the first metal film in the fully exposed area is etched and the remaining photoresist is peeled off glue to form the gate electrode 11 and the gate line 20 pattern. Subsequently, a gate insulating layer 12 is deposited, and the gate insulating layer 12 covers the gate electrode 11 and the gate line 20 pattern, as shown in FIG. 3A and FIG. 3B . The substrate can be a glass substrate or a quartz substrate, and the first metal film can be made of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W and other metals. One or more, the gate insulating layer can be made of silicon nitride SiNx, silicon oxide SiOx or a composite film of SiNx/SiOx.

In the second patterning process, on the substrate on which the gate electrode pattern and the gate insulating layer are formed, source electrode and data line patterns are formed through a patterning process. Forming the source electrode and data line patterns includes: depositing a second metal thin film on the gate insulating layer 12, coating a layer of photoresist on the second metal thin film, and exposing and developing the photoresist using a single-tone mask , form an unexposed area at the source electrode and the data line pattern position, retain the photoresist, form a fully exposed area in other positions, remove the photoresist, etch the second metal film in the fully exposed area and peel off the remaining Photoresist to form the pattern of the source electrode 14 and the data line 30, the part of the overlapping area of the data line 30 and the gate electrode 11 is used as the source electrode 14, that is, the source electrode 14 is located on the surface of the gate electrode 11 away from the substrate, and the source electrode 14 is on the substrate. The orthographic projection on the substrate at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate, as shown in FIG. 4A and FIG. 4B . Wherein, the second metal thin film may be one or more of metals such as platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W and the like.

In the third patterning process, an active layer pattern is formed on the substrate on which the active electrode pattern is formed through a patterning process. Forming the active layer pattern includes: depositing an active layer film on the substrate formed with the aforementioned pattern, coating a layer of photoresist on the active layer film, and exposing and developing the photoresist by using a single-tone mask , an unexposed area is formed at the pattern position of the active layer, the photoresist is retained, a fully exposed area is formed at other positions, the photoresist is removed, the active layer film in the fully exposed area is etched and the remaining photoresist is peeled off glue to form the pattern of the active layer 13, the active layer 13 is located on the surface of the gate electrode 11 away from the substrate, the orthographic projection of the active layer 13 on the substrate and the orthographic projection of the gate electrode 11 on the substrate at least partially overlap, as shown in Figure 5A , as shown in Figure 5B. Among them, the thickness of the active layer is 2000-8000 angstroms, and the material can be either amorphous silicon, polysilicon or microcrystalline silicon material to form LTPS thin film transistors, or metal oxide materials to form Oxide thin film transistors, and the metal oxide material can be Indium Gallium Zinc Oxide (IGZO) or Indium Tin Zinc Oxide (ITZO).

In the fourth patterning process, a drain electrode is formed by a patterning process on the substrate on which the active layer pattern is formed. Forming the drain electrode pattern includes: depositing a third metal film on the substrate formed with the aforementioned pattern, coating a layer of photoresist on the third metal film, and exposing and developing the photoresist by using a single-tone mask, An unexposed area is formed at the drain electrode pattern position, the photoresist is retained, a fully exposed area is formed at other positions, the photoresist is removed, the third metal film in the fully exposed area is etched, and the remaining photoresist is peeled off, A pattern of the drain electrode 15 is formed, the drain electrode 15 is located on the surface of the gate electrode 11 away from the substrate, the orthographic projection of the drain electrode 15 on the substrate and the orthographic projection of the gate electrode 11 on the substrate at least partially overlap, as shown in FIG. 6A and FIG. 6B . Wherein, the third metal thin film may be one or more of metals such as platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W and the like.

It can be seen from the process of preparing the thin film transistor shown in FIGS. 3A to 6B that in this embodiment, a thin film transistor with a vertical channel structure is formed through four patterning processes of an ordinary mask. In the thin film transistor with the existing horizontal channel structure, since the source electrode and the drain electrode are arranged in parallel, and the source electrode, the drain electrode and the channel are all arranged on the gate electrode, it is necessary to design the width of the gate electrode to be greater than the sum of the three widths. The gate electrode width is made equivalent to the width of three data lines. In this embodiment, the source electrode, the active layer and the drain electrode are sequentially stacked on the surface of the gate electrode away from the substrate, and the orthographic projection of the source electrode, the active layer and the drain electrode on the substrate and the orthographic projection of the gate electrode on the substrate At least partially overlap, so that the width of the gate electrode can be designed to be equal to or slightly larger than the width of the source electrode (ie, the data line) or the drain electrode. Compared with the thin film transistor with the existing horizontal channel structure, the size of the thin film transistor in this embodiment can be reduced by 50% to 60%, which not only effectively reduces the size of the thin film transistor, but also effectively avoids the alignment accuracy and other factors during preparation. The display is poor, thereby increasing the aperture ratio and improving the yield.

In this embodiment, "width" refers to the feature size in the width direction of the data lines of the array substrate, or, in other words, refers to the feature size in the direction perpendicular to the length of the data lines. Therefore, the width of the gate electrode or the width of the orthographic projection of the gate electrode on the substrate refers to the characteristic dimension of the cross section of the gate electrode in the vertical direction of the length of the data line (direction A-A as shown in FIGS. 3A-6B ). The width of the source electrode and the drain electrode or the width of the orthographic projection of the source electrode and the drain electrode on the substrate refers to the cross-section of the source electrode and the cross-section of the drain electrode in the vertical direction of the length of the data line (A-A direction as shown in FIGS. 3A-6B ). feature size. In practical implementation, the overlapping portion of the data line and the gate electrode is usually used as the source electrode, so the width of the source electrode is equal to the width of the data line, or the width of the orthographic projection of the source electrode on the substrate is equal to the width of the data line. In addition, in this embodiment, "at least partially overlapping" means that the orthographic projection range of the source electrode, the drain electrode or the active layer on the substrate is exactly the same as the orthographic projection range of the gate electrode on the substrate, that is, the source electrode, drain electrode or The width of the orthographic projection of the active layer on the substrate is equal to the width of the orthographic projection of the gate electrode on the substrate, or the orthographic projection range of the source electrode, the drain electrode or the active layer on the substrate is located in the orthographic projection range of the gate electrode on the substrate In other words, the width of the orthographic projection of the source electrode, the drain electrode or the active layer on the substrate is smaller than the width of the orthographic projection of the gate electrode on the substrate, or the orthographic projection range of the gate electrode on the substrate is located between the source electrode and the drain electrode. Or within the range of the orthographic projection of the active layer on the substrate, that is, the width of the orthographic projection of the source electrode, the drain electrode or the active layer on the substrate is greater than the width of the orthographic projection of the gate electrode on the substrate. In actual implementation, the positional relationship between the source electrode, the active layer and the drain electrode can also be set, so that the orthographic projection of one of them on the substrate is exactly the same as the orthographic projection of the other one or two on the substrate, or, wherein One orthographic projection on the substrate lies within the other or two orthographic projections on the substrate.

Second Embodiment

7 to 8 are schematic diagrams of a second embodiment of preparing a thin film transistor according to the present invention. This embodiment is based on an extension of the first embodiment. Different from the first embodiment, this embodiment adopts three patterning processes to form a thin film transistor with a vertical channel structure.

In the first patterning process, gate electrodes and gate line patterns are formed on the substrate through a patterning process, as shown in FIG. 3A and FIG. 3B . The first patterning process in this embodiment is the same as the first patterning process in the first embodiment, which will not be repeated here.

In the second patterning process, on the substrate on which the gate electrode pattern and the gate insulating layer are formed, source electrodes, data lines and active layer patterns are formed through a patterning process. Forming the source electrode, the data line and the active layer pattern includes: depositing a second metal film and an active layer film in sequence on the gate insulating layer 12, coating a layer of photoresist on the active layer film, and using a halftone mask The photoresist is exposed and developed in a stepwise manner with a plate or a gray-tone reticle, an unexposed area is formed at the pattern position of the active layer, and the photoresist with a first thickness is formed, and a partially exposed area is formed at the position of the data line pattern, with a second thickness. Thickness of photoresist, complete exposure areas are formed in the remaining positions, no photoresist, and the first thickness is greater than the second thickness. The active layer film and the second metal film in the fully exposed area are etched away by the first etching process, and the photoresist is ashed to remove the second thickness of the photoresist as a whole, exposing the partially exposed area. Active layer thin film, the active layer thin film in the partially exposed area is etched away by the second etching process, and the remaining photoresist is peeled off to form the source electrode 14, the data line 30 (not shown) and the active layer 13 Pattern, the source electrode 14 is located on the gate insulating layer 12, the active layer 13 is located on the source electrode 14, the source electrode 14 and the active layer 13 have the same pattern, and the orthographic projection of the source electrode 14 and the active layer 13 on the substrate is the same as The orthographic projections of the gate electrode 11 on the substrate at least partially overlap, as shown in FIG. 7 .

In the third patterning process, on the substrate formed with the above pattern, a drain electrode is formed through a patterning process, as shown in FIG. 8 . The third patterning process in this embodiment is the same as the fourth patterning process in the first embodiment, and will not be repeated here.

In actual implementation, the second patterning process can also use a common mask patterning process to form source electrodes, data lines and active layer patterns, specifically: depositing a second metal film and an active layer film on the gate insulating layer in sequence, A layer of photoresist is coated on the active layer film, and the photoresist is exposed and developed using a common mask, and an unexposed area is formed at the source electrode and data line pattern positions, and the photoresist is retained. A fully exposed area is formed without photoresist. The active layer thin film and the second metal thin film in the fully exposed area are etched away through an etching process, and the remaining photoresist is peeled off to form source electrodes, data lines and active layer patterns. The active layer thin film remains on the data line.

It can be seen from the process of preparing thin film transistors shown in FIGS. 3A , 3B, 7 and 8 that in this embodiment, a thin film transistor with a vertical channel structure is formed through three patterning processes, and the three patterning processes can be two ordinary Mask and 1-pass halftone mask or gray-tone mask, also can be 3-pass normal mask. In this embodiment, parameters such as the material and thickness of each film layer are the same as those in the first embodiment. Compared with the thin film transistor with the existing horizontal channel structure, the size of the thin film transistor in this embodiment can be reduced by 50%-60%.

Third Embodiment

9 to 10 are schematic diagrams of the third embodiment of preparing a thin film transistor according to the present invention. This embodiment is based on an extension of the first embodiment. Different from the first embodiment, this embodiment adopts three patterning processes to form a thin film transistor with a vertical channel structure.

In the first patterning process, gate electrodes and gate line patterns are formed on the substrate through a patterning process, as shown in FIG. 3A and FIG. 3B . The first patterning process in this embodiment is the same as the first patterning process in the first embodiment, which will not be repeated here.

In the second patterning process, on the substrate on which the gate electrode pattern and the gate insulating layer are formed, source electrode and data line patterns are formed through a patterning process, as shown in FIG. 4A and FIG. 4B . The second patterning process in this embodiment is the same as the second patterning process in the first embodiment, and will not be repeated here.

In the third patterning process, on the substrate on which the active electrode and the data line pattern are formed, the active layer and the drain electrode pattern are formed through a patterning process. Forming the pattern of the active layer and the drain electrode includes: depositing an active layer film and a third metal film in sequence on the substrate formed with the aforementioned patterns, coating a layer of photoresist on the third metal film, and using a halftone mask The photoresist is exposed and developed in a stepwise manner with a reticle or a gray-tone reticle, and an unexposed area is formed at the position of the drain electrode pattern with a first thickness of photoresist, and a partially exposed area is formed at the position of the active layer pattern, with a second thickness of the photoresist. Thickness of photoresist, complete exposure areas are formed in the remaining positions, no photoresist, and the first thickness is greater than the second thickness. The third metal film and the active layer film in the fully exposed area are etched away by the first etching process, and the photoresist ashing process is performed to remove the second thickness of the photoresist as a whole, exposing the partially exposed area. The third metal film, the third metal film in the partially exposed area is etched away by the second etching process, the remaining photoresist is peeled off, and the pattern of the active layer 13 and the drain electrode 15 is formed, and the active layer 13 is located on the source electrode. 14, the drain electrode 15 is located on the active layer 13, the orthographic projection width of the drain electrode 15 on the substrate is smaller than the orthographic projection width of the active layer 13 on the substrate, and the orthographic projection of the active layer 13 and the drain electrode 15 on the substrate It at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate, as shown in FIG. 9 .

In actual implementation, the third patterning process can also use the patterning process of a common mask to form the active layer and the drain electrode pattern, specifically: depositing the active layer film and the third metal film sequentially on the substrate formed with the foregoing pattern, A layer of photoresist is coated on the third metal thin film, and the photoresist is exposed and developed using a common mask, an unexposed area is formed at the position of the drain electrode pattern, the photoresist is retained, and the remaining positions are completely formed. Exposure area without photoresist. The third metal film and the active layer film in the fully exposed area are etched away through an etching process, and the remaining photoresist is peeled off to form an active layer and a drain electrode pattern. The patterns of the drain electrode and the active layer are the same.

It can be seen from the processes of preparing thin film transistors shown in FIGS. 3A, 3B, 4A, 4B and 9 that in this embodiment, a thin film transistor with a vertical channel structure is formed through three patterning processes, and the three patterning processes can be 2 times normal mask and 1 time halftone mask or gray tone mask, also can be 3 times normal mask. In this embodiment, parameters such as the material and thickness of each film layer are the same as those in the first embodiment. Compared with the thin film transistor with the existing horizontal channel structure, the size of the thin film transistor in this embodiment can be reduced by 50%-60%.

Fourth Embodiment

Based on the technical solutions of the foregoing first to third embodiments, the present application further provides an array substrate including the foregoing thin film transistors. The preparation process of the array substrate includes:

Thin film transistors are formed on the substrate.

A passivation layer is deposited on the substrate on which the thin film transistor is formed, a layer of photoresist is coated on the passivation layer, a single-tone mask is used to expose and develop the photoresist, and the pattern position of the via hole in the passivation layer is exposed and developed. A fully exposed area is formed, the photoresist is removed, an unexposed area is formed in the remaining positions, the photoresist is retained, the passivation layer in the fully exposed area is etched and the remaining photoresist is stripped to form a passivation layer via hole pattern, and the passivation layer via hole is located where the second electrode is located. Wherein, the passivation layer can be made of silicon nitride SiNx, silicon oxide SiOx or a composite film of SiNx/SiOx.

A transparent conductive film is deposited on the passivation layer, a layer of photoresist is coated on the transparent conductive film, and the photoresist is exposed and developed using a single-tone mask, and an unexposed area is formed at the position of the pixel electrode pattern. With photoresist, a fully exposed area is formed in the remaining positions, the photoresist is removed, the transparent conductive film in the fully exposed area is etched and the remaining photoresist is peeled off to form the pattern of pixel electrode 17, and the pixel electrode passes through the passivation layer. The via hole is connected to the second electrode, as shown in FIG. 10A and FIG. 10B .

The array substrate prepared in this embodiment includes: gate lines, data lines, thin film transistors and pixel electrodes, wherein the thin film transistors and the pixel electrodes are located in the pixel unit defined by the vertical intersection of the gate lines and the data lines, and the gate lines and the thin film transistors The gate electrode is connected, the pixel electrode is connected to the second electrode of the thin film transistor, the orthographic projection of the data line on the substrate and the orthographic projection of the gate electrode on the substrate have an overlapping area, and the portion of the data line corresponding to the overlapping area serves as the thin film transistor the first electrode. Specifically, the array substrate includes:

the gate electrode 11 and the gate line 20 arranged on the substrate 10;

the gate insulating layer 12 covering the gate electrode 11 and the gate line 20;

The first electrode 14 and the data line 30 disposed on the gate insulating layer 12, the first electrode 14 is the overlapping portion of the data line 30 and the gate electrode 11, and the orthographic projection on the substrate is at least the orthographic projection of the gate electrode 11 on the substrate. partial overlap;

the orthographic projection of the active layer 13 disposed on the first electrode 14 on the substrate at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate;

the orthographic projection of the second electrode 15 disposed on the active layer 13 on the substrate at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate;

The passivation layer 16 covering the above pattern is provided with a passivation layer via hole at the position of the second electrode 15;

The pixel electrode 17 disposed on the passivation layer 16 is connected to the second electrode 15 through the passivation layer via hole.

Wherein, the first electrode 14, the active layer 13 and the second electrode 15 stacked in sequence form a vertical channel structure. The first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode. The thickness of the active layer is 2000-8000 angstroms, and the material of the active layer can be either polysilicon to form an LTPS thin film transistor, or metal oxide to form an Oxide thin film transistor. The width of the orthographic projection of the first electrode and the second electrode on the substrate is 3 to 5 microns, the width of the orthographic projection of the gate electrode on the substrate is 4 to 6 microns, and the width of the gate electrode is the width of the first electrode or the second electrode. 1.0-2.0 times, preferably, the width of the gate electrode is 1.2-1.3 times the width of the first electrode or the second electrode.

This embodiment provides an array substrate, because the first electrode, the active layer and the second electrode are sequentially stacked on the surface of the gate electrode away from the substrate, and the first electrode, the active layer and the second electrode are arranged on the substrate. The orthographic projection and the orthographic projection of the gate electrode on the substrate at least partially overlap, with a smaller TFT size, which can not only improve the aperture ratio and achieve high-resolution display, but also ensure the alignment accuracy and line width control, and improve the yield. .

Fifth Embodiment

Based on the inventive concept of the foregoing embodiments, an embodiment of the present invention provides a method for fabricating a thin film transistor, including:

S1, forming a gate electrode and a gate insulating layer on the substrate;

S2, forming a first electrode, an active layer and a second electrode sequentially stacked on the surface of the gate electrode away from the substrate on the gate insulating layer.

In one embodiment, step S2 may include:

S211, forming a first electrode on the gate insulating layer through a patterning process, and the orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate;

S212, forming an active layer on the first electrode through a patterning process, and the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate;

S213 , forming a second electrode on the active layer through a patterning process, the orthographic projection of the second electrode on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate.

In another embodiment, step S2 may include:

S221, forming a stacked first electrode and an active layer on the gate insulating layer through a patterning process of a half-tone mask or a gray-tone mask, and the orthographic projection of the first electrode and the active layer on the substrate is the same as that of the gate electrode on the substrate The orthographic projections on are at least partially coincident;

S222 , forming a second electrode on the active layer through a patterning process, the orthographic projection of the second electrode on the substrate at least partially coincides with the orthographic projection of the gate electrode on the substrate.

In another embodiment, step S2 may include:

S231, forming a first electrode on the gate insulating layer through a patterning process, and the orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate;

S232, forming a stacked active layer and a second electrode on the first electrode through a patterning process of a half-tone mask or a gray-tone mask, and the orthographic projection of the active layer and the second electrode on the substrate is the same as that of the gate electrode on the substrate The orthographic projections on are at least partially coincident.

Wherein, the first electrode, the active layer and the second electrode stacked in sequence form a vertical channel structure. The first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode. The thickness of the active layer is 2000-8000 angstroms, and the material of the active layer can be either polysilicon to form an LTPS thin film transistor, or metal oxide to form an Oxide thin film transistor. The width of the orthographic projection of the first electrode and the second electrode on the substrate is 3 to 5 microns, the width of the orthographic projection of the gate electrode on the substrate is 4 to 6 microns, and the width of the gate electrode is the width of the first electrode or the second electrode. 1.0-2.0 times, preferably, the width of the gate electrode is 1.2-1.3 times the width of the first electrode or the second electrode.

Sixth Embodiment

Based on the inventive concept of the foregoing embodiments, an embodiment of the present invention further provides a display panel, the display panel including the thin film transistor using the foregoing embodiment, or including the array substrate using the foregoing embodiment. The display panel can be any product or component with display function, such as mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. It can be a liquid crystal display (LCD) display panel, or an organic Light-emitting diode (Organic Light-Emitting Diode, OLED) display panel and so on.

In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom" "The orientation or positional relationship indicated by "inside", "outside", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must be It has a specific orientation, is constructed and operates in a specific orientation, and therefore should not be construed as a limitation of the present invention.

In the description of the embodiments of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited. For example, it may be a fixed connection or a Removable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

Although the embodiments disclosed in the present invention are as above, the described contents are only the embodiments adopted to facilitate the understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form and details of the implementation, but the scope of the patent protection of the present invention must still be The scope defined by the appended claims shall prevail.

Claims (10)

1. A thin film transistor comprises a gate electrode arranged on a substrate and a gate insulating layer covering the gate electrode, and is characterized by further comprising a first electrode, an active layer and a second electrode which are sequentially overlapped on the surface of the gate electrode, which is far away from the substrate; the patterns of the first electrode and the active layer are the same, namely the orthographic projection of the first electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; or, the patterns of the second electrode and the active layer are the same, that is, the orthographic projection of the second electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; the orthographic projection range of the first electrode, the active layer and the second electrode on the substrate is located within the orthographic projection range of the gate electrode on the substrate, and the orthographic projection width of the gate electrode on the substrate is 1.2-1.3 times that of the orthographic projection width of the first electrode or the second electrode on the substrate.

2. The thin film transistor according to claim 1, wherein the first electrode, the active layer, and the second electrode which are sequentially stacked on a surface of the gate electrode away from the substrate comprise: the first electrode is arranged on the gate insulating layer, the active layer is arranged on the first electrode, the second electrode is arranged on the active layer, and the first electrode, the active layer and the second electrode which are sequentially overlapped form a vertical channel structure.

3. The thin film transistor according to claim 1, wherein the material of the active layer comprises polysilicon or metal oxide, and has a thickness of 2000 to 8000 angstroms.

4. A method for manufacturing a thin film transistor includes:

forming a gate electrode and a gate insulating layer on a substrate;

forming a first electrode, an active layer and a second electrode which are sequentially overlapped on the surface of the gate electrode, which is far away from the substrate, on the gate insulating layer; the patterns of the first electrode and the active layer are the same, namely the orthographic projection of the first electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; or, the patterns of the second electrode and the active layer are the same, that is, the orthographic projection of the second electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; the orthographic projection range of the first electrode, the active layer and the second electrode on the substrate is located within the orthographic projection range of the gate electrode on the substrate, and the orthographic projection width of the gate electrode on the substrate is 1.2-1.3 times that of the orthographic projection width of the first electrode or the second electrode on the substrate.

5. The method according to claim 4, wherein the forming of the first electrode, the active layer, and the second electrode on the gate insulating layer, which are sequentially stacked on the surface of the gate electrode away from the substrate, comprises:

forming a first electrode on the gate insulating layer through a patterning process; forming an active layer on the first electrode through a patterning process; a second electrode is formed on the active layer through a patterning process.

6. The method according to claim 4, wherein the forming of the first electrode, the active layer, and the second electrode on the gate insulating layer, which are sequentially stacked on the surface of the gate electrode away from the substrate, comprises:

forming a first electrode and an active layer which are overlapped on the gate insulating layer through a composition process of a half-tone mask or a gray-tone mask; a second electrode is formed on the active layer through a patterning process.

7. The method according to claim 4, wherein the forming of the first electrode, the active layer, and the second electrode on the gate insulating layer, which are sequentially stacked on the surface of the gate electrode away from the substrate, comprises:

forming a first electrode on the gate insulating layer through a patterning process; and forming a stacked active layer and a second electrode on the first electrode through a patterning process of a half-tone mask or a gray-tone mask.

8. The method according to claim 4, wherein the active layer comprises polysilicon or metal oxide with a thickness of 2000-8000 angstroms.

9. An array substrate, comprising a gate line, a data line, a pixel electrode and the thin film transistor of any one of claims 1 to 3, wherein the gate line is connected to the gate electrode of the thin film transistor, the pixel electrode is connected to the second electrode of the thin film transistor, an orthographic projection of the data line on a substrate and an orthographic projection of the gate electrode on the substrate have an overlapping region, and a portion of the data line corresponding to the overlapping region is used as the first electrode of the thin film transistor.

10. A display panel comprising the array substrate according to claim 9.

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