CN106953511B - Switching power circuit and its adjusting method - Google Patents
Switching power circuit and its adjusting method Download PDFInfo
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- CN106953511B CN106953511B CN201710296120.4A CN201710296120A CN106953511B CN 106953511 B CN106953511 B CN 106953511B CN 201710296120 A CN201710296120 A CN 201710296120A CN 106953511 B CN106953511 B CN 106953511B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
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Abstract
The invention discloses switching power circuit and its adjusting methods, switching power circuit includes: main circuit, it includes switching node and the main switch for being controlled by switching signal, and main circuit has the first ground terminal, the input terminal for receiving input direct-current signal and for providing the output end of output direct current signal；I2C bus module generates control data；Control circuit generates switching signal according to control data and/or output direct current signal, and is generated according to control data and adjust data-signal；Buffer circuit, it is connected between the second ground terminal and the switching node of main circuit, the resistance value and capacitance of buffer circuit are controlled by adjusting data-signal, can be provided at switching node and the matched buffering grounding path of the main circuit of switching power circuit without carrying out duplicate welding and dismounting to buffer circuit, improve signal waveform integrality and debugging efficiency at switching node.
Description
Technical field
The present invention relates to electronic circuit fields, more particularly, to switching power circuit and its adjusting method.
Background technique
Switching power circuit has advantage high-efficient, that output electric current is big, therefore is widely used in the electricity in each field
Lu Zhong, for example, using switching power circuit as display backlight mould group power supply module design in backlight driving chip, will switch
Power circuit is applied in liquid crystal display die set (LCD Module, LCM) in bias supply driving chip and by Switching Power Supply
Circuit design is realized in charging chip to battery charging etc..
However, switching power circuit is usually since the influence of parasitic capacitance and parasitic inductance causes to generate vibration at switching node
Bell phenomenon (ringing), to will affect the integrality of signal, and may be in electromagnetic interference (Electromagnetic
Interference, EMI) and radio frequency (Radio Frequency, RF) test in easily lead to some sections in switching power circuit
Point overtension the problems such as and there is exception.
The above problem is illustrated by taking the switching power circuit of boost type arrangement (Boost) as an example below.
Fig. 1 shows the schematic equivalent circuit of the switching power circuit of boost type arrangement, and section parasitic electricity is shown
(Lp1 to Lp5), parasitic capacitance and parasitic inductance are according in switching power circuit for appearance (Cp1 and Cp2) and section parasitic inductance
Route or device etc. influence the equivalent model come out of factor of circuit performance.As shown in Figure 1, switching node LX be inductance L1 with
Switching tube Q1 connected node.The distribution of parasitic inductance is substantially in switching power circuit are as follows: switching tube Q1 and power ground PGND it
Between there are parasitic inductance Lp2, diode and inductance L1 on the lead that is connected there are parasitic inductance Lp1, switching tube Q1 with inductance L1
There are parasitic inductance Lp3 on connected lead, and there are parasitic inductance Lp4, output capacitances between diode D1 and output end vo ut
There are parasitic inductance Lp5 between Cout and power ground PGND；Key parasitic capacitor in switching power circuit includes: switching tube Q1
Parasitic capacitance Cp2 existing for itself existing parasitic capacitance Cp1 and diode D1 itself.Due to these parasitic capacitances and parasitism electricity
Sense would generally generate mutual inductance, so as to cause vibration in the certain frequency range of the voltage on switching node LX (being greater than 200MHz)
It swings, i.e. ringing.When the maximum value that the amplitude of the oscillation can bear beyond switching tube Q1, exception will occur by switching tube Q1
It even damages, and the conduct radiation as caused by the oscillation and/or electromagnetic interference also will affect neighbouring chip.
For the oscillation amplitude for reducing ringing, following method can be theoretically used: the small switch of selection parasitic capacitance
Pipe Q1 and diode D1；Switching tube Q1, diode D1 and inductance L1 are disposed adjacent to reduce and post as far as possible in circuit layout
Raw inductance Lp2 and Lp3；Power ground PGND is set near switching tube Q1 to reduce parasitic inductance Lp1；By output capacitance Cout and
Diode D1 and power ground PGND are placed adjacent, to reduce parasitic inductance Lp4 and Lp5；In output end vo ut and power ground
A shunt capacitance Cbyp is accessed between PGND, to filter out high frequency spurs.
However since above-mentioned theory is difficult to carry out in actual design, the prior art is usually in switching node LX and ground
Between series connection access buffer circuit (snubber).As shown in Figure 1, buffer circuit includes being connected between switching node LX and ground
Buffer resistance and buffering capacitor, which provides a grounding path for the electric current that parasitic inductance generates to inhibit to switch
Ringing on node LX, i.e., the amplitude for the oscillation for inhibiting parasitic capacitance to generate when switching tube is connected simultaneously reduce parasitic inductance
The spike waveform of generation.
The above-mentioned prior art, which has following defects that, to be needed manually to carry out the buffer resistance in buffer circuit with buffering capacitor
Debugging, and need to be correspondingly arranged different resistance values and capacitance according to the layout and cabling of different switching power circuits, it is debugging
In the process repeatedly replacement element will will lead to debugging efficiency it is very low, influence design process；Capacitor and buffering are buffered in the prior art
Resistance is usually the discrete member for being welded on printed circuit board (Printed Circuit Board, PCB), being set to outside chip
Part or small package element, increasingly close with what is be laid out on the reduction of pcb board size and pcb board, the position of buffer circuit is chosen
And its difficulty of welding will will increase.
Summary of the invention
In order to solve the above-mentioned problems of the prior art, the purpose of the present invention is to provide a kind of switching power circuit and
Its adjusting method, solving can only go replacement capacitor, resistance complete to adjust signal at switching node by manual in the prior art
It is laid out close on the problem of whole property and pcb board and is difficult to the problem of accommodating buffer circuit.
According to an aspect of the present invention, a kind of switching power circuit is provided, which is characterized in that the switching power circuit
It include: main circuit comprising switching node and the main switch for being controlled by switching signal, the main circuit have the first ground connection
End, the input terminal for receiving input direct-current signal and for provides export direct current signal output end；I2C bus module,
It generates control data according to serial data and serial clock；Control circuit, according to the control data and/or output direct current
Signal generates the switching signal, and is generated according to the control data and adjust data-signal；Buffer circuit is connected to second
To provide the buffering grounding path of the switching node, the buffering between ground terminal and the switching node of the main circuit
The resistance value and capacitance of circuit are controlled by the adjusting data-signal.
Preferably, the buffer circuit includes: register, is used to storing the adjusting data-signal and is stored
The adjusting data-signal is converted into configuration signal output；And capacitance-resistance module, offer is provided and is connected in series in the joint
The optional buffer resistance of resistance value and capacitance between point and second ground terminal optionally buffer capacitor, the buffer resistance and
The buffering capacitor constitutes the buffering grounding path, and the resistance value of the buffer resistance and the capacitance for buffering capacitor are controlled by
The configuration signal.
Preferably, the adjusting data-signal includes at least first part and second part, and the first part indicates institute
The resistance value of buffer resistance is stated, the second part indicates the capacitance of the buffering capacitor.
Preferably, the capacitance-resistance module includes: buffer resistance selecting unit comprising and the resistance of multiple parallel connections is described more
The turn-on and turn-off of parallel branch are controlled by the configuration signal and the adjusting where at least partly resistance in a resistance
The first part of data-signal corresponds to position accordingly, buffers capacitance selection unit comprising the capacitor of multiple parallel connections, it is described
The turn-on and turn-off of parallel branch are controlled by the configuration signal and the tune where at least partly capacitor in multiple capacitors
The second part of section data-signal corresponds to position accordingly.
Preferably, the configuration signal further includes Part III, and the Part III indicates the unlatching of the buffer circuit
And shutdown, the buffer circuit further include the enabled switch being connected on the buffering grounding path, the enabled switch is led
Logical and shutdown is controlled by corresponding position corresponding with the adjusting Part III of data-signal in the configuration signal.
Preferably, the I2C bus module, the control circuit, the buffer circuit are set in same chip, the master
Circuit is set in the chip or is at least partially disposed in outside the chip.
According to another aspect of the present invention, a kind of adjusting method of switching power circuit, the switch power supply are provided
Road includes: main circuit, and input direct-current signal is converted to output direct current signal using the main switch for being controlled by switching signal,
Buffer circuit is connected with the switching node of the main circuit to provide and buffer grounding path, which is characterized in that the adjusting side
Method includes: to utilize I2C bus receives serial data；According to the serial data and/or output direct current signal generation
Switching signal；It is generated according to the serial data and adjusts data-signal；The buffering electricity is selected according to the adjusting data-signal
The resistance value and capacitance on road.
Preferably, the adjusting data-signal includes at least first part and second part, and the first part indicates institute
The resistance value of buffer circuit is stated, the second part indicates the capacitance of the buffer circuit.
Preferably, the adjusting data-signal further includes Part III, and the Part III indicates the buffer circuit
It is switched on and off.
Preferably, the step of resistance value and capacitance of the buffer circuit being selected according to the adjusting data-signal include: by
The adjusting data-signal is converted to the corresponding configuration signal；Correspondence position according to the configuration signal is electric by the buffering
In road with it is described adjust data-signal first part indicated by resistance value buffer resistance and have the adjustings data believe
Number second part indicated by capacitance buffering capacitor connect to form the buffering grounding path.
The invention has the advantages that by the way that buffer circuit is arranged at the switching node of switching power circuit, and utilize
I2The serial data that C bus module receives adjusts the resistance value and capacitance of buffer circuit, without carrying out weight to buffer circuit
Multiple welding and dismounting can provide at switching node and the matched buffering grounding path of the main circuit of switching power circuit,
The debugging efficiency of buffer circuit is improved while improving the signal waveform integrality at switching node.In some preferred realities
It applies in example, at least partly circuit in buffer circuit and switching power circuit is located in same chip, therefore can be omitted individually
The step of welding buffer circuit, and the number of elements on printed circuit board can be reduced, while saving and opening on printed circuit board
The layout area of powered-down source circuit and Power Management Unit.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 shows the schematic equivalent circuit of the switching power circuit of boost type arrangement.
Fig. 2 shows the structural schematic diagrams of the switching power circuit of first embodiment of the invention.
Fig. 3 shows the partial structure diagram of buffer circuit in the switching power circuit of the embodiment of the present invention.
Fig. 4 shows the schematic diagram of the functions of the adjusting data-signal of first embodiment of the invention.
Fig. 5 shows the flow diagram of the adjusting method of the switching power circuit of second embodiment of the invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.In addition, may not show in figure
Certain well known parts out.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The Power Management Unit of first embodiment of the invention includes at least one switching power circuit.
Switching power circuit can be boost type arrangement (Boost), voltage-dropping type structure (Buck) or buck-boost type structure
(Boost-Buck) etc..It may include the switching power circuit of multiple and different types in Power Management Unit.Such as applied to liquid
Power Management Unit in crystal device may include multiple for generating different voltages (gate-on voltage VGH, grid pass
Power-off pressure VGL, common voltage Vcom and simulation supply voltage AVDD etc.) switching power circuit 1100.
It can also include multiple functional modules, such as grid impulse applied to the Power Management Unit in liquid crystal display device
It modulation module (Grid Pulse Modulation, GPM), common voltage buffer module, linear regulation module (LDO) and puts
Big module etc..
As one embodiment, each section circuit in Power Management Unit (including switching power circuit and functional module)
It is integrated in same chip.
It is illustrated by taking the switching power circuit of boost type arrangement 1100 as an example and referring to attached drawing below.
Fig. 2 shows the structural schematic diagrams of the switching power circuit of first embodiment of the invention.
As shown in Fig. 2, the switching power circuit 1100 of first embodiment of the invention includes main circuit 1110, I2C bus mould
Block 1120, control circuit 1130 and buffer circuit 1140.
Main circuit 1110 is Boost structure, be mainly used for for input direct-current signal being converted into output direct current signal (such as
Output voltage Vout shown in figure).In order to uniformly show the connection relationship between main circuit 1110 and other each section circuits,
The partial circuit in main circuit 1110 is illustrated only in Fig. 2, mainly includes switching tube Q1 and switching tube Q2.Switching tube Q1 and switch
Pipe Q2 is connected between output voltage Vout and the first ground terminal PGND1, and switching tube Q1 receives control as the power tube of main circuit
The switching signal pwm that circuit 1130 processed provides, switching tube Q2 (replacing diode D1 shown in FIG. 1) is as the same of main circuit 1110
It walks pipe and receives synchronization signal p_syn to reduce rectifier loss.The common node of switching tube Q1 and Q2 are denoted as switching node LX, switch
The path terminal that pipe Q1 is not connected with switching node LX is connected with the first ground terminal PGND1, switching tube Q2 not with switching node LX phase
Path terminal even provides output direct current signal.As a kind of alternative embodiment, switching tube Q2 also could alternatively be diode with
Reduce cost.
Main circuit 1110 can also be the structures such as Buck or Buck-Boost, such as when main circuit 1110 is Buck structure
When, a path terminal of power tube (its control terminal receives switching signal pwm) receives input direct-current signal, another path terminal and opens
Artis LX is connected, the two paths end of lock-in tube (its control terminal receive synchronization signal p_syn) respectively with switching node LX and
First ground terminal PGND1 is connected.
I2The data terminal and clock end of C bus module 1120 respectively with serial data line (Serial Data, SDA), serial
Clock line (Serial Clock, SCL) is connected to receive serial data s_da and serial clock s_cl.I2C bus module 1120
Control data d_sqn is generated according to serial data and serial clock.
Output direct current signal (such as output voltage Vout) that control circuit 1130 is used to be provided according to main circuit 1110 and
I2The control data d_syn that C bus module 1120 provides generates switching signal pwm and synchronization signal p_syn with control switch pipe
The turn-on and turn-off of Q1 and switching tube Q2, to realize the feedback control of switching power circuit.Meanwhile control circuit 1130 goes back root
According to I2The control data d_syn that C bus module 1120 provides, which is generated, adjusts data-signal d_tun, every kind of adjusting data-signal d_
Tun corresponds to the one group of resistance value and capacitance of buffer circuit 1140.
Buffer circuit 1140 includes register 1141 and capacitance-resistance module 1142, wherein capacitance-resistance module 1142 is for providing string
The optional buffer resistance R_b of the resistance value being coupled between switching node LX and the second ground terminal PGND2 and capacitance optionally buffer electricity
Hold the buffering grounding path that C_b, buffer resistance R_b and buffering capacitor C_b constitute switching node LX.Register 1141 is according to adjusting
Data-signal d_tun generates and stores corresponding configuration signal c_buf, and configuration signal c_buf is for directly controlling capacitance-resistance module
The capacitance of the resistance value of buffer resistance R_b and buffering capacitor C_b in 1142.
The buffering grounding path as provided by buffer circuit 1140 can determine the work of entire switching power circuit 1100
Make effect, thus the second ground terminal PGND2 usually from the corresponding different grounding pin of the first ground terminal PGND1.Buffer circuit
1140 connect the buffer resistance R_b of the selected resistance value and buffering capacitor C_b of selected capacitance under the control of configuration signal c_buf
It connects between switching node LX and the second ground terminal PGND2, due to the resistance value of buffer resistance R_b and the capacitance of buffering capacitor C_b
It is controlled by configuration signal c_buf, therefore designer can be by I2C bus module 1120 inputs different serial data s_
Da (corresponding different configuration signal c_buf) changes the resistance value of buffer resistance R_b in buffer circuit 1140 and buffers capacitor C_b's
Capacitance, to make buffer circuit 1140 match with main circuit 1110 to weaken or eliminate the ringing and mistake at switching node LX
Rush phenomenon.
Fig. 3 shows the partial structure diagram of buffer circuit in the switching power circuit of the embodiment of the present invention.
Buffer circuit 1140 in the switching power circuit 1100 of the embodiment of the present invention includes register 1141 and capacitance-resistance mould
Block 1142.As shown in figure 3, capacitance-resistance module 1142 include buffer U0, enabled switch K0, buffer resistance selecting unit 1142r and
Buffer capacitance selection unit 1142c.The input terminal of buffer U0 is connected with switching node LX, output end and enabled switch K0 one
End is connected, buffer resistance selecting unit 1142r and buffering capacitance selection unit 1142c be connected on enabled switch K0 the other end and
Between second ground terminal PGND2.
Buffer resistance selecting unit 1142r includes the branch of n item parallel connection, and n is non-zero natural number, and every branch road is in series with
One first switch (one of K11 to K1n, as shown in Figure 3) and a resistance (R1 to Rn, as shown in figure 3, being located at same branch
First switch and resistance label it is corresponding).In addition to this, can also include in buffer resistance selecting unit 1142r and the n item
The initial resistance branch of branch circuit parallel connection, which includes an initial resistance R0.Buffer resistance selecting unit
Equivalent resistance is equal to quilt in the branch (further including initial resistance branch in the embodiment with initial resistance branch) of n item parallel connection
The parallel value of the resistance of the branch road of conducting.
Buffering capacitance selection unit 1142c includes the branch of m item parallel connection, and m is non-zero natural number, and every branch road is in series with
One second switch (one of K21 to K2m, as shown in Figure 3) and a capacitor (C1 to Cm, as shown in figure 3, being located at same branch
Second switch and capacitor label it is corresponding).In addition to this, buffering in capacitance selection unit 1142c can also include and the m item
The initial capacitance branch of branch circuit parallel connection, which includes an initial capacitance C0, and capacitance is, for example, 10pF.It is slow
Rush capacitance selection unit equivalent capacity be equal to the parallel connection of m item branch (further include in the embodiment with initial capacitance branch
Initial capacitance branch) in be switched on branch road capacitor parallel value.
Enabled switch K0, first switch K11 to K1n and second switch K21 to K2n are controlled by register in buffer circuit
The correspondence position of the configuration signal c_buf of 1141 outputs, enables switch K0, first switch K11 to K1n and second switch K21 extremely
K2n is, for example, MOSFET.Wherein enable signal K0 is used to control the conducting and shutdown of buffer circuit, and first switch K11 to K1n is used
In by carrying out selection and the resistance value in parallel to determine buffer resistance to each branch resistance, second switch K21 to K2m is for passing through
Selection and combination is carried out to each branch capacitor to determine the capacitance of buffering capacitor.
Such as n=3, the resistance value of resistance R1 to R3 is for example followed successively by 15 Ω, 10 Ω and 8.2 Ω, first switch K11
Corresponding 3 bit in configuration signal c_buf is controlled by K13 (namely to be controlled by and adjust data-signal d_tun's
Corresponding position).This 3 bit, which is set as ' 001 ', can make first switch K11 conducting, K12 and K13 shutdown, thus will buffering
The resistance value of resistance R_b is determined as 15 Ω；By this 3 bit be set as ' 101 ' can make first switch K11 and K13 conducting,
K12 shutdown, so that the resistance value of buffer resistance R_b is determined as R1//R3=15//8.2=5.3 Ω；This 3 bit is set
First switch K11 to K13 can be made to be both turned on for ' 111 ', so that the resistance value of buffer resistance R_b is determined as R1//R2//R3=
10//15//8.2=3.4 Ω, and so on, to realize buffer resistance using 3 bits in configuration signal c_buf
7 kinds of resistance values of R_b (can use 3 bits in configuration signal c_buf in the embodiment with initial resistance branch
Realize 8 kinds of resistance values of buffer resistance R_b).
Similarly, such as m=3, the capacitance of capacitor C1 to C3 is for example followed successively by 22pF, 33pF and 68pF and initial electricity
The capacitance for holding the initial capacitance C0 of branch road is equal to 10pF, and second switch K21 to K23 is controlled by configuration signal c_buf
Corresponding other 3 bit (namely being controlled by the correspondence position for adjusting data-signal d_tun).This 3 bit is set
Second switch K21 to K23 can be made to be turned off for ' 000 ', so that the capacitance for buffering capacitor C_b is determined as C0=10pF；It will
This 3 bit, which is set as ' 001 ', can make second switch K21 conducting, K22 and K23 shutdown, to will buffer capacitor C_b's
Capacitance is determined as C1+C0=32pF；This 3 bit, which is set as ' 101 ', can make second switch K21 and K23 conducting, K22
Shutdown, so that the capacitance for buffering capacitor C_b is determined as C1+C3+C0=100pF；This 3 bit is set as ' 111 ' can
So that second switch K21 to K23 is both turned on, so that the capacitance for buffering capacitor C_b is determined as C1+C2+C3+C0=133pF, with
This analogizes, to realize that 8 kinds of capacitances of buffering capacitor C_b (are being not present using 3 bits in configuration signal c_buf
It can use 3 bits in configuration signal c_buf realize buffering capacitor C_b 7 in the embodiment of initial capacitance branch
Kind capacitance).
As a kind of alternative embodiment, buffer circuit 1140 includes for providing total electricity of the buffer resistance of various resistance values
The total capacitance of resistance and the buffering capacitor for providing various capacitances.Wherein, the resistance value of all-in resistance be set as switching power circuit can
The maximum value for the buffer resistance that can be needed, the capacitance of total capacitance are set as the maximum for the buffering capacitor that switching power circuit may need
Value.All-in resistance and total capacitance can be passive element or active component.All-in resistance has multiple first nodes, multiple first nodes
Among two first nodes between definition have a kind of resistance value buffer resistance, therefore from multiple first nodes draw two
Different nodes can define a variety of resistance values of buffer resistance.Total capacitance has multiple second nodes, among multiple second nodes
Definition has a kind of buffering capacitor of capacitance between two second nodes, therefore two different sections are drawn from multiple second nodes
Point can define a variety of capacitances of buffering capacitor.Since buffer resistance and buffering capacitor are connected in series, by buffer resistance R_b
Third node is denoted as with the common node of buffering capacitor C_b.Each first node leads to respectively with switching node LX and/or third node
It crosses a first switch tube to be connected, the grid of first switch tube is controlled by the correspondence position in configuration signal c_buf, i.e. configuration signal
Correspondence position in c_buf can be corresponding by the buffer resistance both ends of selected resistance value by controlling the turn-on and turn-off of first switch tube
First node be connected respectively with switching node LX and third node.Each second node and third node and/or the second ground terminal
PGND2 passes through a second switch respectively and is connected, and the grid of second switch is controlled by the correspondence position of configuration signal c_buf,
Configuring the correspondence position in signal c_buf can be electric by the buffering of selected capacitance by controlling the turn-on and turn-off of second switch
Hold the corresponding second node in both ends to be connected with third node and the second ground terminal PGND2 respectively.To sum up, configuration signal c_buf is logical
Cross buffer resistance in the conducting and shutdown selection buffer circuit for the switching tube that control is connected with each first node and each second node
The resistance value of R_b and the capacitance of buffering capacitor C_b.
Fig. 4 shows the schematic diagram of the functions of the adjusting data-signal of first embodiment of the invention.
As shown in figure 4, adjusting includes three parts in a frame data of data-signal d_tun: first part is for selecting
The resistance value of buffer resistance in buffer circuit, second part are used to select to buffer the capacitance of capacitor in buffer circuit, and Part III is used
In being switched on and off for control buffer circuit.
As a kind of specific embodiment, a valid data section (such as a frame data) of data-signal d_tun is adjusted
Including at least 8 data, in turn below for exchange respectively section data-signal d_tun functions be described.
The 8th d_tun [7] of data-signal is adjusted for controlling being switched on and off for buffer circuit 1140.Such as work as tune
When the 8th d_tun [7] for saving data-signal is 1, buffer circuit 1140 is opened and the buffering ground connection for providing switching node LX
Path；When the 8th d_tun [7] for adjusting data-signal is 0, buffer circuit 1140 is closed.Specifically, as shown in figure 3, matching
The conducting and shutdown of enabled switch K0 are controlled in confidence c_buf with the 8th corresponding corresponding position for adjusting data-signal, thus
Realize being switched on and off for buffer circuit 1140.
The 6th to the 4th d_tun [5:3] of data-signal is adjusted for selecting buffer resistance R_b in buffer circuit 1140
One of resistance value r1 to r7 (r1 to r7 is for example followed successively by 15 Ω, 10 Ω, 6 Ω, 8.2 Ω, 5.3 Ω, 4.5 Ω and 3.4
Ω), can by each branch resistance in buffer resistance selecting unit as shown in Figure 3 carry out selection and parallel connection obtain, example
If buffer resistance selecting unit only need to include that 7 kinds of resistance values of buffer resistance R_b can be realized in the resistance of 3 kinds of resistance values).Specifically,
As shown in figure 3, controlling first switch respectively with the 6th to 4 corresponding corresponding position for adjusting data-signal in configuration signal c_buf
The conducting and shutdown of K11 to K1n, thus realize selection to the resistance of each branch road in buffer resistance selecting unit and/or
Combination, is set as desired value for buffer resistance R_b.
The 3rd to the 1st d_tun [2:0] for adjusting data-signal buffers capacitor C_b for selecting in buffer circuit 1140
One of capacitance c1 to c8 (c1 to c8 be for example followed successively by 10pF, 32pF, 43pF, 62pF, 78pF, 100pF, 111pF,
133pF), can by each branch capacitor in buffering capacitance selection unit as shown in Figure 3 carry out selection and parallel connection obtain,
Such as 8 kinds of capacitances of buffering capacitor C_b need to only can be realized in buffering capacitance selection unit including the capacitor of 4 kinds of capacitances).Specifically
Ground, as shown in figure 3, controlling second respectively with the 3rd to 1 corresponding corresponding position for adjusting data-signal in configuration signal c_buf
The conducting and shutdown of switch K21 to K2m, to realize the selection of the capacitor to each branch road in buffering capacitance selection unit
And/or combination, capacitor C_b will be buffered and be set as desired value.
It follows that the unlatching of buffer circuit, buffer circuit may be implemented by changing each data bit in adjusting data
Shutdown and buffering grounding path on buffer resistance resistance value selection and buffer capacitor capacitance selection.Therefore, if
Meter personnel can be input to I by changing2The serial data s_da of C bus module, which changes, adjusts data-signal d_tun, buffering electricity
Register 1141 in road 1140 will adjust data-signal d_tun and be converted to corresponding configuration signal c_buf to choose buffering electricity
The capacitance of the resistance value of buffer resistance R_b and buffering capacitor C_b in road 1140, thus by buffer resistance R_b's and buffering capacitor C_b
Value is set as desired value to weaken ringing.
Embodiment as one preferred, I2C bus module 1120, control circuit 1130 and buffer circuit 1140 are set to same
In one chip, main circuit 1110 is set in the chip or is at least partially disposed in outside the chip.
The beneficial effect of the switching power circuit of first embodiment of the invention is: at the switching node of switching power circuit
Buffer circuit is set, and utilizes I2The serial data that C bus module receives adjusts the resistance value and capacitance of buffer circuit, thus nothing
Duplicate welding and dismounting need to be carried out to buffer circuit can provide and the main circuit of switching power circuit at switching node
The buffering grounding path matched improves the debugging of buffer circuit while improving the signal waveform integrality at switching node
Efficiency.In some preferred embodiments, at least partly circuit in buffer circuit and switching power circuit is located at same chip
In, therefore the step of can be omitted individually welding buffer circuit, and printed circuit on-board switching power circuit can be saved and opened
The layout area of Power Management Unit where powered-down source circuit.
Fig. 5 shows the flow diagram of the adjusting method of the switching power circuit of second embodiment of the invention.The adjusting side
Method includes step S2100 to S2400.
The switching power circuit of second embodiment of the invention includes main circuit and buffer circuit, and wherein main circuit utilizes controlled
Input direct-current signal is converted into output direct current signal, the joint of buffer circuit and main circuit in the main switch of switching signal
Point is connected to provide and buffer grounding path.As one embodiment, the switching power circuit of second embodiment of the invention for example on
State the either switch power circuit in first embodiment.
In step S2100, I is utilized2C bus receives serial data.
In step S2200, the switching signal is generated according to the serial data and/or the output direct current signal.
In step S2300, is generated according to the serial data and adjust data-signal.
The adjusting data-signal is at least divided into first part to Part III by embodiment as one preferred；Root
The resistance value of the buffer resistance is selected according to the first part for adjusting data-signal；According to the adjusting data-signal
The second part selects the capacitance of the buffering capacitor；According to the Part III control for adjusting data-signal
The opening and closing of buffer circuit；.
In step S2400, the resistance value and capacitance of the buffer circuit are selected according to the adjusting data-signal.
The adjusting data-signal is converted to corresponding configuration signal by embodiment as one preferred；According to described
Configuration signal controls the connection relationship inside the buffer circuit will have the buffer resistance of selected resistance value and have selected hold
The buffer resistance of value connects to form the buffering grounding path.
To sum up, the adjusting method of Power Management Unit provided by the invention, switching power circuit and switching power circuit
Beneficial effect be: at the switching node of switching power circuit be arranged buffer circuit, and utilize I2C bus module receives
Serial data adjusts the resistance value and capacitance of buffer circuit, without carrying out duplicate welding to buffer circuit and dismounting can be
Main circuit matched buffering grounding path with switching power circuit is provided at switching node, is improving the letter at switching node
The debugging efficiency of buffer circuit is improved while number waveform integrality.In some preferred embodiments, buffer circuit with open
At least partly circuit in powered-down source circuit is located in same chip, therefore the step of can be omitted individually welding buffer circuit,
And the number of elements on printed circuit board can be reduced, while saving printed circuit on-board switching power circuit and power management
The layout area of unit.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.
Claims (10)
1. a kind of switching power circuit, which is characterized in that the switching power circuit includes:
Main circuit comprising switching node and the main switch for being controlled by switching signal, the main circuit have the first ground terminal,
For receiving the input terminal of input direct-current signal and for providing the output end of output direct current signal；
I2C bus module generates control data according to serial data and serial clock；
Control circuit generates the switching signal according to the control data and/or output direct current signal, and according to the control
Data processed, which generate, adjusts data-signal；
Buffer circuit is connected between the second ground terminal and the switching node of the main circuit to provide the joint
The buffering grounding path of point, the resistance value and capacitance of the buffer circuit are controlled by the adjusting data-signal,
Wherein, in debugging process, the I2C bus module receives the different serial datas to debug the buffer circuit
Resistance value and capacitance, so that the resistance value and capacitance of the buffer circuit are set to desired value after debugging process so that described
Buffer circuit is matched with the main circuit,
The buffer circuit and at least partly described main circuit are integrated in same chip, first ground terminal and described second
Ground terminal corresponds to the different pins of the chip.
2. switching power circuit according to claim 1, which is characterized in that the buffer circuit includes:
Register, is used to store the adjusting data-signal and the adjusting data-signal stored is converted into confidence
Number output；And
Capacitance-resistance module is used to provide the resistance value being connected in series between the switching node and second ground terminal and optionally delays
It rushing resistance and capacitance optionally buffers capacitor, the buffer resistance and the buffering capacitor constitute the buffering grounding path,
The resistance value of the buffer resistance and the capacitance of the buffering capacitor are controlled by the configuration signal.
3. switching power circuit according to claim 2, which is characterized in that the adjusting data-signal includes at least first
Part and second part,
The first part indicates the resistance value of the buffer resistance,
The second part indicates the capacitance of the buffering capacitor.
4. switching power circuit according to claim 3, which is characterized in that the capacitance-resistance module includes:
Buffer resistance selecting unit comprising the resistance of multiple parallel connections, where at least partly resistance in the multiple resistance simultaneously
The turn-on and turn-off of connection branch are controlled by corresponding with the adjusting first part of data-signal in the configuration signal
Corresponding position,
Buffer capacitance selection unit comprising the capacitor of multiple parallel connection, at least partly capacitor place in the multiple capacitor is simultaneously
The turn-on and turn-off of connection branch are controlled by corresponding with the adjusting second part of data-signal in the configuration signal
Corresponding position.
5. switching power circuit according to claim 3, which is characterized in that the adjusting data-signal further includes third portion
Point, the Part III indicates being switched on and off for the buffer circuit,
The buffer circuit further include be connected on it is described buffering grounding path on enabled switch, the conducting of the enabled switch and
Shutdown is controlled by corresponding position corresponding with the adjusting Part III of data-signal in the configuration signal.
6. switching power circuit according to claim 1, which is characterized in that the I2C bus module, the control circuit,
The buffer circuit is set in the chip.
7. a kind of adjusting method of switching power circuit, the switching power circuit include:
Input direct-current signal is converted to output direct current signal, institute using the main switch for being controlled by switching signal by main circuit
It states main circuit and is connected to the first ground terminal,
Buffer circuit is connected to provide the buffering being connected with the second ground terminal and be grounded road with the switching node of the main circuit
Diameter,
It is characterized in that, the adjusting method includes:
Utilize I2C bus receives serial data；
The switching signal is generated according to the serial data and/or the output direct current signal；
It is generated according to the serial data and adjusts data-signal；
The resistance value and capacitance of the buffer circuit are selected according to the adjusting data-signal,
Wherein, in debugging process, the different serial datas is provided to debug the resistance value and capacitance of the buffer circuit, from
And the resistance value and capacitance of the buffer circuit are set to desired value after debugging process so that the buffer circuit with it is described
Main circuit matching,
The buffer circuit and at least partly described main circuit are integrated in same chip, first ground terminal and described second
Ground terminal corresponds to the different pins of the chip.
8. adjusting method according to claim 7, which is characterized in that the adjusting data-signal includes at least first part
And second part, the first part indicate the resistance value of the buffer circuit, the second part indicates the buffering electricity
The capacitance on road.
9. adjusting method according to claim 8, which is characterized in that the adjusting data-signal further includes Part III,
The Part III indicates being switched on and off for the buffer circuit.
10. according to the described in any item adjusting methods of claim 8 or 9, which is characterized in that selected according to the adjusting data-signal
The step of selecting the resistance value and capacitance of the buffer circuit include:
The adjusting data-signal is converted into corresponding configuration signal；
According to the correspondence position of the configuration signal will there is the institute, first part for adjusting data-signal in the buffer circuit
The buffer resistance of the resistance value of instruction and with it is described adjust data-signal second part indicated by capacitance buffering capacitor string
Connection is to form the buffering grounding path.
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| CN201710296120.4A CN106953511B (en) | 2017-04-28 | 2017-04-28 | Switching power circuit and its adjusting method |
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| CN201710296120.4A CN106953511B (en) | 2017-04-28 | 2017-04-28 | Switching power circuit and its adjusting method |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107508455A (en) * | 2017-08-25 | 2017-12-22 | 惠科股份有限公司 | Buffer circuit and display device thereof |
| CN107845371B (en) * | 2017-10-12 | 2020-04-03 | 深圳市华星光电技术有限公司 | Power management integrated circuit and liquid crystal panel |
| CN107782943A (en) * | 2017-11-13 | 2018-03-09 | 江西怡杉环保股份有限公司 | A kind of micro current circuit and method |
| CN109062832B (en) * | 2018-07-26 | 2021-10-15 | 郑州云海信息技术有限公司 | A method, device and storage medium for adjusting I2C bus parameters |
| JP2020103008A (en) * | 2018-12-25 | 2020-07-02 | 日本電産株式会社 | Snubber circuit, control circuit, and information processing device |
| IT201900007386A1 (en) * | 2019-05-28 | 2020-11-28 | Eldor Corp Spa | DC-DC converter |
| KR20230093646A (en) * | 2021-12-20 | 2023-06-27 | 주식회사 엘지에너지솔루션 | Dc-dc converter |
| CN115694140B (en) * | 2022-12-28 | 2023-04-04 | 西安水木芯邦半导体设计有限公司 | Driving circuit applied to step-down DC-DC converter |
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