CN106935643A - HEMT and memory chip - Google Patents

Abstract

The invention provides a high electron mobility transistor and a memory chip, wherein the high electron mobility transistor comprises: a substrate; a gallium nitride layer and a gallium aluminum nitride layer, one side of the gallium nitride layer is compounded on the surface layer of the substrate, nitrogen The other side of the gallium nitride layer is compounded on the bottom of the aluminum gallium nitride layer; the oxide layer is compounded on the top layer of the aluminum gallium nitride layer, and the oxide layer is provided with at least three through contact holes; the electrode includes a drain electrode, The gate electrode and the source electrode, and the drain electrode, the gate electrode and the source electrode are respectively arranged in corresponding contact holes among the corresponding at least three through contact holes. Through the technical scheme of the invention, the interface defect between the gate electrode and the drain electrode is reduced, and the reliability of the high electron mobility transistor is improved.

Description

High Electron Mobility Transistors and Memory Chips

technical field

The invention relates to the technical field of semiconductors, in particular to a high electron mobility transistor and a memory chip.

Background technique

In related technologies, with the development of semiconductor manufacturing technology, power devices with low power consumption and high-speed high-pass characteristics have become the mainstream research direction.

GaN (Gallium Nitride) is the third generation wide bandgap semiconductor material with large bandgap (3.4eV), high electron saturation rate (2e7cm/s), high breakdown electric field (1e10--3e10V/cm), relatively It has high thermal conductivity, corrosion resistance and radiation resistance, and has strong advantages in high pressure, high frequency, high temperature, high power and radiation resistance environmental conditions, so it is considered to be a research tool for short-wave optoelectronic devices and high-voltage, high-frequency and large Optimal material for power devices.

Specifically, a high-concentration, high-mobility two-dimensional electron gas (2DEG, Two-dimensional electron gas) is formed at the AlGaN (aluminum gallium nitride)/GaN heterojunction, and the heterojunction has a good regulating effect on 2DEG. GaN AlGaN/GaN-based high-mobility transistors are a research hotspot in power devices.

However, the use of GaN materials and non-doped intrinsic materials makes it difficult to obtain HEMT (High Electron Mobility Transistor, High Electron Mobility Transistor) devices with low on-resistance, and for high-power high-frequency devices, interface defects are serious Affects the reliability of high electron mobility transistors.

Therefore, how to design a new high electron mobility transistor to improve device reliability has become an urgent technical problem to be solved.

Contents of the invention

Based on the above problems, the present invention proposes a new technical solution for high electron mobility transistors, by setting an oxide layer between aluminum gallium nitride and the electrode structure (between the gate electrode, the source electrode and the drain electrode) , reduces the interface defects of aluminum gallium nitride, reduces the surface leakage current, and improves the reliability of high electron mobility transistors.

In view of this, the present invention proposes a high electron mobility transistor, comprising: a substrate; a gallium nitride layer and an aluminum gallium nitride layer, one side of the gallium nitride layer is compounded on the surface layer of the substrate, and the The other side of the gallium nitride layer is compounded on the bottom of the gallium aluminum nitride layer; the oxide layer is compounded on the top layer of the gallium aluminum nitride layer, and the oxide layer is provided with at least three through contact holes; the electrode , the electrodes include a drain electrode, a gate electrode, and a source electrode, and the drain electrode, the gate electrode, and the source electrode are respectively arranged in the corresponding at least three through contact holes corresponding to in the contact hole.

In this technical scheme, by setting an oxide layer between the aluminum gallium nitride and the electrode structure (between the gate electrode, the source electrode and the drain electrode), the interface defects of the aluminum gallium nitride are reduced, and the surface leakage current is reduced. Improved reliability of high electron mobility transistors.

In the above technical solution, preferably, the source electrode includes a first titanium-aluminum-titanium-titanium nitride composite layer.

In the above technical solution, preferably, the drain electrode includes a second titanium-aluminum-titanium-titanium nitride composite layer, and the source electrode is separated from the drain electrode.

In the above technical solution, preferably, the gate electrode includes: a nickel-gold composite layer, the gate electrode is separated from the source electrode, and the gate electrode is separated from the drain electrode of.

In the above technical solution, preferably, the oxide layer includes: a first silicon oxide layer, and the first silicon oxide layer includes a tetraethyl orthosilicate layer.

In this technical solution, by arranging the first silicon oxide layer to include the tetraethyl orthosilicate layer, due to the compactness and reliability of the tetraethyl orthosilicate layer, the withstand voltage characteristics of the high electron mobility transistor are further ensured.

In the above technical solution, preferably, the oxide layer further includes: an aluminum oxide layer, and the aluminum oxide layer is compounded on the top layer of the first silicon nitride layer.

In this technical solution, by disposing the aluminum oxide layer in the oxide layer, the stress between the aluminum nitride layer and the silicon nitride layer is reduced, and the reliability of the high electron mobility transistor is further improved.

In the above technical solution, preferably, the aluminum gallium nitride layer includes an intrinsic aluminum gallium nitride structure layer.

In the above technical solution, preferably, further comprising: an isolation layer, compounded on the oxide layer and the top layer of the electrode.

In this technical solution, by setting the isolation layer on the top layer of the oxide layer and the electrode, the interference of the space electromagnetic signal to the high electron mobility transistor is reduced under the premise of improving the reliability of the device.

In the above technical solution, preferably, the isolation layer includes a second silicon oxide layer and/or a second silicon nitride layer.

According to a second aspect of the present invention, a memory chip is provided, including: the high electron mobility transistor described in any one of the above technical solutions.

Through the above technical scheme, by contacting the gate electrode and the source electrode, the distance between the gate and the source is eliminated, the on-resistance and power consumption of the high electron mobility transistor are effectively reduced, and the high electron mobility is improved. Reliability of mobility transistors.

Description of drawings

FIG. 1 shows a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present invention;

Fig. 2 shows a schematic block diagram of a memory chip according to an embodiment of the present invention.

detailed description

In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described here. Therefore, the protection scope of the present invention is not limited by the specific details disclosed below. EXAMPLE LIMITATIONS.

FIG. 1 shows a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention.

As shown in FIG. 1, a high electron mobility transistor 100 according to an embodiment of the present invention includes: a substrate 1; a gallium nitride layer 2 and an aluminum gallium nitride layer 3, one side of the gallium nitride layer 2 is compounded on The surface layer of the substrate 1, the other side of the gallium nitride layer 2 is compounded on the bottom of the gallium aluminum nitride layer 3; the oxide layer 4 is compounded on the top layer of the gallium aluminum nitride layer 3, the The oxide layer 4 is provided with at least three through contact holes; electrodes, the electrodes include a drain 51 electrode, a gate 52 electrode and a source 53 electrode, and the drain 51 electrode, the gate 52 electrode and the The source electrodes 53 are respectively disposed in corresponding contact holes among the at least three through contact holes.

In this technical scheme, the interface defects of the aluminum gallium nitride 3 are reduced by setting the oxide layer 4 between the aluminum gallium nitride 3 and the electrode structure (between the gate 52 electrode, the source electrode 53 electrode and the drain electrode 51 electrode), The surface leakage current is reduced and the reliability of the high electron mobility transistor is improved.

Among them, after the high electron mobility transistor 100 is applied with an electric load, the two-dimensional electron gas 7 is polarized between the gallium nitride layer 2 and the aluminum gallium nitride layer 3, which has high concentration and high mobility characteristics, and improves While device reliability is ensured, the fabrication process of the high electron mobility transistor 100 is compatible with the CMOS (Complementary Metal-Oxide-Semiconductor Transistor, Compensation Metal-Oxide-Semiconductor Transistor) process, thereby reducing the manufacturing cost.

In the above technical solution, preferably, the source electrode 53 includes a first titanium-aluminum-titanium-titanium nitride composite layer.

In the above technical solution, preferably, the drain electrode 51 includes a second titanium-aluminum-titanium-titanium nitride composite layer, and the source electrode 53 and the drain electrode 51 are separated.

In the above technical solution, preferably, the gate electrode 52 includes: a nickel-gold composite layer, the gate electrode 52 and the source electrode 53 are separated, and the gate electrode 52 and the drain The pole electrode 51 is separated.

In the above technical solution, preferably, the oxide layer 4 includes: a first silicon oxide layer, and the first silicon oxide layer includes a tetraethyl orthosilicate layer.

In this technical solution, by arranging the first silicon oxide layer to include the tetraethyl orthosilicate layer, due to the compactness and reliability of the tetraethyl orthosilicate layer, the withstand voltage characteristic of the high electron mobility transistor 100 is further ensured.

In the above technical solution, preferably, the oxide layer 4 further includes: an aluminum oxide layer, and the aluminum oxide layer is compounded on the top layer of the first silicon nitride layer.

In this technical solution, by disposing the aluminum oxide layer in the oxide layer, the stress between the aluminum nitride layer and the silicon nitride layer is reduced, and the reliability of the high electron mobility transistor 100 is further improved.

In the above technical solution, preferably, the aluminum gallium nitride layer 3 includes an intrinsic aluminum gallium nitride structure layer.

In the above technical solution, preferably, an isolation layer 6 is further included, compounded on the oxide layer 4 and the top layer of the electrodes.

In this technical solution, by disposing the isolation layer 6 on the top layer of the oxide layer 4 and the electrodes, the interference of space electromagnetic signals to the high electron mobility transistor 100 is reduced under the premise of improving device reliability.

In the above technical solution, preferably, the isolation layer includes a second silicon oxide layer and/or a second silicon nitride layer.

Fig. 2 shows a schematic block diagram of a memory chip according to an embodiment of the present invention.

As shown in FIG. 2 , a memory chip 200 according to an embodiment of the present invention includes: the high electron mobility transistor 100 described in any one of the above technical solutions.

The technical scheme of the present invention has been described in detail above in conjunction with the accompanying drawings. Considering the technical problem of how to design a new high electron mobility transistor to reduce the on-resistance proposed in the related art, the present invention proposes a new high electron mobility transistor. The technical solution of the mobility transistor reduces the interface defects of aluminum gallium nitride and the surface leakage current by setting an oxide layer between the aluminum gallium nitride and the electrode structure (between the gate electrode, the source electrode and the drain electrode). , improving the reliability of high electron mobility transistors.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A high electron mobility transistor, characterized in that, comprising: base; a gallium nitride layer and a gallium aluminum nitride layer, one side of the gallium nitride layer is compounded on the surface layer of the substrate, and the other side of the gallium nitride layer is compounded on the bottom of the gallium aluminum nitride layer; an oxide layer compounded on the top layer of the aluminum gallium nitride layer, and the oxide layer is provided with at least three through contact holes; An electrode, the electrode includes a drain electrode, a gate electrode, and a source electrode, and the drain electrode, the gate electrode, and the source electrode are respectively arranged in the corresponding at least three through contact holes corresponding contact holes. 2. The high electron mobility transistor according to claim 1, wherein The source electrode includes a first titanium-aluminum-titanium-titanium nitride composite layer. 3. The high electron mobility transistor according to claim 2, wherein The drain electrode includes a second titanium-aluminum-titanium-titanium nitride composite layer, and the source electrode and the drain electrode are separated. 4. The high electron mobility transistor according to claim 3, wherein the gate electrode comprises: In the nickel-gold composite layer, the gate electrode is separated from the source electrode, and the gate electrode is separated from the drain electrode. 5 . The high electron mobility transistor according to claim 4 , wherein the oxide layer comprises: a first silicon oxide layer, and the first silicon oxide layer comprises a tetraethyl orthosilicate layer. 6. The high electron mobility transistor according to claim 3, wherein the oxide layer further comprises: An aluminum oxide layer, the aluminum oxide layer is compounded on the top layer of the first silicon nitride layer. 7. The high electron mobility transistor according to any one of claims 1 to 6, wherein the aluminum gallium nitride layer comprises an intrinsic aluminum gallium nitride structure layer. 8. The high electron mobility transistor according to any one of claims 1 to 6, further comprising: The isolation layer is compounded on the oxide layer and the top layer of the electrode. 9. The high electron mobility transistor according to any one of claims 1 to 6, wherein the isolation layer comprises a second silicon oxide layer and/or a second silicon nitride layer. 10. A memory chip, characterized in that, comprising: A high electron mobility transistor as claimed in any one of claims 1 to 9.