CN111312815A - GaN-based power transistor structure and preparation method thereof - Google Patents

Abstract

The invention discloses a GaN-based power transistor structure and a preparation method thereof. The GaN-based power transistor structure includes: a source structure, a stacked structure, a drain structure and a gate structure, and the source structure is arranged on the first part of the stacked structure. At one end, the drain structure is arranged at the second end of the stack structure relative to the source structure; the gate structure is arranged on the stack structure, and the gate structure is arranged between the first end and the second end; wherein, the stack structure It includes: a lower barrier layer, a channel layer, an upper barrier layer and a passivation layer sequentially stacked from bottom to top. The GaN-based power transistor structure stabilizes the reverse conduction voltage drop of the device at about 0V, which enables the device to have freewheeling capability without affecting the forward conduction characteristics, which promotes the application of GaN-based power transistors in high-frequency power electronic systems. Applications.

Description

GaN-based power transistor structure and preparation method thereof

technical field

The invention relates to the technical field of semiconductor devices, in particular to a GaN-based power transistor structure and a preparation method thereof.

Background technique

A High Electron Mobility Transistor (HEMT for short) is a field effect transistor with a heterojunction structure. Among them, GaN-based HEMTs have excellent performances such as high switching speed, low parasitics, and high output power, and have great application potential in high-frequency power electronic systems. However, due to the lack of a body diode, GaN-based HEMTs do not have freewheeling capability, and have a large reverse conduction voltage drop when the device is in the off state, and this voltage drop is regulated by the gate-source voltage, which affects the synchronous rectification of the power converter. , and generate additional power loss, reducing system efficiency.

SUMMARY OF THE INVENTION

(1) Technical problems to be solved

In order to solve the technical problem that the GaN-based HEMT in the prior art does not have the freewheeling capability and has a large reverse conduction voltage drop when the device is in an off state, which affects the efficiency of the device system, the present invention discloses a GaN-based power transistor. Structure and method of making the same.

(2) Technical solutions

One aspect of the present invention discloses a GaN-based power transistor structure, comprising: a source structure, a stack structure, a drain structure and a gate structure, wherein the source structure is disposed at the first end of the stack structure, and the drain structure is opposite to The source structure is arranged on the second end of the stacked structure; the gate structure is arranged on the stacked structure, and is located between the first end and the second end; wherein, the stacked structure includes: stacking sequentially from bottom to top layer of lower barrier layer, channel layer, upper barrier layer and passivation layer.

According to an embodiment of the present invention, the GaN-based power transistor structure further includes: a base structure disposed under the stacked layer structure; the base structure includes: a buffer layer and a substrate layer, the buffer layer is disposed under the lower barrier layer; the substrate layer is disposed under the buffer layer below the layer.

According to an embodiment of the present invention, the GaN-based power transistor structure further includes: a 2DEG layer and a 2DHG layer, the 2DEG layer is formed in the channel layer and below the interface between the channel layer and the upper barrier layer; and the 2DHG layer is formed in the channel layer and formed above the interface between the lower barrier layer and the channel layer.

According to an embodiment of the present invention, the source structure includes: a source hole, a lower source and an upper source. The source hole is opened at the first end of the stacked structure and penetrates the passivation layer, the upper source and the upper source in sequence from top to bottom. The barrier layer and the channel layer are partially penetrated through the lower barrier layer; the lower source is arranged at the lower end of the source hole, and is arranged corresponding to the upper part of the lower barrier layer and the lower part of the channel layer; and the upper source The electrode is arranged on the upper end of the source hole, and is arranged corresponding to the upper part of the channel layer, the upper barrier layer and the passivation layer.

According to an embodiment of the present invention, an ohmic contact is formed between the upper source electrode and the 2DEG layer; and a Schottky contact is formed between the lower source electrode and the 2DHG layer.

According to an embodiment of the present invention, the drain structure includes: a drain hole, a lower drain, and an upper drain, the drain hole is opened at the second end of the stacked structure, and penetrates the passivation layer, the upper drain and the upper drain in sequence from top to bottom. The barrier layer and the channel layer are partially penetrated through the lower barrier layer; the lower drain is arranged at the lower end of the drain hole, and is arranged corresponding to the upper part of the lower barrier layer and the lower part of the channel layer; and the upper drain The electrode is arranged on the upper end of the drain hole, and is arranged corresponding to the upper part of the channel layer, the upper barrier layer and the passivation layer.

According to an embodiment of the present invention, an ohmic contact or Schottky contact is formed between the upper drain electrode and the 2DEG layer; and an ohmic contact is formed between the lower drain electrode and the 2DHG layer.

According to an embodiment of the present invention, the gate structure includes: a gate hole and a gate, the gate hole is opened on the passivation layer of the stacked structure, and is disposed close to the source structure, and the gate hole penetrates the passivation layer, and partially penetrated through the upper barrier layer; and the gate is arranged in the gate hole, and is arranged corresponding to the passivation layer and the upper part of the upper barrier layer.

According to an embodiment of the present invention, the material of the source structure, the drain structure or the gate structure includes: one or a combination of Ti, Al, Ni, W, Pt, Pd, Au or Ag.

According to an embodiment of the present invention, the material of the buffer layer includes GaN; the material of the lower barrier layer or the upper barrier layer includes: one or a combination of AlN, AlGaN, AlInN, InGaN or AlInGaN; The material includes: InGaN, wherein the Ga composition is between 0 and 100%; the material of the passivation layer includes: one or more combinations of silicon nitride, silicon dioxide, aluminum nitride or GaN.

According to an embodiment of the present invention, the thickness of the upper barrier layer or the lower barrier layer includes: 1 nm-50 nm, and the thickness of the channel layer is 10-500 nm.

Another aspect of the present invention discloses a preparation method for the above-mentioned GaN-based power transistor structure, including: forming a stack structure; forming a source structure and a drain structure on the stack structure; and forming a stack structure on the stack structure A gate structure is formed between the source structure and the drain structure.

According to an embodiment of the present invention, forming a source structure and a drain structure on the stacked structure includes: forming a source structure at a first end of the stacked structure, and forming a drain structure at a second end of the stacked structure; or A drain structure is formed at the second end of the stacked structure, and a source structure is formed at the first end of the stacked structure.

(3) Beneficial effects

The invention discloses a GaN-based power transistor structure and a preparation method thereof. The GaN-based power transistor structure includes: a source structure, a stack structure, a drain structure and a gate structure, and the source structure is arranged on the first part of the stack structure. At one end, the drain structure is arranged at the second end of the stack structure relative to the source structure; the gate structure is arranged on the stack structure, and the gate structure is arranged between the first end and the second end; wherein, the stack structure It includes: a lower barrier layer, a channel layer, an upper barrier layer and a passivation layer sequentially stacked from bottom to top. A double-heterojunction structure is formed by the upper barrier layer and the lower barrier layer and the channel layer between them, forming a double-channel GaN-based HEMT device structure with a 2DEG layer and a 2DHG layer, so that the 2DEG layer is used as the field effect of the device. The forward conduction channel of the transistor (Metal-Oxide-Semiconductor Field Effect Transistor, referred to as MOSFET) structure, and the 2DHG layer as the source-to-drain reverse conduction of the Schottky Barrier Diode (SBD) structure in the device Through the channel, the reverse conduction voltage drop of the device is stabilized at about 0V, so that the device has freewheeling capability without affecting the forward conduction characteristics, which promotes the application of GaN-based power transistors in high-frequency power electronic systems.

Description of drawings

FIG. 1 is a schematic composition diagram of a GaN-based power transistor structure according to an embodiment of the present invention;

2 is a schematic circuit diagram of an equivalent circuit diagram of a GaN-based power transistor structure according to an embodiment of the present invention;

3 is a schematic diagram of a corresponding energy band principle of a GaN-based power transistor structure according to an embodiment of the present invention;

4 is a schematic flowchart of a method for fabricating a GaN-based power transistor structure according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

In order to solve the technical problem that the GaN-based HEMT in the prior art does not have the freewheeling capability and has a large reverse conduction voltage drop when the device is in an off state, which affects the efficiency of the device system, the present invention discloses a GaN-based power transistor. Structure and method of making the same.

One aspect of the present invention discloses a GaN-based power transistor structure, as shown in FIG. 1 , comprising: a source structure 310 , a stacked structure 100 , a drain structure 320 and a gate structure 330 ,

The source structure 310 is disposed at the first end of the stacked structure 100 to provide a source for the GaN-based power transistor structure, and can also provide a location for extracting the source. Therefore, the upper end of the source structure 310 may partially protrude from the stacked structure 100. outside.

The drain structure 320 is disposed at the second end of the stacked structure 100 relative to the source structure 310; it is used to provide a drain for the GaN-based power transistor structure, and can also provide a location for extracting the drain, so its upper end may partially protrude from outside the stack structure 100 .

The gate structure 330 is arranged on the stacked structure 100 and is arranged between the first end and the second end; it is used to provide a gate for the GaN-based power transistor structure, and at the same time, it can provide a location for drawing out the gate, so its upper end It may partially protrude out of the laminated structure 100 .

In the embodiment of the present invention, as shown in FIG. 1 , the first end and the second end of the GaN-based power transistor structure are actually described from the perspective of the GaN-based power transistor structure as an independent structure, so as to facilitate the Those skilled in the art can accurately understand its structure. In practice, several GaN-based power transistor structures can be formed simultaneously on a wafer substrate to form an array of the GaN-based power transistor structures. For adjacent GaN-based power transistor structures, an isolation layer can be set to avoid Contact between the respective sources or drains of adjacent GaN-based power transistor structures, resulting in short-circuiting of the structures or other effects. For a GaN-based power transistor structure with an independent structure, the position of the source structure 310 can be set as the first end of the GaN-based power transistor structure, and the position of the drain structure 320 can be set as the second end of the GaN-based power transistor structure, It can also be set in reverse.

The stacked structure 100 includes: a lower barrier layer 110 , a channel layer 120 , an upper barrier layer 130 and a passivation layer 140 that are sequentially stacked from bottom to top. The stacked structure 100 is used as a functional layer of a GaN-based power transistor structure to realize the GaN-based HEMT device of the present invention. The channel layer 120 , the upper barrier layer 130 and the passivation layer 140 are used to cooperate with the source structure 310 at the first end and the drain structure 320 at the second end to form a forward conducting MOSFET structure, and the lower barrier layer 110 is used to cooperate with the source structure 310 at the first end and the drain structure 320 at the second end to form a reverse conducting SBD structure, thereby integrating the MOSFET structure and the SBD structure in a GaN-based power transistor structure. The passivation layer 140 is used to separate the outside world from the stacked structure 100 , maintain insulation properties between electrodes, prevent short circuits between the electrodes, and provide protection for the stacked structure 100 .

According to an embodiment of the present invention, as shown in FIG. 1 , the GaN-based power transistor structure further includes: a base structure 200 disposed under the stacked structure 100; the base structure 200 includes: a buffer layer 220 and a substrate layer 210, which are used to Layer structure 100 provides a substrate function to facilitate the formation of GaN-based power transistor structures on base structure 200 . The buffer layer 220 is disposed under the lower barrier layer 110, and the material of the buffer layer 220 can be a GaN material, which can not only have a good lattice match with the substrate layer 210, but also have a good lattice match with the lower barrier layer 110. Lattice matching is used to establish a more stable bonding effect between the lower barrier layer 110 and the substrate layer 210, thereby enhancing the stability of the device structure. The substrate layer 210 is disposed under the buffer layer 220 and is mainly used to provide a substrate.

According to an embodiment of the present invention, as shown in FIG. 1 , the GaN-based power transistor structure further includes: a 2DEG layer and a 2DHG layer, that is, the GaN-based power transistor structure of the present invention communicates with the upper potential through the lower barrier layer 110 and the channel layer 120 The double heterojunction structure realized by the barrier layer 130 and the channel layer 120 forms a 2DEG layer (two-dimensional electron gas layer) and a 2DHG layer (two-dimensional hole gas layer).

The 2DEG layer is formed in the channel layer 120, and the 2DEG layer is formed under the interface between the channel layer 120 and the upper barrier layer 130, so that the 2DEG layer can be used as a forward conduction channel with the source structure 310 and the drain structure 320, The gate structure 330 forms the MOSFET structure described above.

The 2DHG layer is formed in the channel layer 120, and the 2DHG layer is formed above the interface between the lower barrier layer 110 and the channel layer 120, so that the 2DEG layer can be formed as a reverse conduction channel with the source structure 310 and the drain structure 320 The above-mentioned SBD structure.

Therefore, the GaN-based power transistor structure of the present invention realizes high integration of the MOSFET structure and the SBD structure, and at the same time, the GaN-based power transistor is formed by the 2DEG layer formed in the channel layer 120 and the 2DHG layer formed in the channel layer 120. The dual-channel structure of the structure enables the GaN-based power transistor structure to stabilize the reverse conduction voltage drop of the device at about 0V when the GaN-based power transistor structure is in the off state, so that the device has a stable freewheeling capability without affecting the forward conduction characteristics. At the same time, it also maintains the original forward conduction performance such as threshold voltage, forward conduction resistance and saturation current of the original device, as well as dynamic performance such as switching speed. In addition, the high integration of MOSFET structure and SBD structure does not occupy additional wafers area, effectively reducing the size of integrated circuits, and promoting the application of GaN-based power transistors in high-frequency power electronic systems.

According to an embodiment of the present invention, as shown in FIG. 1 , the source structure 310 includes: a source hole, a lower source 311 and an upper source 312 , the source hole is opened at the first end of the stacked structure 100 , and the source hole is The passivation layer 140 , the upper barrier layer 130 , and the channel layer 120 are penetrated in sequence from top to bottom, and part of the lower barrier layer 110 is penetrated; the source hole is mainly used for the lower source electrode 311 and the upper source electrode 312 Provide accommodation space.

The lower source electrode 311 is arranged at the lower end of the source hole, and the lower source electrode 311 is arranged corresponding to the upper part of the lower barrier layer 110 and the lower part of the channel layer 120; the end face of the lower end of the lower source electrode 311 and the bottom surface of the source hole At least one side surface of the lower source electrode 311 is in contact with the end surface of the upper part of the lower barrier layer 110 corresponding to the first end and the end surface of the lower part of the channel layer 120 corresponding to the first end, so as to be in contact with the lower drain of the drain structure 320 The electrodes 321 are matched to form a 2DHG layer in the channel layer 120 above the interface between the lower barrier layer 110 and the channel layer 120 .

The upper source electrode 312 is arranged at the upper end of the source hole, and the upper source electrode 312 is arranged corresponding to the upper part of the channel layer 120 , the upper barrier layer 130 and the passivation layer 140 ; The end face of the upper end is in contact, and at least one side surface of the upper source electrode 312 and the upper part of the channel layer 120 correspond to the end face of the first end, the end face of the upper barrier layer 130 corresponding to the first end, and the end face of the passivation layer 140 corresponding to the first end. The end surfaces are in contact with each other to match with the upper drain electrode 322 of the drain structure 320 , and a 2DEG layer is formed in the channel layer 120 below the interface between the channel layer 120 and the upper barrier layer 130 .

According to an embodiment of the present invention, as shown in FIG. 1 , the drain structure 320 includes: a drain hole, a lower drain 321 and an upper drain 322 , the drain hole is opened at the second end of the stacked structure 100 , and the drain hole The passivation layer 140 , the upper barrier layer 130 and the channel layer 120 are penetrated in sequence from top to bottom, and part of the lower barrier layer 110 is penetrated; the drain hole is mainly used for the lower drain 321 and the upper drain 322 Provide accommodation space.

The lower drain 321 is arranged at the lower end of the drain hole, and the lower drain 321 is arranged corresponding to the upper part of the lower barrier layer 110 and the lower part of the channel layer 120 ; the end face of the lower end of the lower drain 321 and the bottom surface of the drain hole contact, at least one side surface of the lower drain electrode 321 is in contact with the end surface of the upper part of the lower barrier layer 110 corresponding to the first end and the end surface of the lower part of the channel layer 120 corresponding to the first end, so as to be in contact with the lower source of the source structure 310 The electrodes 311 are matched to form a 2DHG layer in the channel layer 120 above the interface between the lower barrier layer 110 and the channel layer 120 .

The upper drain 322 is arranged at the upper end of the drain hole, and the upper drain 322 is arranged corresponding to the upper part of the channel layer 120 , the upper barrier layer 130 and the passivation layer 140 ; the end face of the lower end of the upper drain 322 and the lower drain 321 The end face of the upper end is in contact, and at least one side of the upper drain 322 and the upper part of the channel layer 120 correspond to the end face of the first end, the end face of the upper barrier layer 130 corresponding to the first end, and the end face of the passivation layer 140 corresponding to the first end. The end surfaces are in contact with the upper source electrode 312 of the source electrode structure 310 to form a 2DEG layer in the channel layer 120 below the interface between the channel layer 120 and the upper barrier layer 130 .

Based on the above-mentioned GaN-based power transistor structure, as shown in FIG. 1 , wherein the channel layer 120 and the upper barrier layer 130 are used to connect with the upper source electrode 312 at the first end, the upper drain electrode 322 at the second end and the gate structure 330 forms a forward conducting MOSFET structure, and the lower barrier layer 110 is used to form a reverse conducting SBD structure with the lower source electrode 311 at the first end, the lower drain electrode 321 at the second end and the channel layer 120, thereby The MOSFET structure and the SBD structure are integrated in the GaN-based power transistor structure. As shown in FIG. 2, the GaN-based power transistor structure of the present invention can be a HEMT device structure, then the drain D of the HEMT structure is connected to the cathode (lower drain 321) of the SBD structure, and the source S of the HEMT structure is connected to the SBD The anode (lower source 311) is connected. When the gate-source voltage of the HEMT structure is greater than the threshold voltage, if the drain-source voltage is greater than 0V, the HEMT structure is in an on state, and the SBD structure is in a reverse biased state and turned off; if the drain-source voltage is less than 0V, and the drain-source voltage Slightly higher than the threshold voltage of the SBD structure, the HEMT structure cannot be turned on in the reverse direction, while the SBD structure will be in a conductive state, so that the equivalent circuit has freewheeling capability.

According to an embodiment of the present invention, as shown in FIG. 1 , a Schottky contact is formed between the lower source electrode 311 and the 2DHG layer, and an ohmic contact is formed between the lower drain electrode 321 and the 2DHG layer. Therefore, the GaN-based power transistor of the present invention The structure can form an SBD structure with a 2DHG layer through the lower source electrode 311, the lower drain electrode 321, the channel layer 120 and the lower barrier layer 110, and the 2DHG layer can be used as the reverse conduction channel of the GaN-based power transistor structure of the present invention. Provides freewheeling capability to the equivalent circuit when the device is off. As shown in FIG. 3 , the lower barrier layer 110 disposed on the buffer layer 220 is used to cooperate with the channel layer 120 to raise the energy band of the device structure, and is on the interface between the lower barrier layer 110 and the channel layer 120 . Holes are generated in the channel layer 120 of the 2DHG layer.

According to an embodiment of the present invention, as shown in FIG. 1 , an ohmic contact is formed between the upper source electrode 312 and the 2DEG layer, and an ohmic contact or Schottky contact is formed between the upper drain electrode 322 and the 2DEG layer; The transistor structure can form a MOSFET structure with a 2DEG layer through the upper source electrode 312, the upper drain electrode 322, the channel layer 120, and the upper barrier layer 130, and the 2DEG layer can be used as the forward conduction channel of the GaN-based power transistor structure of the present invention. As shown in FIG. 3 , the upper barrier layer 130 disposed on the channel layer 120 is used to cooperate with the channel layer 120 to lower the energy band of the device structure, and the interface between the upper barrier layer 130 and the channel layer 120 is Electron gas is generated in the channel layer 120 below the surface to form a 2DEG layer. Therefore, using the double heterostructure of the lower barrier layer 110/channel layer 120/upper barrier layer 130 of the present invention, the 2DEG layer and the 2DHG layer are respectively generated at the upper and lower heterointerfaces by utilizing the polarization characteristics.

According to an embodiment of the present invention, as shown in FIG. 1 , the gate structure 330 includes a gate hole and a gate, and the gate structure 330 is used to provide the gate G of the GaN-based power transistor structure of the present invention, as shown in FIG. 2 . . The gate hole is opened on the passivation layer 140 of the stacked structure 110, the gate hole is disposed close to the source structure 310, and the gate hole penetrates through the passivation layer 140 and partially penetrates the upper barrier layer 130 to form a gate The accommodating electrode provides space; and the gate is disposed in the gate hole, and the gate hole is disposed corresponding to the upper portion of the passivation layer 140 and the upper barrier layer 130 . The end face and side face of the lower end of the gate are in contact with the upper barrier layer 130 , part of the peripheral side of the gate is in contact with the passivation layer 140 , and the upper end of the gate may protrude beyond the passivation layer 140 by a certain distance . In order to lead out the gate G of the device. Similarly, the upper ends of the upper source electrode 312 and the upper drain electrode 322 may also protrude beyond the passivation layer 140 by a certain distance, so that the device can lead out the source electrode S and the drain electrode D, as shown in FIG. 1 . In addition, the gate hole is disposed close to the source structure 310, so that the gate-source voltage Vgs applied through the gate can realize the turn-on of the MOSFET structure, so that the threshold voltage of the device is more stable.

In addition, the gate can deplete the 2DEG (two-dimensional electron gas) on the corresponding channel layer 120 , so that the 2DEG layer at the corresponding position disappears to form a normally-off device structure. When a certain gate-source voltage Vgs is applied, the MOSFET structure realizes forward conduction. Therefore, the GaN-based power transistor structure of the present invention can be applied to both enhancement mode/depletion mode GaN-based MIS/MES-HEMT devices and integration with anti-parallel Schottky diodes.

According to an embodiment of the present invention, the material of the source structure 310 , the drain structure 320 or the gate structure 330 includes one or a combination of Ti, Al, Ni, W, Pt, Pd, Au or Ag. Since the source structure 310 includes a lower source 311 and an upper source 312, the drain structure 320 includes a lower drain 321 and an upper drain 322, and the gate structure 330 includes a gate, therefore, the lower source 311, the upper The material selection of the source electrode 312, the lower drain electrode 321, the upper drain electrode 322 and the gate electrode includes: one or a combination of Ti, Al, Ni, W, Pt, Pd, Au or Ag. In addition, in order to form an ohmic contact between the upper source electrode 312 and the 2DEG layer, an ohmic contact or a Schottky contact is formed between the upper drain electrode 322 and the 2DEG layer to form a MOSFET structure with a 2DEG layer; A Schottky contact is formed between the 2DHG layers, an ohmic contact is formed between the lower drain electrode 321 and the 2DHG layer to form an SBD structure with a 2DHG layer, a lower source electrode 311, an upper source electrode 312, a lower drain electrode 321, and an upper drain electrode The material selection of 322 and the gate electrode can be different. For example, the material of the lower source electrode 311 can be Ti, the material of the upper source electrode 312 can be Al, the material of the lower drain electrode 321 can be Ni, and the material of the upper drain electrode 322 can be It is Pt, and is specifically intended to form the integration of an SBD structure having a 2DHG layer and a MOSFET structure having a 2DEG layer.

According to an embodiment of the present invention, as shown in FIG. 1 , the material of the buffer layer 220 includes GaN; the material of the lower barrier layer 110 or the upper barrier layer 130 includes: one of AlN, AlGaN, AlInN, InGaN or AlInGaN or The material of the channel layer 120 includes: InGaN, wherein, in the InGaN material of the channel layer 120, the Ga composition is between 0 and 100%; the material of the passivation layer 140 includes: silicon nitride, A combination of one or more of silicon dioxide, aluminum nitride, or GaN. The GaN-based material has a good direct band gap and excellent electron saturation mobility, so that the GaN-based power transistor structure of the present invention has the performance of high frequency, high temperature and high power. Band width and strong chemical stability make the device structure have good working stability, and the GaN-based material has a higher breakdown voltage, which can make the device work at higher voltages, and the polarization performance is not good, making The conduction band of the heterojunction structure of GaN-based materials is discontinuous and has stronger current capability. Those skilled in the art should understand that the GaN, AlN, AlGaN, AlInN, InGaN or AlInGaN mentioned in the present invention is only a symbolic expression of the corresponding material, not a limitation of the corresponding composition ratio of the material.

According to an embodiment of the present invention, as shown in FIG. 1 , the thickness of the upper barrier layer 130 or the lower barrier layer 110 includes: 1 nm-50 nm, specifically, the thickness of the upper barrier layer 130 may be 1 nm-10 nm, so as to As an enhancement-mode device, the device achieves better depletion function for the 2DEG layer. At other thicknesses, the device can be used as a depletion mode device. Therefore, the GaN-based power transistor structure can be either a depletion-mode HEMT structure or an enhancement-mode HEMT structure, and at the same time, the integration with the above-mentioned anti-parallel SBD structure is realized. The thickness of the channel layer is 10-500 nm.

Another aspect of the present invention discloses a preparation method for the above-mentioned GaN-based power transistor structure, as shown in FIG. 4 , comprising:

S410, forming a laminated structure;

S420, forming a source structure and a drain structure on the stacked structure;

S430 , forming a gate structure between the source structure and the drain structure on the stacked structure.

Among them, the GaN-based power transistor structure has been analyzed in detail in the above, and the passivation layer in the stacked structure can use metal organic compound chemical vapor deposition method, low pressure chemical vapor deposition method, plasma enhanced chemical vapor deposition method or formed by atomic layer deposition. The preparation method of the GaN-based power transistor structure disclosed in the present invention is compatible with the process of the traditional GaN-based HEMT device structure, and is suitable for the enhancement mode/depletion mode GaN-based MIS/MES-HEMT device and the anti-parallel connection at the same time. Integration of Schottky diodes.

According to an embodiment of the present invention, forming a source structure and a drain structure on the stacked structure includes: forming a source structure at a first end of the stacked structure, and forming a drain structure at a second end of the stacked structure; or A drain structure is formed at the second end of the stacked structure, and a source structure is formed at the first end of the stacked structure. Specifically, the source hole of the source structure and the drain hole of the drain structure can be formed at the same time, but the upper source and lower source of the source structure and the upper drain and lower drain of the drain structure are formed in sequence , for the source structure, the lower source can be formed first, and then the upper source can be formed. Similarly, the drain structure can be formed first with the lower drain, and then the upper drain. As for the preparation of the source structure and the drain structure, it can be based on Material selection for different areas, which define the order of priority for preparation.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in further detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. a GaN-based power transistor structure, is characterized in that, comprises: layered structure, a source structure, disposed at the first end of the stacked structure, a drain structure, disposed at the second end of the stack structure relative to the source structure; a gate structure disposed on the stacked structure and located between the first end and the second end; Wherein, the stacked structure includes: a lower barrier layer, a channel layer, an upper barrier layer and a passivation layer stacked in sequence from bottom to top. 2 . The GaN-based power transistor structure according to claim 1 , further comprising: a base structure disposed under the stacked structure, the base structure comprising: 3 . a buffer layer disposed under the lower barrier layer; and The substrate layer is disposed under the buffer layer. 3. The GaN-based power transistor structure according to claim 1, wherein the GaN-based power transistor structure further comprises: a 2DEG layer formed within the channel layer and below the interface of the channel layer and the upper barrier layer; and A 2DHG layer is formed in the channel layer and above the interface between the lower barrier layer and the channel layer. 4. The GaN-based power transistor structure according to claim 3, wherein the source structure comprises: a source hole, which is opened at the first end of the stacked structure, penetrates the passivation layer, the upper barrier layer and the channel layer in sequence from top to bottom, and partially penetrates the lower barrier layer; a lower source electrode, disposed at the lower end of the source hole, corresponding to the upper part of the lower barrier layer and the lower part of the channel layer; and an upper source electrode, disposed at the upper end of the source electrode hole, corresponding to the upper part of the channel layer, the upper barrier layer and the passivation layer; forming an ohmic contact between the upper source and the 2DEG layer; and A Schottky contact is formed between the lower source electrode and the 2DHG layer. 5. The GaN-based power transistor structure according to claim 3, wherein the drain structure comprises: a drain hole, which is opened at the second end of the stacked structure, penetrates the passivation layer, the upper barrier layer and the channel layer in sequence from top to bottom, and partially penetrates the lower barrier layer; a lower drain, disposed at the lower end of the drain hole, corresponding to the upper part of the lower barrier layer and the lower part of the channel layer; and an upper drain, disposed at the upper end of the drain hole, corresponding to the upper part of the channel layer, the upper barrier layer and the passivation layer; forming an ohmic or Schottky contact between the upper drain and the 2DEG layer; and An ohmic contact is formed between the lower drain electrode and the 2DHG layer. 6. The GaN-based power transistor structure according to claim 3, wherein the gate structure comprises: a gate hole, opened on the passivation layer of the stacked structure, and disposed close to the source structure, and the gate hole penetrates the passivation layer and partially penetrates the upper barrier layer ;as well as The gate is disposed in the gate hole and corresponding to the upper part of the passivation layer and the upper barrier layer. 7. The GaN-based power transistor structure according to claim 1, wherein, The material of the source structure, the drain structure or the gate structure includes: a combination of one or more of Ti, Al, Ni, W, Pt, Pd, Au or Ag. 8. The GaN-based power transistor structure according to claim 2, wherein, The material of the buffer layer includes GaN; The material of the lower barrier layer or the upper barrier layer includes: one or a combination of AlN, AlGaN, AlInN, InGaN or AlInGaN; The material of the channel layer includes: InGaN, wherein the Ga composition is between 0% and 100%; The material of the passivation layer includes: one or more combinations of silicon nitride, silicon dioxide, aluminum nitride or GaN; The thickness of the upper barrier layer or the lower barrier layer includes: 1nm-50nm, and The thickness of the channel layer is 10-500 nm. 9. A preparation method for the GaN-based power transistor structure according to any one of claims 1-8, characterized in that, comprising: form a laminated structure; forming a source structure and a drain structure on the stacked structure; and A gate structure is formed between the source structure and the drain structure on the stacked structure. 10. The method for preparing a GaN-based power transistor structure according to claim 9, wherein forming a source structure and a drain structure on the stacked structure comprises: forming a source structure at a first end of the stacked structure and forming a drain structure at a second end of the stacked structure; or A drain structure is formed at a second end of the stacked structure, and a source structure is formed at a first end of the stacked structure.

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