CN106910778B - A thin film transistor and its preparation method, and an array substrate - Google Patents

Abstract

Embodiments of the present invention provide a thin film transistor, a preparation method thereof, and an array substrate, which relate to the field of display technology, and can increase the channel length of the thin film transistor without changing the size and thickness of the vertical structure. The thin film transistor includes a substrate, and a first conductive layer, an insulating layer, a second conductive layer, an active layer, a gate insulating layer, and a gate are sequentially arranged on the substrate; the active layer, the gate insulating layer, and the gate are arranged on the substrate. One side of the first conductive layer, the insulating layer and the second conductive layer; the size of the upper surface of the first conductive layer is greater than or equal to the size of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is greater than or equal to the size of the lower surface of the second conductive layer; The channel length of the thin film transistor is greater than the distance from the edge where the upper surface of the insulating layer intersects the first side surface to the edge where the lower surface of the insulating layer intersects the first side surface on the first side surface where the insulating layer contacts the active layer.

Description

A thin film transistor and its preparation method, and an array substrate

technical field

The present invention relates to the field of display technology, in particular to a thin film transistor, a preparation method thereof, and an array substrate.

Background technique

With the development of display technology, the development of ultra-high-resolution (pixels per inch, PPI) technology is gradually becoming one of the mainstream development directions. However, the aperture ratio of ultra-high-resolution products is often low.

As shown in Figure 1 (a) and Figure 1 (b), due to the traditional BCE (back channel etched) structure and Self-Aligned (self-aligned) structure of TFT (Thin Film Transistor, referred to as thin film transistor) The larger size reduces the aperture ratio of the array substrate, so it is not suitable for the development of ultra-high-resolution products. As shown in Figure 1(c), in order to ensure the aperture ratio of ultra-high-resolution products, a vertical structure TFT has been reported in the literature. Compared with the BCE structure and Self-Aligned structure TFT, the vertical structure The size of the TFT is greatly reduced, and it has good TFT characteristics. Therefore, the TFT of the vertical structure has great application prospects in ultra-high-resolution products.

As shown in Fig. 1(c), an insulating layer 30 is separated between the source electrode 02 and the drain electrode 01 of the vertical structure TFT, and the channel length is approximately equal to the thickness of the insulating layer (about 0.5 μm), which is easy to cause short-circuit The channel effect is not conducive to the stability of TFT characteristics.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a thin film transistor, a method for fabricating the same, and an array substrate, which can increase the channel length of the TFT without changing the size and thickness of the vertical structure, thereby improving the characteristics of the TFT caused by the short channel effect. unstable phenomenon.

To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

In a first aspect, a thin film transistor is provided, comprising a substrate, a first conductive layer, an insulating layer, a second conductive layer, an active layer, a gate insulating layer, and a gate electrode that are sequentially arranged on the substrate; the The active layer is disposed on one side of the first conductive layer, the insulating layer and the second conductive layer, and the gate insulating layer is disposed on the active layer away from the first conductive layer and the insulating layer. layer, one side of the second conductive layer, and the gate electrode is disposed on the side of the gate insulating layer away from the active layer.

The size of the upper surface of the first conductive layer is greater than or equal to the size of the lower surface of the insulating layer, the size of the upper surface of the insulating layer is greater than or equal to the size of the lower surface of the second conductive layer; the channel length of the thin film transistor greater than the first side surface of the insulating layer in contact with the active layer, from the edge where the upper surface of the insulating layer intersects the first side surface to the edge where the lower surface of the insulating layer intersects the first side surface edge distance.

Optionally, the first side surface is stepped.

Optionally, the size of the upper surface of the insulating layer is larger than the size of the lower surface of the second conductive layer in contact with the insulating layer; the first side surface is flat.

Preferably, the material of the insulating layer is SiOx.

In a second aspect, an array substrate is provided, including the thin film transistor described in the first aspect.

In a third aspect, a method for preparing a thin film transistor is provided, comprising sequentially forming a first conductive layer, an insulating layer, a second conductive layer, and an active layer, a gate insulating layer, and a gate on a substrate; the active layer Located on one side of the first conductive layer, the insulating layer and the second conductive layer, the gate insulating layer is located on the active layer away from the first conductive layer, the insulating layer, and the first conductive layer. On one side of the two conductive layers, the gate is located on the side of the gate insulating layer away from the active layer.

The size of the upper surface of the first conductive layer is greater than or equal to the size of the lower surface of the insulating layer, the size of the upper surface of the insulating layer is greater than or equal to the size of the lower surface of the second conductive layer; the channel length of the thin film transistor greater than the first side surface of the insulating layer in contact with the active layer, from the edge where the upper surface of the insulating layer intersects the first side surface to the edge where the lower surface of the insulating layer intersects the first side surface edge distance.

Optionally, the size of the upper surface of the insulating layer is larger than the size of the lower surface of the second conductive layer in contact with the insulating layer; the first side surface is flat. Forming the second conductive layer and the insulating layer includes:

An insulating layer film and a second conductive layer film are sequentially formed on the first conductive layer, and a first photoresist pattern is formed through a mask exposure process.

The second conductive layer thin film is over-etched by wet etching to form the second conductive layer with a size smaller than that of the first photoresist pattern.

The insulating layer thin film is etched by dry etching to form the insulating layer whose first side is planar.

Optionally, the first side surface is stepped. Forming the second conductive layer and the insulating layer includes:

An insulating layer film and a second conductive layer film are sequentially formed on the first conductive layer, and a first photoresist pattern is formed through a mask exposure process; wet etching is used to over-etch the second conductive layer film etching to form the second conductive layer with a size smaller than the size of the first photoresist pattern; dry etching is used to etch the insulating layer film for the first time to form the first side surface to be flat shape of the insulating layer.

The size of the first photoresist pattern is reduced by an ashing process to form a second photoresist pattern, and the size of the second photoresist pattern is greater than or equal to the size of the second conductive layer.

Dry etching is used to etch the insulating layer whose first side is planar for a second time to form the insulating layer whose first side is one-step-shaped.

Further preferably, when the size of the second conductive layer is smaller than the size of the second photoresist pattern, after forming the insulating layer with the first side surface in a step-like shape, the method further comprises: Including: repeating at least one ashing of the second photoresist pattern and performing a third etching on the insulating layer whose first side is one-step-shaped, so that the first side is more than one step-shaped. Step-by-step. Wherein, performing ashing on the second photoresist pattern and performing a third etching on the insulating layer whose first side is one-step-shaped, including:

The size of the second photoresist pattern is reduced by an ashing process to form a third photoresist pattern, and the size of the third photoresist pattern is greater than or equal to the size of the second conductive layer.

Dry etching is used to perform a third etching on the insulating layer whose first side is in the shape of one step, so as to increase the number of steps on the first side by one step.

Preferably, the active layer, the gate insulating layer, and the gate are formed by one patterning process.

Embodiments of the present invention provide a thin film transistor, a method for preparing the same, and an array substrate, which are formed by sequentially arranging a first conductive layer, an insulating layer, a second conductive layer, an active layer, a gate insulating layer, and a gate on the substrate. Vertical structure TFT, and the channel length of the Vertical structure TFT is longer than the first side where the insulating layer is in contact with the active layer. The distance between the sides where the sides intersect, so as to increase the channel length of the TFT without changing the size and thickness of the TFT of the vertical structure, thereby improving the phenomenon of unstable TFT characteristics caused by the short channel effect.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Fig. 1 (a) is a structural schematic diagram of a TFT with a BCE structure provided by the prior art;

FIG. 1(b) is a schematic structural diagram of a TFT with a Self-Aligned structure provided by the prior art;

Fig. 1(c) is a structural schematic diagram of a TFT with a vertical structure provided by the prior art;

FIG. 2 is a schematic structural diagram of a TFT according to an embodiment of the present invention;

3(a) is a schematic side view 1 of a TFT provided by an embodiment of the present invention;

3(b) is a second schematic side view of a TFT provided by an embodiment of the present invention;

Figure 3(c) is a schematic side view 3 of a TFT provided by an embodiment of the present invention;

FIG. 3(d) is a schematic diagram 4 of a side view of a TFT provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram 5 of a side view of a TFT according to an embodiment of the present invention;

5 is a sixth schematic side view of a TFT according to an embodiment of the present invention;

6 is a seventh schematic side view of a TFT according to an embodiment of the present invention;

FIG. 7 is a schematic side view eight of a TFT provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram 9 of a side view of a TFT according to an embodiment of the present invention;

FIG. 9 is a schematic side view tenth of a TFT according to an embodiment of the present invention;

FIG. 10 is a schematic side view eleventh of a TFT according to an embodiment of the present invention;

FIG. 11 is a schematic side view 12 of a TFT according to an embodiment of the present invention;

12 is a schematic side view thirteen of a TFT provided by an embodiment of the present invention;

FIG. 13 is a schematic flowchart of preparing a TFT with a planar first side surface according to an embodiment of the present invention;

14(a) is a schematic diagram 1 of a process for preparing a TFT with a planar first side surface provided by an embodiment of the present invention;

FIG. 14(b) is a schematic diagram 2 of a process for preparing a TFT with a planar first side surface provided by an embodiment of the present invention;

Fig. 14(c) is a schematic diagram 3 of a process for preparing a TFT with a planar first side surface provided by an embodiment of the present invention;

FIG. 15 is a schematic flowchart of preparing a TFT whose first side is a step-like shape according to an embodiment of the present invention;

FIG. 16( a ) is a schematic diagram 1 of a process for preparing a TFT with a first-level step-shaped first side according to an embodiment of the present invention;

Fig. 16(b) is a schematic diagram 2 of a process for preparing a TFT with a first-level step-shaped first side according to an embodiment of the present invention;

Fig. 16(c) is a schematic diagram 3 of a process for preparing a TFT with a first-level step-shaped first side according to an embodiment of the present invention;

FIG. 16(d) is a schematic diagram 4 of a process for preparing a TFT with a first-level step-shaped first side according to an embodiment of the present invention;

Fig. 16(e) is a schematic diagram 5 of a process for preparing a TFT with a first-level step-shaped first side according to an embodiment of the present invention;

FIG. 17 is a schematic flowchart of preparing a TFT with a second-level stepped first side according to an embodiment of the present invention;

FIG. 18( a ) is a schematic diagram 1 of a process for preparing a TFT with a second-level stepped first side according to an embodiment of the present invention;

FIG. 18( b ) is a schematic diagram 2 of a process for preparing a TFT with a second-level stepped first side according to an embodiment of the present invention.

Reference number:

01-drain; 02-source; 10-substrate; 20-first conductive layer; 30-insulating layer; 31-insulating layer film; 32-first side; 33-third side; 40-second conductive layer; 41-second conductive layer film; 42-second side; 50-active layer; 60-gate insulating layer; 70-gate; 81-first photoresist pattern; 82-second photoresist pattern ; 83-The third photoresist pattern.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a TFT, as shown in FIGS. 2-12 , comprising a substrate 10 , a first conductive layer 20 , an insulating layer 30 , a second conductive layer 40 , and an active layer disposed on the substrate 10 in sequence. 50, the gate insulating layer 60, the gate 70; the active layer 50 is arranged on one side of the first conductive layer 20, the insulating layer 30 and the second conductive layer 40, and the gate insulating layer 60 is arranged on the active layer 50 away from the first conductive layer On one side of the layer 20 , the insulating layer 30 and the second conductive layer 40 , the gate 70 is disposed on the side of the gate insulating layer 60 away from the active layer 50 .

The size of the upper surface of the first conductive layer 20 is greater than or equal to the size of the lower surface of the insulating layer 30, and the size of the upper surface of the insulating layer 30 is greater than or equal to the size of the lower surface of the second conductive layer 40; the channel length of the TFT is greater than that of the insulating layer 30 and the On the first side surface 32 in contact with the active layer 50 , the distance from the edge where the upper surface of the insulating layer 30 intersects the first side surface 32 to the edge where the lower surface of the insulating layer 30 intersects the first side surface 32 .

Here, as shown in FIG. 2 , the side of the insulating layer 30 in contact with the active layer 50 is the first side 32 , the side of the second conductive layer 40 in contact with the active layer 50 is the second side 42 , and the insulating layer 30 is more The side surface adjacent to the first side surface 32 among the side surfaces is the third side surface 33 . The channel length of the TFT is: the distance A from the side where the second side 42 and the lower surface of the second conductive layer 40 intersect to the side where the first side 32 and the upper surface of the insulating layer 30 intersect, and the first side 32 and the third side 33 . The sum of the lengths B of the intersecting sides (FIG. 2 only shows a perspective view in which the first side is planar).

Exemplarily, as shown in FIG. 3( b ), the distance from the edge where the second side surface 42 intersects the lower surface of the second conductive layer 40 to the edge where the first side surface 32 intersects the upper surface of the insulating layer 30 is A=L1, the first The length of the side where the side surface 32 and the third side surface 33 intersect is B=L2, and the channel length of the TFT is L1+L2. Compared with the prior art, the TFT channel length of the present invention is increased by L1; as shown in FIG. 8 , The distance from the edge where the second side 42 intersects the lower surface of the second conductive layer 40 to the edge where the first side 32 intersects the upper surface of the insulating layer 30 is A=L3, and the length of the edge where the first side 32 and the third side 33 intersect B=L4+L5+L6, the channel length of the TFT is L3+L4+L5+L6. Compared with the prior art, the TFT channel length of the present invention is increased by L3+L4; as shown in FIG. 9 , the second The distance from the side where the side 42 intersects the lower surface of the second conductive layer 40 to the side where the first side 32 intersects the upper surface of the insulating layer 30 is A=0, and the length of the side where the first side 32 and the third side 33 intersect is B =L7+L8+L9+L10+L11, the channel length of the TFT is L7+L8+L9+L10+L11. Compared with the prior art, the TFT channel length of the present invention is increased by L7+L8.

It should be noted that, first, in the TFT, if the first conductive layer 20 is the source electrode, the second conductive layer 40 is the drain electrode; or, the first conductive layer 20 is the drain electrode, and the second conductive layer 40 is the source electrode pole.

Here, the materials of the first conductive layer 20 and the second conductive layer 40 may be metal materials such as Mo (molybdenum), Cu (copper), Al (aluminum), AlNd (aluminum neodymium alloy), etc., or may be, for example, ITO ( Indium tin oxide), IZO (indium zinc oxide) and other transparent conductive materials.

Second, the type of TFT is not limited, and may be TFTs of amorphous silicon, metal oxide, polysilicon, organic and other types.

Third, the material of the insulating layer 30 is not limited, for example, it may be SiO _x (silicon oxide), SiN _x (silicon nitride), SiON (silicon oxynitride), and organic resin.

Fourth, as shown in FIG. 3( a ), without increasing the size of the TFT, the active layer 50 , the gate insulating layer 60 , and the gate electrode 70 can only be provided on the first conductive layer 20 , the insulating layer 30 and the second One side of the conductive layer 40 and extending on the substrate 10, it can also be disposed on one side of the first conductive layer 20, the insulating layer 30 and the second conductive layer 40, and extend from the side of the second conductive layer 40 to the other side. The upper surface is partially in contact with the upper surface of the second conductive layer 40 (as shown in FIG. 3(b) ) or in complete contact (as shown in FIG. 3(c) ), as shown in FIG. 3(d), or only It is disposed on one side of the first conductive layer 20 , the insulating layer 30 and the second conductive layer 40 .

Fifth, the surface of the first conductive layer 20 away from the substrate 10 is the upper surface, the surface opposite to the upper surface is the lower surface of the first conductive layer 20, and the surfaces adjacent to the upper surface and the lower surface are the first surface. A plurality of sides of the conductive layer 20; the surface of the insulating layer 30 away from the substrate 10 is the upper surface, and the surface opposite to the upper surface is the lower surface of the insulating layer 30, adjacent to the multiple surfaces between the upper surface and the lower surface are multiple sides of the insulating layer 30, wherein the side contacting the active layer 50 among the multiple sides is the first side 32; the surface of the second conductive layer 40 away from the substrate 10 is the upper surface, and the side opposite to the upper surface The surface is the lower surface of the second conductive layer 40, and the multiple surfaces adjacent to the upper surface and the lower surface are multiple side surfaces of the second conductive layer 40, wherein the side surfaces in contact with the active layer 50 among the multiple side surfaces are The second side 42 .

Sixth, the shape of the first side surface 32 is not limited, and its shape may be a plane shape, a curved surface shape, a stepped shape, and the like.

Seventh, in the process of forming the first side surface 32, the entire TFT needs to be processed. Therefore, in addition to the first side surface 32, other multiple side surfaces of the insulating layer 30 will also be formed with the same shape as the first side surface 32. shape.

An embodiment of the present invention provides a TFT, which is formed by sequentially disposing a first conductive layer 20 , an insulating layer 30 , a second conductive layer 40 , an active layer 50 , a gate insulating layer 60 , and a gate electrode 70 on a substrate 10 to form a Vertical structure, and the channel length of the vertical structure TFT is greater than that on the first side 32 where the insulating layer 30 is in contact with the active layer 50, and the edge where the upper surface of the insulating layer 30 and the first side 32 meet The distance between the lower surface and the side where the first side surface 32 intersects, so as to increase the channel length of the TFT without changing the size and thickness of the TFT with the vertical structure, thereby improving the unstable TFT characteristics caused by the short channel effect. The phenomenon.

Optionally, as shown in FIGS. 5-12 , the first side surface 32 is stepped.

It should be noted that the number of steps on the first side 32 is determined by the thickness of the insulating layer 30. Due to the limitation of the process, when the thickness of the insulating layer 30 is constant, the number of steps on the first side 32 increases to a certain extent, and the process cannot be realized. .

)，且经过刻蚀形成的绝缘层30的坡度较角度很大，在后续设置有源层50、栅绝缘层60、以及栅极70的过程中，容易使有源层50、栅绝缘层60、以及栅极70断裂，为了避免这种情况，将第一侧面32设置为台阶状，台阶状的第一侧面32中与衬底10平行的平面可起到缓冲作用，大大降低了有源层50、栅绝缘层60、以及栅极70断裂的风险。In the embodiment of the present invention, by setting the first side surface 32 to be stepped, on the one hand, the channel length of the TFT can be increased; on the other hand, since the thickness of the insulating layer 30 is relatively large (not less than

), and the slope of the insulating layer 30 formed by etching is relatively large, in the subsequent process of disposing the active layer 50, the gate insulating layer 60, and the gate 70, it is easy to make the active layer 50, the gate insulating layer 60 , and the gate 70 is broken. In order to avoid this situation, the first side 32 is set to be stepped, and the plane parallel to the substrate 10 in the stepped first side 32 can play a buffering role, which greatly reduces the active layer. 50, the gate insulating layer 60, and the risk of the gate 70 breaking.

Optionally, as shown in FIGS. 2-4 , the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact therewith; the first side surface 32 is flat.

In the embodiment of the present invention, in the case that the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact with it, the first side surface 32 is set to be flat, on the one hand, the channel of the TFT can be increased. length; on the other hand, it has the advantage of simple preparation process.

Preferably, the material of the insulating layer 30 is SiOx.

In the embodiment of the present invention, SiOx is used as the insulating layer material. Compared with materials such as _SiNx , SiON, and organic resins, SiOx is not conductive, so as to avoid conducting the first conductive layer 20 and the second conductive layer 40 through the insulating layer 30. Pass.

An embodiment of the present invention further provides an array substrate, including the TFT described in any of the foregoing embodiments of the present invention.

An embodiment of the present invention provides an array substrate, the array substrate includes a TFT with a vertical structure, and a first conductive layer 20 , an insulating layer 30 , a second conductive layer 40 , and an active layer are sequentially arranged on the substrate 10 of the TFT 50. The gate insulating layer 60 and the gate electrode 70, and make the channel length of the TFT larger than that on the first side 32 where the insulating layer 30 contacts the active layer 50, and the edge where the upper surface of the insulating layer 30 intersects with the first side 32 reaches The distance between the lower surface of the insulating layer 30 and the edge where the first side surface 32 intersects, so as to increase the channel length of the TFT without changing the size and thickness of the TFT with the vertical structure, thereby improving the short-channel effect. The phenomenon of unstable TFT characteristics.

An embodiment of the present invention provides a method for preparing a TFT, as shown in FIGS. 13-18 , which includes sequentially forming a first conductive layer 20 , an insulating layer 30 , a second conductive layer 40 , and an active layer 50 , an insulating layer 30 , a second conductive layer 40 on a substrate 10 , The gate insulating layer 60, the gate electrode 70; the active layer 50 is located on one side of the first conductive layer 20, the insulating layer 30 and the second conductive layer 40, and the gate insulating layer 60 is located on the active layer 50 away from the first conductive layer 20, insulating On one side of the layer 30 and the second conductive layer 40 , the gate electrode 70 is located on the side of the gate insulating layer 60 away from the active layer 50 .

The size of the upper surface of the first conductive layer 20 is greater than or equal to the size of the lower surface of the insulating layer 30, and the size of the upper surface of the insulating layer 30 is greater than or equal to the size of the lower surface of the second conductive layer 40; the channel length of the TFT is greater than that of the insulating layer 30 and the On the first side surface 32 in contact with the active layer 50 , the distance from the edge where the upper surface of the insulating layer 30 intersects the first side surface 32 to the edge where the lower surface of the insulating layer 30 intersects the first side surface 32 .

An embodiment of the present invention provides a method for fabricating a TFT, which has the same technical effect as the aforementioned array substrate, and details are not described herein again.

Optionally, as shown in FIGS. 13-14( c ), the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact with it; the first side surface 32 is flat.

Based on this, as shown in FIG. 13 , the formation of the second conductive layer 40 and the insulating layer 30 can be achieved by the following steps:

S101 , as shown in FIG. 14( a ), an insulating layer film 31 and a second conductive layer film 41 are sequentially formed on the first conductive layer 20 , and a first photoresist pattern 81 is formed through a mask exposure process.

S102 , as shown in FIG. 14( b ), wet etching is used to over-etch the second conductive layer film 41 to form a second conductive layer 40 with a size smaller than that of the first photoresist pattern 81 .

S103 , as shown in FIG. 14( c ), dry etching is used to etch the insulating layer thin film 31 to form the insulating layer 30 whose first side surface 32 is planar.

Here, the wet etching is used to over-etch the second conductive layer film 41, and the dry etching is used to etch the insulating layer film 31, both of which are consistent with the specific CD Bias (Critical Dimension Bias, etch amount for short). ), the time required for different CD Bias is different.

On this basis, the first photoresist pattern 81 can also be removed through a lift-off process, so as to facilitate the subsequent formation of the active layer 50 , the gate insulating layer 60 and the gate electrode 70 .

It should be noted that those skilled in the art should know that after the insulating layer film 31 is etched by dry etching, the size of the upper surface of the insulating layer 30 formed with the first side 32 in a planar shape is substantially equal to the size of the first surface of the insulating layer 30. A size of the photoresist pattern 81 .

In the embodiment of the present invention, when the size of the upper surface of the insulating layer 30 is larger than the size of the lower surface of the second conductive layer 40 in contact with it, the insulating layer film 31 is dry-etched to form the first side surface 32 as a flat surface The shape of the insulating layer 30, on the one hand, can increase the channel length of the TFT; on the other hand, has the advantage of a simple fabrication process.

Of course, the insulating layer 30 with the first side surface 32 in a plane shape can also be formed in other ways, which is not limited herein.

Optionally, as shown in FIGS. 15-16(e), the first side surface 32 is stepped.

Based on this, as shown in FIG. 15 , the formation of the second conductive layer 40 and the insulating layer 30 can be achieved by the following steps:

S201 , as shown in FIG. 16( a ), an insulating layer film 31 and a second conductive layer film 41 are sequentially formed on the first conductive layer 20 , and a first photoresist pattern 81 is formed through a mask exposure process.

S202 , as shown in FIG. 16( b ), wet etching is used to over-etch the second conductive layer film 41 to form a second conductive layer 40 with a size smaller than that of the first photoresist pattern 81 .

S203 , as shown in FIG. 16( c ), dry etching is used to etch the insulating layer film 31 for the first time to form the insulating layer 30 whose first side surface 32 is planar.

It should be noted that those skilled in the art should know that after the insulating layer film 31 is etched by dry etching, the size of the upper surface of the insulating layer 30 with the first side surface 32 formed in a plane shape is basically is equal to the size of the first photoresist pattern 81 .

S204 , as shown in FIG. 16( d ), an ashing process is used to reduce the size of the first photoresist pattern 81 to form a second photoresist pattern 82 , and the size of the second photoresist pattern 82 is greater than or equal to the second conductive pattern Dimensions of layer 40 .

S205 , as shown in FIG. 16( e ), dry etching is used to etch the insulating layer 30 whose first side 32 is planar for a second time to form the first side 32 whose first side 32 is a step. The insulating layer 30 (FIG. 16(e) only shows one of the cases in which the first side surface 32 is in a step-like shape, for other cases, please refer to FIGS. 5-8).

Here, the second conductive layer film 41 is over-etched by wet etching, the insulating layer film 31 is etched for the first time by dry etching, and the first side 32 is flattened by dry etching The insulating layer 30 in the shape of a second time is etched, which is related to the specific CD Bias, and the time required for different CD Bias is different.

On this basis, the second photoresist pattern 82 can also be removed by a lift-off process, so as to facilitate the subsequent formation of the active layer 50 , the gate insulating layer 60 and the gate electrode 70 .

It should be noted that those skilled in the art should know that after dry etching is used to etch the insulating layer 30 whose first side surface 32 is planar, the formed first side surface 32 is step-shaped. The size of the upper surface of the insulating layer 30 is substantially equal to the size of the second photoresist pattern 82 .

In the embodiment of the present invention, the insulating layer film 31 is first dry etched to form the insulating layer 30 with the first side surface 32 in a planar shape, and then an ashing process is used to reduce the size of the first photoresist pattern 81 , and finally The second dry etching is performed on the insulating layer 30 whose first side 32 is in a planar shape to form the insulating layer 30 whose first side 32 is in a step-like shape. On the one hand, the channel length of the TFT can be increased; On the one hand, the plane parallel to the substrate 10 in the stepped first side surface 32 can play a buffer role, which greatly reduces the risk of breakage of the active layer 50 , the gate insulating layer 60 , and the gate electrode 70 .

Of course, the insulating layer 30 with the first side surface 32 in the shape of one step can also be formed in other ways, which is not limited here.

Further preferably, as shown in FIGS. 17-18(b), when the size of the second conductive layer 40 is smaller than the size of the second photoresist pattern 82, the first side surface 32 is formed in a stepped shape. After the insulating layer 30 is formed, the method further includes: repeating at least once ashing the second photoresist pattern 82 and performing a third etching on the insulating layer 30 with the first side surface 32 in a step-like shape, so as to The first side surface 32 is formed in a multi-step shape.

Wherein, as shown in FIG. 17 , ashing is performed on the second photoresist pattern 82 and a third etching is performed on the insulating layer 30 whose first side surface 32 is in the shape of a step, which can be achieved by the following steps:

S301 , as shown in FIG. 18( a ), an ashing process is used to reduce the size of the second photoresist pattern 82 to form a third photoresist pattern 83 , and the size of the third photoresist pattern 83 is greater than or equal to the second conductive pattern Dimensions of layer 40 .

S302 , as shown in FIG. 18( b ), dry etching is used to perform a third etching on the insulating layer 30 with the first side surface 32 in the shape of one step, so as to increase the number of steps of the first side surface 32 by one (Fig. 18(b) only shows one of the cases where the number of steps on the side of the insulating layer is increased by one step, for other cases, please refer to Figs. 9-12).

Here, dry etching is used to perform the third etching on the insulating layer 30 with the first side surface 32 in a stepped shape, which is related to the specific CD Bias, and the time required for different CD Bias is different.

On this basis, the third photoresist pattern 83 can also be removed by a lift-off process, so as to facilitate the subsequent formation of the active layer 50 , the gate insulating layer 60 and the gate electrode 70 .

It should be noted that, first, those skilled in the art should know that after dry etching is used to etch the insulating layer 30 whose first side 32 is one-step-shaped, the formed first side 32 is The size of the upper surface of the two-step-shaped insulating layer 30 is substantially equal to the size of the third photoresist pattern 83 .

Second, the number of steps on the first side surface 32 and the number of times the second photoresist pattern 82 is ashed and the insulating layer 30 whose first side surface 32 is one-step-shaped is dry-etched are determined by the insulating layer. The thickness of layer 30 is determined.

In the embodiment of the present invention, by increasing the number of steps of the first side surface 32, the number of planes parallel to the substrate 10 in the stepped first side surface 32 is increased, and the distance of each step is shortened. The first side surface 32 and the first side surface 32 with the multi-step steps can play a better buffer function, so as to better avoid the breakage of the active layer 50 , the gate insulating layer 60 , and the gate electrode 70 .

Of course, the insulating layer 30 with the first side surface 32 in the shape of multiple steps can also be formed in other ways, which is not limited here.

Preferably, as shown in FIGS. 3( b ) and 3 ( c ), the active layer 50 , the gate insulating layer 60 and the gate electrode 70 are formed by one patterning process.

In the embodiment of the present invention, the active layer 50 , the gate insulating layer 60 , and the gate electrode 70 are formed by one patterning process, which has the advantage of simplifying the manufacturing process.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A thin film transistor comprises a substrate, a first conducting layer, an insulating layer, a second conducting layer, an active layer, a gate insulating layer and a gate, wherein the first conducting layer, the insulating layer and the second conducting layer are sequentially arranged on the substrate from bottom to top; the active layer is arranged on one side of the first conducting layer, the insulating layer and the second conducting layer, the gate insulating layer is arranged on one side of the active layer far away from the first conducting layer, the insulating layer and the second conducting layer, the gate electrode is arranged on one side of the gate insulating layer far away from the active layer,

the size of the upper surface of the first conducting layer is larger than or equal to that of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is larger than or equal to that of the lower surface of the second conducting layer;

the channel length of the thin film transistor is longer than the distance from the edge of the upper surface of the insulating layer, which is intersected with the first side surface, to the edge of the lower surface of the insulating layer, which is intersected with the first side surface, on the first side surface of the insulating layer, which is contacted with the active layer.

2. The thin film transistor of claim 1, wherein the first side surface is stepped.

3. The thin film transistor according to claim 1, wherein a size of an upper surface of the insulating layer is larger than a size of a lower surface of the second conductive layer in contact therewith;

the first side surface is planar.

4. The thin film transistor according to any one of claims 1 to 3, wherein a material of the insulating layer is SiOx.

5. An array substrate comprising the thin film transistor according to any one of claims 1 to 4.

6. A preparation method of a thin film transistor comprises the steps of sequentially forming a first conducting layer, an insulating layer, a second conducting layer, an active layer, a gate insulating layer and a gate electrode on a substrate from bottom to top; the active layer is located on one side of the first conductive layer, the insulating layer and the second conductive layer, the gate insulating layer is located on one side of the active layer away from the first conductive layer, the insulating layer and the second conductive layer, and the gate electrode is located on one side of the gate insulating layer away from the active layer,

the size of the upper surface of the first conducting layer is larger than or equal to that of the lower surface of the insulating layer, and the size of the upper surface of the insulating layer is larger than or equal to that of the lower surface of the second conducting layer;

the channel length of the thin film transistor is longer than the distance from the edge of the upper surface of the insulating layer, which is intersected with the first side surface, to the edge of the lower surface of the insulating layer, which is intersected with the first side surface, on the first side surface of the insulating layer, which is contacted with the active layer.

7. The manufacturing method according to claim 6, wherein a size of an upper surface of the insulating layer is larger than a size of a lower surface of the second conductive layer in contact therewith; the first side surface is planar;

forming the second conductive layer, the insulating layer, including:

sequentially forming an insulating layer film and a second conductive layer film on the first conductive layer, and forming a first photoresist pattern through a mask exposure process;

performing over-etching on the second conducting layer film by adopting wet etching to form the second conducting layer with the size smaller than that of the first photoresist pattern;

and etching the insulating layer film by adopting dry etching to form the insulating layer with the planar first side surface.

8. The method of claim 6, wherein the first side is stepped;

forming the second conductive layer, the insulating layer, including:

sequentially forming an insulating layer film and a second conductive layer film on the first conductive layer, and forming a first photoresist pattern through a mask exposure process;

performing over-etching on the second conducting layer film by adopting wet etching to form the second conducting layer with the size smaller than that of the first photoresist pattern;

performing first etching on the insulating layer film by adopting dry etching to form the insulating layer with the planar first side surface;

reducing the size of the first photoresist pattern by adopting an ashing process to form a second photoresist pattern, wherein the size of the second photoresist pattern is larger than or equal to that of the second conductive layer;

and performing secondary etching on the insulating layer with the planar first side surface by adopting dry etching to form the insulating layer with the primary step-shaped first side surface.

9. The method according to claim 8, wherein after the insulating layer with the first side surface stepped one step is formed in a case where the size of the second conductive layer is smaller than the size of the second photoresist pattern, the method further comprises: ashing the second photoresist pattern and etching the insulating layer with the first side in the shape of the one-step for the third time at least once to enable the first side to be in the shape of the multi-step;

ashing the second photoresist pattern and etching the insulating layer with the first side in the first step shape for the third time, wherein the ashing step comprises:

reducing the size of the second photoresist pattern by adopting an ashing process to form a third photoresist pattern, wherein the size of the third photoresist pattern is larger than or equal to that of the second conductive layer;

and performing third etching on the insulating layer with the first side surface in the first step shape by adopting dry etching so as to increase the number of steps of the first side surface by one step.

10. The method according to claim 6, wherein the active layer, the gate insulating layer and the gate electrode are formed by a single patterning process.

Images