CN106887393A - It is integrated with the method for packing of the encapsulating structure of power transmission chip - Google Patents
It is integrated with the method for packing of the encapsulating structure of power transmission chip Download PDFInfo
- Publication number
- CN106887393A CN106887393A CN201710172468.2A CN201710172468A CN106887393A CN 106887393 A CN106887393 A CN 106887393A CN 201710172468 A CN201710172468 A CN 201710172468A CN 106887393 A CN106887393 A CN 106887393A
- Authority
- CN
- China
- Prior art keywords
- chip
- power
- power transmission
- layer
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/992—Noise prevention, e.g. preventing crosstalk
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供一种集成有功率传输芯片的封装结构的封装方法，所述封装结构包括用电芯片及连接于所述用电芯片下方的功率传输芯片；所述功率传输芯片用于将外部电源的电压转换成所述用电芯片所需的多个电压，并提供多条对接所述用电芯片的供电轨道。本发明的封装方法利用所述功率传输芯片3作为有源2.5D中介板，通过微凸块或其它凸块结构将用电芯片5集成在有源2.5D中介板上，得到三维堆叠芯片结构。整个系统电路板的功率传输系统由所述功率传输芯片实现，可以消除封装基板上的寄生电阻，从而提高功率传输效率，改善功率控制的响应时间，提高保真度。
The present invention provides a packaging method for a packaging structure integrated with a power transmission chip. The packaging structure includes a power consumption chip and a power transmission chip connected under the power consumption chip; the power transmission chip is used to integrate an external power supply The voltage is converted into multiple voltages required by the power chip, and multiple power supply rails are provided for connecting the power chip. The packaging method of the present invention uses the power transmission chip 3 as an active 2.5D interposer, and integrates the power consumption chip 5 on the active 2.5D interposer through micro-bumps or other bump structures to obtain a three-dimensional stacked chip structure. The power transmission system of the entire system circuit board is realized by the power transmission chip, which can eliminate the parasitic resistance on the packaging substrate, thereby improving the power transmission efficiency, improving the response time of power control, and improving the fidelity.
Description
技术领域technical field
本发明属于半导体封装技术领域，涉及一种集成有功率传输芯片的封装结构的封装方法。The invention belongs to the technical field of semiconductor packaging, and relates to a packaging method for a packaging structure integrated with a power transmission chip.
背景技术Background technique
所有的计算和通信系统都需要功率传输系统。功率传输系统会将电源的高电压转换成系统中离散器件所需的许多不同的低电压。功率传输系统的效率决定了向下转换的电力损失，而功率传输轨数决定了可支持的离散电压供应或器件的数量。All computing and communication systems require power delivery systems. A power delivery system converts the high voltage of a power supply to the many different low voltages required by the discrete components in the system. The efficiency of the power delivery system determines the power loss for down conversion, while the number of power delivery rails determines the number of discrete voltage supplies or devices that can be supported.
目前的功率传输技术面临着如下挑战：Current power transfer technologies face the following challenges:
一、随着工艺节点的收缩，器件电压减小，功率传输的效率会随之降低，使功率消耗更大。1. As the process node shrinks and the device voltage decreases, the efficiency of power transmission will decrease accordingly, resulting in greater power consumption.
二、添加更多的功率传输轨道需要复制更多的功率传输组件，会增加元件数量、增大电路板尺寸、增加电路板的层数、加大系统体积、成本和重量。Second, adding more power transmission tracks requires duplicating more power transmission components, which will increase the number of components, increase the size of the circuit board, increase the number of layers of the circuit board, and increase the volume, cost and weight of the system.
三、由于再布线层的线距、线宽的限制，需要增加封装尺寸。3. Due to the limitation of the line distance and line width of the rewiring layer, it is necessary to increase the package size.
因此，如何提高功率传输效率，增加不同电压轨道的可用数量，已成为本领域技术人员亟待解决的一个重要技术问题。Therefore, how to improve power transmission efficiency and increase the available number of different voltage rails has become an important technical problem to be solved urgently by those skilled in the art.
发明内容Contents of the invention
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种集成有功率传输芯片的封装结构的封装方法，用于解决现有功率传输系统的功率传输效率低，不同电压轨道的可用数量少的问题。In view of the shortcomings of the prior art described above, the object of the present invention is to provide a packaging method for a packaging structure integrated with a power transmission chip, which is used to solve the problem of low power transmission efficiency and the availability of different voltage rails in the existing power transmission system. less problem.
为实现上述目的及其他相关目的，本发明提供一种集成有功率传输芯片的封装结构的封装方法，所述封装结构包括用电芯片及连接于所述用电芯片下方的功率传输芯片；所述功率传输芯片用于将外部电源的电压转换成所述用电芯片所需的多个电压，并提供多条对接所述用电芯片的供电轨道；所述封装方法包括如下步骤：In order to achieve the above purpose and other related purposes, the present invention provides a packaging method for a packaging structure integrated with a power transmission chip, the packaging structure includes a power consumption chip and a power transmission chip connected under the power consumption chip; The power transmission chip is used to convert the voltage of the external power supply into multiple voltages required by the power chip, and provide a plurality of power supply rails connected to the power chip; the packaging method includes the following steps:
提供一载体，并在所述载体上形成粘附层；providing a carrier, and forming an adhesive layer on the carrier;
将所述功率传输芯片的有源元件与无源元件放置于所述粘附层上，其中，所述有源元件及无源元件具有焊盘的一面朝上；placing the active and passive components of the power transmission chip on the adhesive layer, wherein the active and passive components have pads facing up;
在所述粘附层上形成覆盖所述有源元件与无源元件的塑封层，并对所述塑封层进行研磨，以暴露出所述焊盘；forming a plastic sealing layer covering the active components and passive components on the adhesive layer, and grinding the plastic sealing layer to expose the pad;
形成多个上下贯穿所述塑封层的通孔，并在所述通孔中填充导电材料，得到导电柱；forming a plurality of through holes penetrating through the plastic encapsulation layer up and down, and filling the through holes with conductive material to obtain conductive columns;
在所述塑封层上形成所述功率传输芯片的再布线层；所述再布线层的导电部分与所述导电柱及所述焊盘连接，实现所述有源元件与无源元件之间的电连接，并提供多条对接所述用电芯片的供电轨道；Form the rewiring layer of the power transmission chip on the plastic encapsulation layer; the conductive part of the rewiring layer is connected to the conductive column and the pad, so as to realize the connection between the active element and the passive element Electrically connected, and providing a plurality of power supply rails connected to the power chip;
通过多个第一凸块结构将所述用电芯片与所述再布线层连接，实现所述用电芯片与多条所述供电轨道的对接；Connecting the power-using chip to the rewiring layer through a plurality of first bump structures, realizing the docking between the power-using chip and a plurality of the power supply tracks;
去除所述载体及粘附层，暴露出所述导电柱下表面；removing the carrier and the adhesive layer to expose the lower surface of the conductive pillar;
形成多个与所述导电柱连接的第二凸块结构。A plurality of second bump structures connected to the conductive pillars are formed.
可选地，所述外部电源的电压高于所述用电芯片所需的电压。Optionally, the voltage of the external power supply is higher than the voltage required by the power chip.
可选地，所述有源元件包括控制器及降压变换器；所述无源元件包括电容、电感和电阻。Optionally, the active components include a controller and a buck converter; the passive components include capacitors, inductors and resistors.
可选地，通过多个第一凸块结构将所述用电芯片与所述再布线层连接之后，还包括通过底部填充胶填满所述用电芯片与所述在布线层之间间隙的步骤，以及通过塑封材料将所述用电芯片周围包裹的步骤。Optionally, after the power-using chip is connected to the re-wiring layer through a plurality of first bump structures, the step of filling the gap between the power-using chip and the wiring layer with an underfill glue is also included. step, and a step of wrapping around the power chip with a plastic encapsulation material.
可选地，所述再布线层包括介电层及形成于所述介电层中的至少一层金属连线及至少一层导电栓；所述金属连线通过所述导电栓实现与所述有源元件、无源元件及导电柱的电连接，且当所述介电层中形成有多层金属连线时，多层金属连线之间通过所述导电栓实现层间电连接。Optionally, the rewiring layer includes a dielectric layer and at least one layer of metal wiring and at least one layer of conductive plugs formed in the dielectric layer; the metal wiring is connected to the The electrical connection of the active element, the passive element and the conductive column, and when the multilayer metal wiring is formed in the dielectric layer, the interlayer electrical connection is realized through the conductive plug between the multilayer metal wiring.
可选地，所述第一凸块结构包括微凸块。Optionally, the first bump structure includes micro bumps.
可选地，所述第二凸块结构包括球栅阵列焊球。Optionally, the second bump structure includes ball grid array solder balls.
可选地，所述用电芯片为专用集成电路。Optionally, the power chip is an application specific integrated circuit.
可选地，形成所述塑封层的方法包括压缩成型、传递模塑、液封成型、真空层压、旋涂中的任意一种或多种。Optionally, the method of forming the plastic sealing layer includes any one or more of compression molding, transfer molding, liquid seal molding, vacuum lamination, and spin coating.
可选地，形成所述通孔的方法包括激光打孔、机械钻孔、反应离子刻蚀、纳米压印中的任意一种或多种。Optionally, the method for forming the through holes includes any one or more of laser drilling, mechanical drilling, reactive ion etching, and nanoimprinting.
可选地，形成所述导电柱的方法包括电镀、化学镀、丝印、引线键合中的一种或多种。Optionally, the method for forming the conductive pillar includes one or more of electroplating, electroless plating, silk screen printing, and wire bonding.
如上所述，本发明提供了一种新的封装方法，使用三维芯片堆叠技术将用电芯片与功率传输芯片集成在一个封装结构内，具有以下有益效果：As mentioned above, the present invention provides a new packaging method, using the three-dimensional chip stacking technology to integrate the power chip and the power transmission chip into one package structure, which has the following beneficial effects:
(1)采用现有的有源元件和无源元件形成有源2.5D中介板，然后通过微凸块或其它凸块结构将用电芯片集成在有源2.5D中介板上，得到三维堆叠结构；其中，所述用电芯片可以是专用集成电路(Application Specific Integrated Circuit，简称ASIC)。(1) Use existing active components and passive components to form an active 2.5D interposer, and then integrate power chips on the active 2.5D interposer through micro-bumps or other bump structures to obtain a three-dimensional stacked structure ; Wherein, the power chip may be an Application Specific Integrated Circuit (ASIC for short).
(2)在三维堆叠结构中，有源2.5D中介板作为功率传输功率芯片，紧密集成于在用电芯片下方，解决了功率传输的问题。(2) In the three-dimensional stacking structure, the active 2.5D interposer is used as the power transmission power chip, which is tightly integrated under the power chip, which solves the problem of power transmission.
(3)整个系统电路板的功率传输系统由所述功率传输芯片实现，所述功率传输芯片包括控制器、降压变换器(buck converter)、电容器(CAP(3T))，电感(L(2T))和电阻，从而消除了系统板上所有的无源元件。(3) The power transmission system of the entire system circuit board is realized by the power transmission chip, and the power transmission chip includes a controller, a step-down converter (buck converter), a capacitor (CAP (3T)), an inductor (L (2T) )) and resistors, thereby eliminating all passive components on the system board.
(4)所述功率传输芯片中的降压变换器可以产生成千上万低电压功率传输轨道(供电轨道)，这些低电压功率传输轨道通过微凸块对接用电芯片。(4) The step-down converter in the power transmission chip can generate tens of thousands of low-voltage power transmission tracks (power supply tracks), and these low-voltage power transmission tracks are connected to the power chip through micro-bumps.
(5)本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基板例如PCB板上的寄生电阻，从而提高了功率传输效率，改善了功率控制的响应时间。(5) Since the package structure of the present invention integrates a power transmission chip containing passive components, it can eliminate parasitic resistance on a package substrate such as a PCB, thereby improving power transmission efficiency and improving the response time of power control.
(6)通过减少压降和噪声提高了保真度，从而改善了响应时间。由于需要更少的设计余量，可以获得更好的保真度性能改善。(6) Increased fidelity by reducing voltage drop and noise, resulting in improved response time. Better fidelity performance improvements can be obtained as less design margin is required.
附图说明Description of drawings
图1显示为本发明的集成有功率传输芯片的封装结构的封装方法的工艺流程图。FIG. 1 is a process flow diagram of a packaging method of a packaging structure integrated with a power transmission chip according to the present invention.
图2显示为本发明的集成有功率传输芯片的封装结构的封装方法提供一载体的示意图。FIG. 2 is a schematic diagram of providing a carrier for the packaging method of the packaging structure integrated with the power transmission chip of the present invention.
图3显示为本发明的集成有功率传输芯片的封装结构的封装方法在所述载体上形成粘附层的示意图。FIG. 3 is a schematic diagram of forming an adhesive layer on the carrier for the packaging method of the packaging structure integrated with the power transmission chip of the present invention.
图4显示为本发明的集成有功率传输芯片的封装结构的封装方法将所述功率传输芯片的有源元件与无源元件放置于所述粘附层上的示意图。FIG. 4 shows a schematic diagram of placing the active components and passive components of the power transmission chip on the adhesive layer for the packaging method of the package structure integrated with the power transmission chip of the present invention.
图5显示为本发明的集成有功率传输芯片的封装结构的封装方法在所述粘附层上形成塑封层的示意图。FIG. 5 is a schematic diagram of forming a plastic encapsulation layer on the adhesive layer for the encapsulation method of the encapsulation structure integrated with the power transmission chip of the present invention.
图6显示为本发明的集成有功率传输芯片的封装结构的封装方法在所述塑封层中形成导电柱的示意图。FIG. 6 shows a schematic diagram of forming conductive columns in the plastic packaging layer for the packaging method of the packaging structure integrated with power transmission chips according to the present invention.
图7显示为本发明的集成有功率传输芯片的封装结构的封装方法形成所述功率传输芯片的再布线层的示意图。FIG. 7 is a schematic diagram of forming the rewiring layer of the power transmission chip for the packaging method of the packaging structure integrated with the power transmission chip of the present invention.
图8显示为本发明的集成有功率传输芯片的封装结构的封装方法通过多个第一凸块结构将所述用电芯片与所述再布线层连接，并通过底部填充胶填满所述用电芯片与所述在布线层之间间隙的示意图。Fig. 8 shows the packaging method of the packaging structure integrated with the power transmission chip of the present invention to connect the power chip with the rewiring layer through a plurality of first bump structures, and fill the power supply with an underfill glue. Schematic diagram of the gap between the electrical chip and the wiring layer.
图9显示为本发明的集成有功率传输芯片的封装结构的封装方法通过塑封材料将所述用电芯片周围包裹的示意图。FIG. 9 is a schematic diagram of wrapping the power-using chip with a plastic encapsulation material in the packaging method of the packaging structure integrated with the power transmission chip according to the present invention.
图10显示为本发明的集成有功率传输芯片的封装结构的封装方法去除所述载体及粘附层的示意图。FIG. 10 is a schematic diagram of removing the carrier and the adhesive layer in the packaging method of the packaging structure integrated with the power transmission chip of the present invention.
图11显示为本发明的集成有功率传输芯片的封装结构的封装方法形成多个与所述导电柱连接的第二凸块结构的示意图。FIG. 11 shows a schematic diagram of forming a plurality of second bump structures connected to the conductive pillars for the packaging method of the packaging structure integrated with the power transmission chip of the present invention.
元件标号说明Component designation description
S1～S8 步骤S1～S8 steps
1 载体1 carrier
2 粘附层2 Adhesive layer
3 功率传输芯片3 power transmission chip
301 有源元件301 active components
302 无源元件302 passive components
3021 电容3021 capacitor
3022 电感3022 inductance
303 焊盘303 Pads
304 塑封层304 Plastic layer
305 导电柱305 conductive column
306 再布线层306 redistribution layer
3061 介电层3061 dielectric layer
3062 金属连线3062 metal wire
3063 导电栓3063 Conductive plug
4 第一凸块结构4 First bump structure
5 用电芯片5 power chips
6 底部填充胶6 Underfill
7 塑封材料7 Molding material
8 第二凸块结构8 Second bump structure
具体实施方式detailed description
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1至图11。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。See Figures 1 through 11. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.
本发明提供一种集成有功率传输芯片的封装结构的封装方法。请参阅图11，所述封装结构包括用电芯片5及连接于所述用电芯片5下方的功率传输芯片3；所述功率传输芯片3用于将外部电源的电压转换成所述用电芯片5所需的多个电压，并提供多条对接所述用电芯片5的供电轨道。本发明的封装方法利用所述功率传输芯片3作为有源2.5D中介板，通过微凸块或其它凸块结构将用电芯片5集成在有源2.5D中介板上，得到三维堆叠芯片结构。整个系统电路板的功率传输系统由所述功率传输芯片实现，可以消除封装基板上的寄生电阻，从而提高功率传输效率，改善功率控制的响应时间，提高保真度。The invention provides a packaging method for a packaging structure integrated with a power transmission chip. Please refer to FIG. 11, the package structure includes a power chip 5 and a power transmission chip 3 connected below the power chip 5; the power transmission chip 3 is used to convert the voltage of an external power supply into the power chip 5, and provide multiple power supply rails connected to the power chip 5. The packaging method of the present invention utilizes the power transmission chip 3 as an active 2.5D interposer, and integrates the power consumption chip 5 on the active 2.5D interposer through micro-bumps or other bump structures to obtain a three-dimensional stacked chip structure. The power transmission system of the entire system circuit board is realized by the power transmission chip, which can eliminate the parasitic resistance on the packaging substrate, thereby improving the power transmission efficiency, improving the response time of power control, and improving the fidelity.
本实施例中，所述功率传输芯片3包括有源元件301、无源元件302、塑封层304、导电柱305以及再布线层306。In this embodiment, the power transmission chip 3 includes an active component 301 , a passive component 302 , a plastic encapsulation layer 304 , a conductive column 305 and a rewiring layer 306 .
请参阅图1，显示为本发明的集成有功率传输芯片的封装结构的封装方法的工艺流程图，包括如下步骤：Please refer to FIG. 1, which shows a process flow chart of the packaging method of the packaging structure integrated with the power transmission chip of the present invention, including the following steps:
S1：提供一载体，并在所述载体上形成粘附层；S1: providing a carrier, and forming an adhesive layer on the carrier;
S2：将所述功率传输芯片的有源元件与无源元件放置于所述粘附层上，其中，所述有源元件及无源元件具有焊盘的一面朝上；S2: placing the active and passive components of the power transmission chip on the adhesive layer, wherein the active and passive components have pads facing up;
S3：在所述粘附层上形成覆盖所述有源元件与无源元件的塑封层，并对所述塑封层进行研磨，以暴露出所述焊盘；S3: forming a plastic sealing layer covering the active components and passive components on the adhesive layer, and grinding the plastic sealing layer to expose the pad;
S4：形成多个上下贯穿所述塑封层的通孔，并在所述通孔中填充导电材料，得到导电柱；S4: forming a plurality of through holes penetrating through the plastic encapsulation layer up and down, and filling the through holes with conductive material to obtain conductive columns;
S5：在所述塑封层上形成所述功率传输芯片的再布线层；所述再布线层的导电部分与所述导电柱及所述焊盘连接，实现所述有源元件与无源元件之间的电连接，并提供多条对接所述用电芯片的供电轨道；S5: forming a rewiring layer of the power transmission chip on the plastic encapsulation layer; the conductive part of the rewiring layer is connected to the conductive column and the pad to realize the connection between the active component and the passive component electrical connection between them, and provide a plurality of power supply rails for docking with the power chip;
S6：通过多个第一凸块结构将所述用电芯片与所述再布线层连接，实现所述用电芯片与多条所述供电轨道的对接；S6: Connect the power consumption chip to the rewiring layer through a plurality of first bump structures, so as to realize the docking between the power consumption chip and a plurality of the power supply tracks;
S7：去除所述载体及粘附层，暴露出所述导电柱下表面；S7: removing the carrier and the adhesive layer to expose the lower surface of the conductive pillar;
S8：形成多个与所述导电柱连接的第二凸块结构。S8: forming a plurality of second bump structures connected to the conductive pillars.
首先请参阅图2及图3，执行步骤S1：提供一载体1，并在所述载体1上形成粘附层2。First, please refer to FIG. 2 and FIG. 3 , step S1 is performed: providing a carrier 1 and forming an adhesive layer 2 on the carrier 1 .
具体的，所述载体的材料可以选自玻璃、硅、氧化硅、金属或陶瓷中的一种或多种，或其他类似物。所述载体1可以为平板型，例如为具有一定厚度的玻璃圆形平板。Specifically, the material of the carrier may be selected from one or more of glass, silicon, silicon oxide, metal or ceramics, or other similar materials. The carrier 1 can be flat, for example, a glass circular flat with a certain thickness.
具体的，所述粘附层2的作用是粘附固定放置于其上的元件，后续去除所述载体1时，所述粘附层2也一并被去除。Specifically, the function of the adhesive layer 2 is to adhere and fix the components placed thereon, and when the carrier 1 is subsequently removed, the adhesive layer 2 is also removed.
作为示例，所述粘附层2可以是UV胶带或热材料，其中，所述UV胶带在特定波长的光照下，粘附强度会降低，使得载体易于剥离。所述热材料在一定加热温度下，粘附强度会降低，使得载体易于剥离。当然，所述粘附层2也可以采用UV胶与热材料的结合。As an example, the adhesive layer 2 may be a UV adhesive tape or a thermal material, wherein the adhesive strength of the UV adhesive tape is reduced under light of a specific wavelength, so that the carrier is easy to peel off. When the thermal material is heated at a certain temperature, the adhesion strength will be reduced, so that the carrier is easy to peel off. Of course, the adhesive layer 2 can also use a combination of UV glue and thermal materials.
然后请参阅图4，执行步骤S2：将所述功率传输芯片3的有源元件301与无源元件302放置于所述粘附层2上，其中，所述有源元件301及无源元件302具有焊盘303的一面朝上。Then referring to FIG. 4, step S2 is performed: placing the active element 301 and the passive element 302 of the power transmission chip 3 on the adhesive layer 2, wherein the active element 301 and the passive element 302 The side with pads 303 faces up.
通常，所述有源元件301具有焊盘303的一面称之为正面，与之相对的另一面称之为背面。对于所述无源元件302，也是如此。本实施例中，是将有源元件301及无源元件302正面朝上放置于所述粘附层2上，从而粘贴固定于所述载体上。Generally, the side of the active element 301 having the pad 303 is called the front side, and the opposite side is called the back side. The same is true for the passive element 302 . In this embodiment, the active element 301 and the passive element 302 are placed on the adhesive layer 2 face up, so as to be pasted and fixed on the carrier.
具体的，首先在包含多个裸片(Die)的晶片背面贴上粘片膜(Die Attach Film，简写DFA)，或者不贴粘片膜，然后划片得到多个独立的裸片(即所述有源元件301或无源元件302)，接着拾取裸片，放置于所述粘附层2上，使所述裸片临时固定于所述载体1上。粘片膜可以是UV膜，在切割晶片后采用特定波长的光照/对膜加热可以降低膜的粘附强度，使得芯片很容易从膜上取下。Concretely, first stick a die attach film (Die Attach Film, abbreviated as DFA) on the back of the wafer comprising a plurality of bare chips (Die), or not stick a die attach film, and then obtain a plurality of independent dies by dicing (that is, the so-called The active component 301 or the passive component 302 ), then pick up the die, place it on the adhesive layer 2 , and temporarily fix the die on the carrier 1 . The sticky film can be a UV film, and the use of light with a specific wavelength/heating the film after dicing the wafer can reduce the adhesive strength of the film, making it easy to remove the chip from the film.
具体的，所述功率传输芯片3的作用是将外部电源的电压转换成所述用电芯片5所需的多个电压，并提供多条对接所述用电芯片5的供电轨道。作为示例，所述外部电源的电压高于所述用电芯片所需的电压，以下将称外部电源的电压为高电压，称用电芯片所需的电压为低电压。Specifically, the function of the power transmission chip 3 is to convert the voltage of the external power supply into multiple voltages required by the power consumption chip 5 , and provide multiple power supply rails connected to the power consumption chip 5 . As an example, the voltage of the external power supply is higher than the voltage required by the power-consuming chip. Hereinafter, the voltage of the external power supply is referred to as high voltage, and the voltage required by the power-consuming chip is referred to as low voltage.
作为示例，所述有源元件301包括控制器及降压变换器；所述无源元件302包括电容3021、电感3021和电阻(未图示)。在所述功率传输芯片中，降压变换器可以高电压变换为成千上万的低电压，这些低电压可通过后续形成的导电柱、再布线层构成多个供电轨道，并通过后续形成的第一凸块结构与顶部用电芯片对接。As an example, the active component 301 includes a controller and a buck converter; the passive component 302 includes a capacitor 3021 , an inductor 3021 and a resistor (not shown). In the power transmission chip, the step-down converter can transform a high voltage into thousands of low voltages, and these low voltages can form multiple power supply rails through the subsequently formed conductive pillars and rewiring layers, and through the subsequently formed The first bump structure is docked with the top power chip.
接着请参阅图5，执行步骤S3：在所述粘附层2上形成覆盖所述有源元件301与无源元件302的塑封层304，并对所述塑封层进行研磨，以暴露出所述焊盘303(减薄过程未图示)。Referring to FIG. 5, step S3 is performed: forming a plastic sealing layer 304 covering the active components 301 and passive components 302 on the adhesive layer 2, and grinding the plastic sealing layer to expose the pad 303 (the thinning process is not shown).
具体的，形成所述塑封层304的方法包括压缩成型、传递模塑、液封成型、真空层压、旋涂中的任意一种或多种，或其它适宜的方法。塑封材料包括环氧类树脂、液体型热固性环氧树脂、塑料等合适的材料。Specifically, the method of forming the plastic sealing layer 304 includes any one or more of compression molding, transfer molding, liquid seal molding, vacuum lamination, spin coating, or other suitable methods. The molding material includes suitable materials such as epoxy resin, liquid thermosetting epoxy resin, and plastic.
作为示例，研磨过程可以采用机械研磨工艺、化学抛光工艺、蚀刻工艺、其任意组合和/或类似工艺。As an example, the grinding process may employ a mechanical grinding process, a chemical polishing process, an etching process, any combination thereof, and/or the like.
再请参阅图6，执行步骤S4：形成多个上下贯穿所述塑封层304的通孔，并在所述通孔中填充导电材料，得到导电柱305。Referring to FIG. 6 again, step S4 is performed: forming a plurality of through holes penetrating through the plastic encapsulation layer 304 up and down, and filling the through holes with conductive material to obtain conductive pillars 305 .
具体的，所述通孔(Through Active-interposer Via，简称TAV)可以通过激光打孔、机械钻孔、反应离子刻蚀、纳米压印中的任意一种或多种，或其他适宜的方法制作。通孔填充材料可以是焊料或铜。TAV填充可通过电镀、化学镀、丝印、引线键合中的任意一种或多种，或其他合适的金属沉积工艺形成。Specifically, the through hole (Through Active-interposer Via, TAV for short) can be made by any one or more of laser drilling, mechanical drilling, reactive ion etching, nanoimprinting, or other suitable methods . The via fill material can be solder or copper. The TAV filling can be formed by any one or more of electroplating, electroless plating, silk screen, wire bonding, or other suitable metal deposition processes.
再请参阅图7，执行步骤S5：在所述塑封层304上形成所述功率传输芯片3的再布线层306；所述再布线层306的导电部分与所述导电柱305及所述焊盘303连接，实现所述有源元件301与无源元件302之间的电连接，并提供多条对接所述用电芯片5的供电轨道。Referring to FIG. 7 again, perform step S5: form the rewiring layer 306 of the power transmission chip 3 on the plastic encapsulation layer 304; the conductive part of the rewiring layer 306 is connected to the conductive column 305 and the pad 303 connection, realizing the electrical connection between the active component 301 and the passive component 302, and providing multiple power supply rails connected to the power chip 5.
具体的，所述再布线层包括介电层3061及形成于所述介电层中的至少一层金属连线3062及至少一层导电栓3063；所述金属连线3062通过所述导电栓3063实现与所述有源元件301、无源元件302及导电柱305的电连接，且当所述介电层3061中形成有多层金属连线3062时，多层金属连线3062之间通过所述导电栓3063实现层间电连接。Specifically, the rewiring layer includes a dielectric layer 3061 and at least one layer of metal wiring 3062 and at least one layer of conductive plugs 3063 formed in the dielectric layer; the metal wiring 3062 passes through the conductive plug 3063 Realize electrical connection with the active element 301, the passive element 302, and the conductive column 305, and when the multilayer metal wiring 3062 is formed in the dielectric layer 3061, the multilayer metal wiring 3062 passes through the The conductive plug 3063 realizes the electrical connection between layers.
作为示例，所述金属连线3062的材料包括Cu、Al、Ag、Au、Sn、Ni、Ti、Ta中的一种或多种，或其他适合的导电金属材料。例如，所述金属连线3062可以为Cu线，制作Cu线的种子层可以为Ti/Cu层。形成所述金属连线182的方法可以包括电解镀、化学镀、丝网印刷中的一种或多种，或其他适合的金属沉积工艺。可以先通过激光钻孔、机械钻孔、反应离子刻蚀、纳米压印或其他适合的开孔方法在所述介电层3061内形成通孔，然后再所述通孔内填充金属材料即可形成所述导电栓3063；所述导电栓3063的材料可以为焊料或Cu，填充方法可以为电解镀、化学镀、丝网印刷、引线键合或其他适合在通孔中填充导电材料的方法。As an example, the material of the metal wiring 3062 includes one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials. For example, the metal connection 3062 may be a Cu wire, and the seed layer for making the Cu wire may be a Ti/Cu layer. The method of forming the metal connection 182 may include one or more of electrolytic plating, chemical plating, screen printing, or other suitable metal deposition processes. Through holes can be formed in the dielectric layer 3061 by laser drilling, mechanical drilling, reactive ion etching, nanoimprinting or other suitable opening methods, and then metal materials can be filled in the through holes. The conductive plug 3063 is formed; the material of the conductive plug 3063 can be solder or Cu, and the filling method can be electrolytic plating, electroless plating, screen printing, wire bonding or other methods suitable for filling conductive materials in through holes.
再请参阅图8，执行步骤S6：通过多个第一凸块结构4将所述用电芯片5与所述再布线层连接，实现所述用电芯片5与多条所述供电轨道的对接。Referring to FIG. 8 again, step S6 is performed: connecting the power chip 5 to the rewiring layer through a plurality of first bump structures 4, so as to realize the docking of the power chip 5 with a plurality of the power supply tracks .
具体的，所述用电芯片5包括但不限于专用集成电路裸芯(ASIC Die)。所述第一凸块结构4可以采用微凸块(mico-bump)或其他合适的凸块结构。Specifically, the power chip 5 includes but not limited to an application specific integrated circuit die (ASIC Die). The first bump structure 4 may adopt a micro-bump (mico-bump) or other suitable bump structures.
作为示例，可以采用超声键合、热压键合或普通的回流焊等工艺将所述用电芯片5经由多个第一凸块结构4焊接于所述再布线层306上。As an example, the power chip 5 may be welded to the rewiring layer 306 via a plurality of first bump structures 4 by ultrasonic bonding, thermocompression bonding or ordinary reflow soldering.
本实施例中，通过多个第一凸块结构将所述用电芯片与所述再布线层连接之后，还包括通过底部填充胶填满所述用电芯片5与所述在布线层306之间间隙的步骤。底部填充胶简单来说就是底部填充之义，常规定义是一种用化学胶水(主要成份是环氧树脂)对芯片进行底部填充，利用加热的固化形式，将芯片底部空隙大面积(一般覆盖80％以上)填满，从而达到加固的目的，增强封装结构的抗跌落性能。In this embodiment, after connecting the power chip 5 and the rewiring layer through a plurality of first bump structures, it also includes filling the gap between the power chip 5 and the wiring layer 306 with an underfill glue. gap between steps. Underfill glue is simply the meaning of underfill. The conventional definition is to fill the underfill of the chip with chemical glue (the main component is epoxy resin), and use the heating curing form to cover a large area of the bottom of the chip (generally covering 80 %) is filled, so as to achieve the purpose of reinforcement and enhance the anti-drop performance of the package structure.
作为示例，底部填充方法可以为毛细填充(capillary underfill)或成型填充(Molding UnderFill，简称MUF)。其中，毛细填充是利用毛细作用使得胶水迅速流过芯片底部，其毛细流动的最小空间是10um。这也符合了焊接工艺中焊盘和焊锡球之间的最低电气特性要求，因为胶水是不会流过低于4um的间隙，所以保障了焊接工艺的电气安全特性。As an example, the underfill method may be capillary underfill or molding underfill (MUF for short). Among them, the capillary filling is to use the capillary action to make the glue quickly flow through the bottom of the chip, and the minimum space for the capillary flow is 10um. This also meets the minimum electrical characteristic requirements between the pad and the solder ball in the soldering process, because the glue will not flow through the gap below 4um, so the electrical safety characteristics of the soldering process are guaranteed.
再请参阅图9，还包括通过塑封材料7将所述用电芯片5周围包裹的步骤。Please refer to FIG. 9 again, which further includes a step of wrapping the power chip 5 with a plastic encapsulation material 7 .
再请参阅图10，执行步骤S7：去除所述载体1及粘附层2，暴露出所述导电柱305下表面。Referring to FIG. 10 again, step S7 is performed: removing the carrier 1 and the adhesive layer 2 to expose the lower surface of the conductive pillar 305 .
具体的，可以采用机械研磨、化学抛光、刻蚀、紫外线剥离、机械剥离中的一种或多种去除所述载体1；优选地，本实施例中，可以通过去除所述粘附层2以剥离所述载体1。Specifically, one or more of mechanical grinding, chemical polishing, etching, ultraviolet stripping, and mechanical stripping can be used to remove the carrier 1; preferably, in this embodiment, the adhesive layer 2 can be removed to The carrier 1 is peeled off.
最后请参阅图11，执行步骤S8：形成多个与所述导电柱连接的第二凸块结构8。Finally, referring to FIG. 11 , step S8 is performed: forming a plurality of second bump structures 8 connected to the conductive pillars.
作为示例，所述第二凸块结构包括球栅阵列(Ball Grid Array，BGA)焊球。As an example, the second bump structure includes ball grid array (Ball Grid Array, BGA) solder balls.
具体的，所述封装结构可以通过所述第二凸块结构与封装基板结合，所述封装基板可以是PCB板(Printed Circuit Board，印制电路板)或其它合适的封装件。外部电源电压可以通过所述封装基板施加到所述功率传输芯片上，并通过所述功率传输芯片转换成用电芯片所需的多个电压，这些转换后的电压进而通过所述功率传输芯片中的多条供电轨道施加到用电芯片上。本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基板例如PCB板上的寄生电阻，从而提高功率传输效率，改善功率控制的响应时间，提高保真度。Specifically, the package structure may be combined with a package substrate through the second bump structure, and the package substrate may be a PCB (Printed Circuit Board, printed circuit board) or other suitable packages. The external power supply voltage can be applied to the power transmission chip through the packaging substrate, and converted into multiple voltages required by the power chip through the power transmission chip, and these converted voltages are then passed through the power transmission chip Multiple power supply rails are applied to the power chip. Since the packaging structure of the present invention integrates a power transmission chip containing passive components, it can eliminate parasitic resistance on a packaging substrate such as a PCB, thereby improving power transmission efficiency, improving power control response time, and improving fidelity.
综上所述，本发明提供了一种新的封装方法，使用三维芯片堆叠技术将用电芯片与功率传输芯片集成在一个封装结构内，具有以下有益效果：(1)采用现有的有源元件和无源元件形成有源2.5D中介板，然后通过微凸块或其它凸块结构将用电芯片集成在有源2.5D中介板上，得到三维堆叠结构；其中，所述用电芯片可以是专用集成电路(ApplicationSpecific Integrated Circuit，简称ASIC)。(2)在三维堆叠结构中，有源2.5D中介板作为功率传输功率芯片，紧密集成于在用电芯片下方，解决了功率传输的问题。(3)整个系统电路板的功率传输系统由所述功率传输芯片实现，所述功率传输芯片包括控制器、降压变换器(buck converter)、电容器(CAP(3T))，电感(L(2T))和电阻，从而消除了系统板上所有的无源元件。(4)所述功率传输芯片中的降压变换器可以产生成千上万低电压功率传输轨道(供电轨道)，这些低电压功率传输轨道通过微凸块对接用电芯片。(5)本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基板例如PCB板上的寄生电阻，从而提高了功率传输效率，改善了功率控制的响应时间。(6)通过减少压降和噪声提高了保真度，从而改善了响应时间。由于需要更少的设计余量，可以获得更好的保真度性能改善。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。To sum up, the present invention provides a new packaging method, using three-dimensional chip stacking technology to integrate the power consumption chip and the power transmission chip in a package structure, which has the following beneficial effects: (1) using the existing active Components and passive components form an active 2.5D interposer, and then integrate the power chip on the active 2.5D interposer through micro-bumps or other bump structures to obtain a three-dimensional stacked structure; wherein the power chip can It is an application specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC). (2) In the three-dimensional stacking structure, the active 2.5D interposer is used as the power transmission power chip, which is tightly integrated under the power chip, which solves the problem of power transmission. (3) The power transmission system of the entire system circuit board is realized by the power transmission chip, and the power transmission chip includes a controller, a step-down converter (buck converter), a capacitor (CAP (3T)), an inductor (L (2T) )) and resistors, thereby eliminating all passive components on the system board. (4) The step-down converter in the power transmission chip can generate tens of thousands of low-voltage power transmission tracks (power supply tracks), and these low-voltage power transmission tracks are connected to the power chip through micro-bumps. (5) Since the package structure of the present invention integrates a power transmission chip containing passive components, it can eliminate parasitic resistance on a package substrate such as a PCB, thereby improving power transmission efficiency and improving the response time of power control. (6) Increased fidelity by reducing voltage drop and noise, resulting in improved response time. Better fidelity performance improvements can be obtained as less design margin is required. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.
Claims (10)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710172468.2A CN106887393B (en) | 2017-03-22 | 2017-03-22 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
| PCT/CN2017/095419 WO2018171100A1 (en) | 2017-03-22 | 2017-08-01 | Encapsulation method for encapsulation structure with integrated power transmission chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710172468.2A CN106887393B (en) | 2017-03-22 | 2017-03-22 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106887393A true CN106887393A (en) | 2017-06-23 |
| CN106887393B CN106887393B (en) | 2018-10-19 |
Family
ID=59180984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710172468.2A Active CN106887393B (en) | 2017-03-22 | 2017-03-22 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106887393B (en) |
| WO (1) | WO2018171100A1 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133931A (en) * | 2018-01-29 | 2018-06-08 | 安徽安努奇科技有限公司 | A kind of modular structure and preparation method thereof |
| WO2018171100A1 (en) * | 2017-03-22 | 2018-09-27 | 中芯长电半导体（江阴）有限公司 | Encapsulation method for encapsulation structure with integrated power transmission chip |
| WO2019144574A1 (en) * | 2018-01-29 | 2019-08-01 | 安徽安努奇科技有限公司 | Module structure and manufacturing method therefor |
| CN112289743A (en) * | 2020-11-20 | 2021-01-29 | 中芯长电半导体（江阴）有限公司 | A wafer system-level fan-out package structure and method of making the same |
| WO2021081943A1 (en) * | 2019-10-31 | 2021-05-06 | 华为技术有限公司 | Chip stack packaging structure, packaging method thereof and electronic device |
| WO2021174395A1 (en) * | 2020-03-02 | 2021-09-10 | 华为技术有限公司 | Encapsulation structure and method for manufacturing encapsulation structure |
| CN113990843A (en) * | 2021-10-25 | 2022-01-28 | 上海壁仞智能科技有限公司 | Chip set and method of manufacturing the same |
| US11315831B2 (en) | 2019-07-22 | 2022-04-26 | International Business Machines Corporation | Dual redistribution layer structure |
| CN116153795A (en) * | 2023-04-20 | 2023-05-23 | 广东赛昉科技有限公司 | Multi-chip packaging method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1722412A (en) * | 2004-01-07 | 2006-01-18 | 三星电子株式会社 | Dimensional packaged circuit board and the encapsulation and the method thereof that comprise dimensional packaged circuit board |
| CN102157393A (en) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | Fan-out high-density packaging method |
| CN102157456A (en) * | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | Three-dimensional system level packaging method |
| CN102176418A (en) * | 2011-03-22 | 2011-09-07 | 南通富士通微电子股份有限公司 | Fan-out system in package (SIP) method |
| US20160372446A1 (en) * | 2015-06-18 | 2016-12-22 | Qualcomm Incorporated | Low profile integrated circuit (ic) package comprising a plurality of dies |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106887393B (en) * | 2017-03-22 | 2018-10-19 | 中芯长电半导体（江阴）有限公司 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
-
2017
- 2017-03-22 CN CN201710172468.2A patent/CN106887393B/en active Active
- 2017-08-01 WO PCT/CN2017/095419 patent/WO2018171100A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1722412A (en) * | 2004-01-07 | 2006-01-18 | 三星电子株式会社 | Dimensional packaged circuit board and the encapsulation and the method thereof that comprise dimensional packaged circuit board |
| CN102157393A (en) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | Fan-out high-density packaging method |
| CN102176418A (en) * | 2011-03-22 | 2011-09-07 | 南通富士通微电子股份有限公司 | Fan-out system in package (SIP) method |
| CN102157456A (en) * | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | Three-dimensional system level packaging method |
| US20160372446A1 (en) * | 2015-06-18 | 2016-12-22 | Qualcomm Incorporated | Low profile integrated circuit (ic) package comprising a plurality of dies |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018171100A1 (en) * | 2017-03-22 | 2018-09-27 | 中芯长电半导体（江阴）有限公司 | Encapsulation method for encapsulation structure with integrated power transmission chip |
| WO2019144574A1 (en) * | 2018-01-29 | 2019-08-01 | 安徽安努奇科技有限公司 | Module structure and manufacturing method therefor |
| CN108133931A (en) * | 2018-01-29 | 2018-06-08 | 安徽安努奇科技有限公司 | A kind of modular structure and preparation method thereof |
| CN108133931B (en) * | 2018-01-29 | 2023-11-07 | 安徽安努奇科技有限公司 | Module structure and manufacturing method thereof |
| US11387182B2 (en) | 2018-01-29 | 2022-07-12 | Anhui Anuki Technologies Co., Ltd. | Module structure and method for manufacturing the module structure |
| US11315831B2 (en) | 2019-07-22 | 2022-04-26 | International Business Machines Corporation | Dual redistribution layer structure |
| CN114631179B (en) * | 2019-10-31 | 2023-09-22 | 华为技术有限公司 | Chip stacking and packaging structure, packaging method thereof and electronic equipment |
| WO2021081943A1 (en) * | 2019-10-31 | 2021-05-06 | 华为技术有限公司 | Chip stack packaging structure, packaging method thereof and electronic device |
| CN114631179A (en) * | 2019-10-31 | 2022-06-14 | 华为技术有限公司 | Chip stacking and packaging structure, packaging method thereof and electronic equipment |
| WO2021174395A1 (en) * | 2020-03-02 | 2021-09-10 | 华为技术有限公司 | Encapsulation structure and method for manufacturing encapsulation structure |
| CN115104179A (en) * | 2020-03-02 | 2022-09-23 | 华为技术有限公司 | Packaging structure and manufacturing method thereof |
| CN112289743A (en) * | 2020-11-20 | 2021-01-29 | 中芯长电半导体（江阴）有限公司 | A wafer system-level fan-out package structure and method of making the same |
| CN113990843A (en) * | 2021-10-25 | 2022-01-28 | 上海壁仞智能科技有限公司 | Chip set and method of manufacturing the same |
| CN116153795A (en) * | 2023-04-20 | 2023-05-23 | 广东赛昉科技有限公司 | Multi-chip packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018171100A1 (en) | 2018-09-27 |
| CN106887393B (en) | 2018-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106887393B (en) | It is integrated with the packaging method of the encapsulating structure of power transmission chip | |
| WO2018171099A1 (en) | Encapsulation method for encapsulation structure with integrated power transmission chip | |
| CN111370387A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| CN107104090B (en) | Rewiring layer, packaging structure with same and preparation method | |
| CN111370385A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| CN105070671A (en) | Chip encapsulation method | |
| CN212084995U (en) | Wafer level package structure | |
| TW201203400A (en) | Semiconductor device and method of forming perforated opening in bottom substrate of flipchip pop assembly to reduce bleeding of underfill material | |
| CN111370386A (en) | Fan-out system-in-package structure and method of making the same | |
| CN106847710B (en) | It is integrated with the packaging method of the packaging part of power transmission system | |
| CN110634838A (en) | Ultrathin fan-out type packaging structure and manufacturing method thereof | |
| CN110085973A (en) | Antenna packages structure and packaging method | |
| US11756871B2 (en) | Fan-out packaging structure and method | |
| CN211480019U (en) | Fan-out type system-in-package structure | |
| CN112289743A (en) | A wafer system-level fan-out package structure and method of making the same | |
| CN114188226A (en) | Fan-out packaging structure and packaging method | |
| CN114188225A (en) | Fan-out packaging structure and packaging method | |
| CN205542764U (en) | Packaging structure and interposer thereof | |
| CN107452728A (en) | The method for packing of integrated image sensor chip and logic chip | |
| CN106898557B (en) | It is integrated with the packaging method of the packaging part of power transmission system | |
| CN107195625A (en) | Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof | |
| CN114188227B (en) | Fan-out packaging structure and packaging method | |
| CN211480020U (en) | Fan-out type system-in-package structure | |
| WO2018129907A1 (en) | Packaging piece for integrated power supply system, and packaging method | |
| WO2018129906A1 (en) | Package method for integrated power supply system packaging piece |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |