CN106876871A - Fabrication Method of SiGe Base Frequency Reconfigurable Sleeve Dipole Antenna - Google Patents

Abstract

The invention relates to a preparation method of a SiGe base frequency reconfigurable sleeve dipole antenna. The method comprises: selecting a SiGeOI substrate; making a plurality of SPiN diode strings on the SiGeOI substrate according to the structure of a sleeve dipole antenna; making a DC bias line to connect the SPiN diode strings and a DC bias power supply; making an SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve; making a coaxial feeder to connect the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve to finally form a sleeve dipole antenna. The sleeve dipole antenna of the embodiment of the present invention controls the conduction of the SPiN diode through the metal DC bias line to form the adjustable length of the plasma antenna arm and the sleeve, thereby realizing the reconfigurable antenna operating frequency, which has the advantages of easy integration, It can be invisible and the frequency can be quickly changed.

Description

Fabrication Method of SiGe Base Frequency Reconfigurable Sleeve Dipole Antenna

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a preparation method of a SiGe-based frequency reconfigurable sleeve dipole antenna.

Background technique

Today, with the rapid development of antenna technology, the traditional sleeve monopole antenna is widely used in vehicle, shipboard and remote sensing due to its wide frequency band, high gain, simple structure, easy feeding, longitudinal size, omnidirectional and many other advantages. and other communication systems. However, the electrical characteristics of the commonly used sleeve monopole antenna not only depend on the sleeve structure, but also have a great relationship with the ground, which makes it difficult to meet the requirements of broadband and miniaturization for elevated antennas in shipboard communication engineering .

The sleeve dipole antenna is a dipole antenna formed by adding a coaxial metal sleeve to the antenna radiator. While thickening the vibrator, the sleeve antenna introduces asymmetrical feeding, which plays a similar role in the staggered tuning in the circuit, thereby broadening the impedance bandwidth more effectively. At the same time, the concept of reconfigurable antennas has been valued and developed in order to break through the fact that the fixed performance of traditional antennas is difficult to meet diverse system requirements and complex and changeable application environments. Reconfigurable microstrip antennas have become a hotspot in the research of reconfigurable antennas because of their small size and low profile. Based on this, the reconfigurable sleeve dipole antenna has become one of the products with better prospects in the current market.

With the development of microelectronics technology, the use of semiconductor materials to make reconfigurable antennas has become the trend of current technology development. Therefore, how to design a frequency-reconfigurable sleeve dipole antenna with a simple structure and easy implementation by using semiconductor process technology is an urgent problem to be solved by those skilled in the art.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a SPiN diode reconfigurable plasma sleeve dipole antenna. The technical problem to be solved in the present invention is realized through the following technical solutions:

An embodiment of the present invention provides a method for preparing a SiGe base frequency reconfigurable sleeve dipole antenna, wherein the antenna includes a semiconductor substrate, an SPiN diode antenna arm, a first SPiN diode sleeve, a second SPiN A diode sleeve, a coaxial feeder, and a DC bias line; wherein, the preparation method includes:

Select SiGeOI substrate;

making a plurality of SPiN diode strings on the SiGeOI substrate according to the structure of the sleeve dipole antenna;

making a DC bias line to connect the SPiN diode strings to a DC bias power supply;

making the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve;

The coaxial feeder is made to connect the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve, finally forming the sleeve dipole antenna.

In one embodiment of the present invention, a plurality of SPiN diode strings are fabricated on the SiGeOI substrate according to the structure of the sleeve dipole antenna, including:

(a) setting an isolation region on the SiGeOI substrate according to the structure of the sleeve dipole antenna;

(b) etching the SiGeOI substrate to form a P-type trench and an N-type trench;

(c) forming a first P-type active region and a first N-type active region by ion implantation in the P-type trench and the N-type trench;

(d) filling the P-type trench and the N-type trench, and forming a second P-type active region and a second N-type active region in the top layer SiGe of the SiGeOI substrate by ion implantation;

(e) forming leads on the SiGeOI substrate to form a lateral SPiN diode;

(f) Photoetching the PAD to realize serial connection of a plurality of lateral SPiN diodes to form a plurality of SPiN diode strings.

In one embodiment of the invention, step (a) includes:

(a1) forming a first protective layer on the surface of the SiGeOI substrate;

(a2) forming a first isolation region pattern on the first protective layer by using a photolithography process;

(a3) Etching the first protection layer and the SiGeOI substrate at a designated position of the first isolation region pattern by a dry etching process to form an isolation trench, and the depth of the isolation trench is greater than or equal to the specified position Describe the thickness of the top layer SiGe of SiGeOI substrate;

(a4) Filling the isolation trench to form the isolation region.

In one embodiment of the invention, step (c) comprises:

(c1) oxidizing the P-type trench and the N-type trench to form an oxide layer on the inner walls of the P-type trench and the N-type trench;

(c2) etching the oxide layer on the inner wall of the P-type trench and the N-type trench by a wet etching process to complete the planarization of the inner wall of the P-type trench and the N-type trench;

(c3) performing ion implantation on the P-type trench and the N-type trench to form the first P-type active region and the first N-type active region.

In one embodiment of the present invention, the first N-type active region is a region whose depth is less than 1 micron from the sidewall and bottom of the N-type trench along the direction of ion diffusion, and the first P-type active region It is a region whose depth is less than 1 micron from the side wall and bottom of the P-type trench along the direction of ion diffusion.

In one embodiment of the invention, step (d) includes:

(d1) filling the P-type trench and the N-type trench with polysilicon to form a P+ region (27) and an N+ region (26);

(d2) After planarizing the SiGeOI substrate, forming a polysilicon layer on the SiGeOI substrate;

(d3) photoetching the polysilicon layer, and implanting P-type impurities and N-type impurities into the P+ region (27) and the N+ region (26) to form a second P-type active layer by implanting gelled ions. region and the second N-type active region and simultaneously form a P-type contact region and an N-type contact region;

(d4)) removing the photoresist;

(d5) Removing the polysilicon except for the P-type electrode and the N-type electrode by wet etching.

In one embodiment of the invention, step (e) includes:

growing silicon dioxide on the SiGeOI substrate;

activating impurities in the P-type active region and the N-type active region by an annealing process;

Lead holes are photolithographically etched in the P+ region (27) and the N+ region (26) to form leads.

In one embodiment of the present invention, preparing a DC bias line includes:

The DC bias line is formed by using copper, aluminum or highly doped polysilicon by using a CVD process.

In one embodiment of the present invention, the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve all include the same number of the SPiN diode strings connected in series, and The SPiN diode strings at corresponding positions include the same number of lateral SPiN diodes.

In one embodiment of the present invention, making the coaxial feeder includes:

The inner core wire of the coaxial feeder is connected to the SPiN diode antenna arm and the outer conductor of the coaxial feeder is connected to the first SPiN diode sleeve and the second SPiN diode sleeve.

Compared with prior art, the beneficial effect of the present invention:

The frequency reconfigurable sleeve dipole antenna based on SiGe-based SPiN diodes prepared by the present invention has small volume, low profile, simple structure, easy processing, no complicated feed source structure, fast frequency jump, and the antenna will turn off when the antenna is turned off. In the state of electromagnetic wave stealth, it can be used in various frequency hopping stations or equipment; because all its components are on the side of the semiconductor substrate, it is a planar structure, easy to form an array, and can be used as the basic component of a phased array antenna.

Description of drawings

Fig. 1 is a schematic structural diagram of a SiGe base frequency reconfigurable sleeve dipole antenna provided by an embodiment of the present invention;

2 is a schematic diagram of a method for preparing a SiGe-based frequency reconfigurable sleeve dipole antenna provided by an embodiment of the present invention;

3 is a schematic diagram of a method for preparing an SPiN diode string provided by an embodiment of the present invention;

4 is a schematic structural diagram of a lateral SPiN diode provided by an embodiment of the present invention;

5 is a schematic structural diagram of an SPiN diode string provided by an embodiment of the present invention; and

6a-6s are schematic diagrams of a method for fabricating a lateral SPiN diode according to an embodiment of the present invention.

detailed description

The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.

Embodiment one

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a SiGe fundamental frequency reconfigurable sleeve dipole antenna provided by an embodiment of the present invention. The antenna includes a semiconductor substrate 1, an SPiN diode antenna arm 2, a first SPiN diode sleeve 3, a second SPiN diode sleeve 4, a coaxial feeder 5, and DC bias lines 9, 10, 11, 12, 13, 14 , 15, 16, 17, 18, 19;

The SPiN diode antenna arm 2, the first SPiN diode sleeve 3, the second SPiN diode sleeve 4, and the DC bias lines 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 are all fabricated on the semiconductor substrate 1; the SPiN diode antenna arm 2, the first SPiN diode sleeve 3 and the second SPiN diode sleeve 4 pass through the coaxial feeder 5 connection, the inner core wire 7 of the coaxial feeder 5 is connected to the SPiN diode antenna arm 2 and the outer conductor 8 of the coaxial feeder 5 is connected to the first SPiN diode sleeve 3 and the second SPiN diode sleeve cartridge 4;

Wherein, the SPiN diode antenna arm 2 includes SPiN diodes w1, w2, w3 connected in series, the first SPiN diode sleeve 3 includes SPiN diodes w4, w5, w6 connected in series, and the second SPiN diode The sleeve 4 includes SPiN diodes w7, w8, w9 connected in series, and each of the SPiN diode strings w1, w2, w3, w4, w5, w6, w7, w8, w9 passes through the corresponding DC bias line 9 , 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 are connected to the DC bias supply.

The antenna controls the length of the plasma antenna arm and the sleeve formed when the SPiN diode is turned on through the metal DC bias line to realize the reconfigurability of the antenna operating frequency. features.

Please refer to FIG. 2 , which is a schematic diagram of a method for preparing a SiGe fundamental frequency reconfigurable sleeve dipole antenna provided by an embodiment of the present invention. The preparation method of the antenna may include:

Select SiGeOI substrate;

making a plurality of SPiN diode strings on the SiGeOI substrate according to the structure of the sleeve dipole antenna;

making a DC bias line to connect the SPiN diode strings to a DC bias power supply;

making the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve;

The coaxial feeder is made to connect the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve, finally forming the sleeve dipole antenna.

Among them, the reason for using the SiGeOI substrate is that the solid-state plasma antenna needs good microwave characteristics, and the solid-state plasma pin diode needs to have good isolation characteristics and the ability to limit the carrier, that is, the solid-state plasma, in order to meet this requirement. The SiGeOI substrate is preferably used as a solid-state plasma pin diode because it has a pin isolation region that can be easily formed with the isolation groove, and silicon dioxide (SiO ₂ ) can also confine carriers, that is, a solid-state plasma, in the top layer of silicon. the substrate. Moreover, the carrier mobility of the SiGe material is relatively large, so the performance of the device can be improved.

Wherein, preparing the DC bias line may include:

The DC bias line is formed by using copper, aluminum or highly doped polysilicon by using a CVD process.

Preferably, making the coaxial feeder may include:

The inner core wire of the coaxial feeder is connected to the SPiN diode antenna arm and the outer conductor of the coaxial feeder is connected to the first SPiN diode sleeve and the second SPiN diode sleeve.

It should be noted that the above-mentioned steps do not have a specific production sequence, and can be adjusted according to actual conditions in actual preparation, which is not limited here.

In this embodiment, both the SPiN diode antenna arm and the SPiN diode sleeve include N sections of SPiN diode strings, and the range of N is N≧2. Moreover, the number of SPiN diodes in each segment of the SPiN diode string can be selected according to actual needs, and there is no limitation here.

Preferably, N=3. That is, the SPiN diode antenna arm 2 includes three sections of SPiN diode strings w1, w2, w3. The first SPiN diode sleeve 3 and the second SPiN diode sleeve 4 respectively include three sections of SPiN diode strings, wherein the first SPiN diode sleeve 3 includes three sections of SPiN diode strings w4, w5, w6, The second SPiN diode sleeve 4 includes three sections of SPiN diode strings w7, w8, w9. And the lengths of the SPiN diode string w1, the SPiN diode string w6, and the SPiN diode string w9 are equal, the lengths of the SPiN diode string w2, the SPiN diode string w5, and the SPiN diode string w8 are equal, so The lengths of the SPiN diode string w3, the SPiN diode string w4, and the SPiN diode string w7 are equal. Each SPiN diode string also has a DC bias line externally connected to the positive voltage.

The antenna prepared in this embodiment has a frequency reconfigurable dipole antenna with small volume, low profile, simple structure, easy processing, no complicated feed source structure, fast frequency jump, and the antenna will be in an electromagnetic stealth state when it is turned off. It can be used in various frequency hopping radio stations or equipment; because all its components are on the side of the semiconductor substrate, it is a planar structure, easy to form an array, and can be used as the basic component of a phased array antenna.

Embodiment two

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of a method for preparing an SPiN diode string provided by an embodiment of the present invention. The preparation method may comprise the steps of:

(a) setting an isolation region on the SiGeOI substrate according to the structure of the sleeve dipole antenna;

(b) etching the SiGeOI substrate to form a P-type trench and an N-type trench;

(c) forming a first P-type active region and a first N-type active region by ion implantation in the P-type trench and the N-type trench;

(d) filling the P-type trench and the N-type trench, and forming a second P-type active region and a second N-type active region in the top layer SiGe of the SiGeOI substrate by ion implantation;

(e) forming leads on the SiGeOI substrate to form a lateral SPiN diode;

(f) Photoetching the PAD to realize serial connection of a plurality of lateral SPiN diodes to form a plurality of SPiN diode strings.

Wherein, step (a) may include:

(a1) forming a first protective layer on the surface of the SiGeOI substrate;

(a2) forming a first isolation region pattern on the first protective layer by using a photolithography process;

(a3) Etching the first protection layer and the SiGeOI substrate at a designated position of the first isolation region pattern by a dry etching process to form an isolation trench, and the depth of the isolation trench is greater than or equal to the specified position Describe the thickness of the top layer SiGe of SiGeOI substrate;

(a4) Filling the isolation trench to form the isolation region.

Wherein, step (c) may comprise:

(c1) oxidizing the P-type trench and the N-type trench to form an oxide layer on the inner walls of the P-type trench and the N-type trench;

(c2) using a wet etching process to etch the oxide layer on the inner wall of the P-type trench and the N-type trench to complete the planarization of the inner wall of the P-type trench and the N-type trench; specifically , the planarization process can adopt the following steps: oxidize the P-type trench and the N-type trench to form an oxide layer on the inner wall of the P-type trench and the N-type trench; use a wet etching process to etch the P-type trench and the N-type trench The oxide layer on the inner wall of the P-type trench is used to complete the planarization of the inner wall of the P-type trench and the N-type trench. The advantage of doing this is that it can prevent the protrusion of the trench side wall from forming an electric field concentration area, causing breakdown of the Pi and Ni junctions.

(c3) performing ion implantation on the P-type trench and the N-type trench to form the first P-type active region and the first N-type active region. The first N-type active region is a region with a depth of less than 1 micron from the side wall and bottom of the N-type trench along the direction of ion diffusion, and the first P-type active region is a region farther from the P The area where the depth of the sidewall and bottom of the type trench is less than 1 micron.

The purpose of forming the first active region is to form a layer of uniform heavily doped region on the side wall of the trench, which is the heavily doped region in the junction of Pi and Ni, and the formation of the first active region has The following advantages are illustrated by filling polysilicon in the groove as an example. First, it avoids the uncertainty of the performance caused by the heterojunction between polysilicon and Si and the junction of Pi and Ni. Second, it can Utilize the characteristics that the diffusion speed of impurities in polysilicon is faster than that in Si, further diffuse to P and N regions, and further increase the doping concentration of P and N regions; third, this prevents the inappropriate growth of polysilicon during the polysilicon process. Voids are formed between the polysilicon and the groove wall caused by homogeneity, and the voids will cause poor contact between the polysilicon and the sidewall, affecting device performance.

Wherein, step (d) may comprise:

(d1) filling the P-type trench and the N-type trench with polysilicon to form a P+ region (27) and an N+ region (26);

(d2) After planarizing the SiGeOI substrate, forming a polysilicon layer on the SiGeOI substrate;

(d3) photoetching the polysilicon layer, and implanting P-type impurities and N-type impurities into the P+ region (27) and the N+ region (26) to form a second P-type active layer by implanting gelled ions. region and the second N-type active region and simultaneously form a P-type contact region and an N-type contact region;

(d4)) removing the photoresist;

(d5) Removing the polysilicon except for the P-type electrode and the N-type electrode by wet etching.

Wherein, step (e) may include:

(e1) generating silicon dioxide on the SiGeOI substrate;

(e2) activating impurities in the P-type active region and the N-type active region by an annealing process;

(e3) Lithographically etching wire holes in the P+ region (27) and the N+ region (26) to form wires.

Please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a schematic structural diagram of a lateral SPiN diode provided by an embodiment of the present invention; FIG. 5 is a schematic structural diagram of an SPiN diode string provided by an embodiment of the present invention. Each SPiN diode string includes a plurality of lateral SPiN diodes, and these SPiN diodes are connected in series. The lateral SPiN diode in the SPiN diode string is composed of a P+ region 27, an N+ region 26 and an intrinsic region 22, the metal contact region 23 is located at the P+ region 27, the metal contact region 24 is located at the N+ region 26, and is in the SPiN diode string The metal contact region 23 of the lateral SPiN diode at one end is connected to the positive pole of the DC bias, and the metal contact region 24 of the lateral SPiN diode at the other end of the SPiN diode string is connected to the negative pole of the DC bias. By applying a DC voltage, the entire SPiN All lateral SPiN diodes in the diode string are in a forward conduction state.

Embodiment three

Please refer to FIG. 6a-FIG. 6s. FIG. 6a-FIG. 6s are schematic diagrams of a method for fabricating a lateral SPiN diode according to an embodiment of the present invention. In this embodiment, on the basis of the above-mentioned embodiments, the preparation of the SPiN diode is described in detail by taking the preparation of a SiGeOI-based SPiN diode (solid-state plasma PiN diode) with a plasma region length of 100 μm as an example, and the specific steps are as follows:

Step 1, substrate material preparation steps:

(1a) As shown in Figure 6a, select (100) crystal orientation, doping type is p-type, SiGeOI substrate sheet 101 with doping concentration of 10 ¹⁴ cm ^-3 , and the thickness of the top layer SiGe is 50 μm;

(1b) As shown in Figure 6b, the first _SiO2 layer 201 with a thickness of 40nm is deposited on the SiGeOI substrate by chemical vapor deposition (Chemical vapor deposition, CVD for short); , depositing a first Si ₃ N ₄ /SiN layer 202 with a thickness of 2 μm on the SiO ₂ layer;

Step 2, isolation preparation steps:

(2a) As shown in FIG. 6c, an isolation region is formed on the protective layer by a photolithography process, and the first Si ₃ N ₄ /SiN layer 202 in the isolation region is wet-etched to form an isolation region pattern; dry etching is used, forming a deep isolation trench 301 with a width of 5 μm and a depth of 50 μm in the isolation region;

(2b) As shown in FIG. 6d , deposit SiO ₂ 401 by CVD to fill up the deep isolation trench;

(2c) As shown in FIG. 6e, the first Si ₃ N ₄ /SiN layer 202 and the first SiO ₂ layer 201 on the surface are removed by using a chemical mechanical polishing (CMP) method to make the surface of the SiGeOI substrate smooth;

Step 3, preparation steps of deep grooves in P and N regions:

(3a) As shown in Figure 6f, two layers of materials are continuously deposited on the substrate by CVD method, the first layer is a second SiO ₂ layer 601 with a thickness of 300nm, and the second layer is a second Si ₃ N layer with a thickness of 600nm ₄ /SiN layer 602;

(3b) As shown in Figure 6g, photolithography of deep grooves in the P and N regions, wet etching of the second Si ₃ N ₄ /SiN layer 602 and the second SiO ₂ layer 601 in the P and N regions to form patterns in the P and N regions ;Use dry etching to form a deep groove 701 with a width of 4 μm and a depth of 5 μm in the P and N regions, and the length of the grooves in the P and N regions is determined according to the application in the prepared antenna;

(3c) As shown in FIG. 6h, at 850° C. for 10 minutes at high temperature, an oxide layer 801 is formed on the inner wall of the oxidation tank;

(3d) As shown in FIG. 6i , the oxide layer 801 on the inner walls of the grooves in the P and N regions is removed by a wet etching process, so that the inner walls of the grooves in the P and N regions are flat.

Step 4, P, N contact region preparation steps:

(4a) As shown in Figure 6j, the deep groove in the P region is photolithographically, and p ⁺ implantation is performed on the side wall of the groove in the P region by the method of ion implantation with glue, so that a thin p ⁺ active region 1001 is formed on the side wall, and the concentration reaches 0.5×10 ²⁰ cm ^-3 , remove the photoresist;

(4b) Lithograph the deep groove in the N region, and use the method of ion implantation with glue to carry out n ⁺ implantation on the side wall of the N region groove, so that a thin n ⁺ active region 1002 is formed on the side wall, and the concentration reaches 0.5×10 ²⁰ cm ^{- 3} , remove the photoresist;

(4c) As shown in FIG. 6k, adopt CVD method to deposit polysilicon 1101 in the grooves of P and N regions, and fill the grooves;

(4d) As shown in FIG. 6l, CMP is used to remove the surface polysilicon 1101 and the second Si ₃ N ₄ /SiN layer 602 to make the surface smooth;

(4e) As shown in FIG. 6m, a layer of polysilicon 1301 is deposited on the surface by CVD with a thickness of 200-500nm;

(4f) As shown in Figure 6n, photoresist the active region of the P region, and perform p ⁺ implantation by using the ion implantation method with glue, so that the doping concentration of the active region of the P region reaches 0.5×10 ²⁰ cm ^-3 , and remove the photoresist , forming a P-contact 1401;

(4g) Photoetching the active region of the N region, using glued ion implantation to perform n ⁺ implantation, so that the doping concentration of the active region of the N region is 0.5×10 ²⁰ cm ^-3 , removing the photoresist, and forming an N contact 1402;

(4h) As shown in FIG. 6o, wet etching is used to etch away the polysilicon 1301 outside the P and N contact regions to form P and N contact regions;

(4i) As shown in FIG. 6p, deposit SiO ₂ 1601 on the surface by CVD with a thickness of 800nm;

(4j) annealing at 1000°C for 1 minute to activate the ion-implanted impurities and advance the impurities in the polycrystalline germanium;

Step 5, forming the PIN diode steps:

(5a) As shown in FIG. 6q, photolithographic lead holes 1701 are formed in the P and N contact areas;

(5b) As shown in Figure 6r, metal is sputtered on the surface of the substrate, a metal silicide 1801 is formed at 750° C., and the metal on the surface is etched away;

(5c) sputtering metal on the surface of the substrate, and photoetching leads;

(5d) As shown in FIG. 6s , deposit Si ₃ N ₄ /SiN to form a passivation layer 1901 , photoetch PAD, and form a PIN diode as a material for preparing a solid plasma antenna.

In this embodiment, the above-mentioned various process parameters are all examples, and the transformations made according to the conventional means of those skilled in the art are within the protection scope of the present application.

The SPiN diode used in the solid-state plasma reconfigurable antenna prepared by the present invention, firstly, the SiGe material used improves the solid-state plasma concentration of the SPiN diode due to its high mobility and large carrier lifetime characteristics; in addition, The P region and N region of the SPiN diode adopt the polysilicon damascene process based on etching deep groove etching, which can provide sudden junction pi and ni junctions, and can effectively increase the junction depth of pi and ni junctions, making solid The controllability of plasma concentration and distribution is enhanced, which is conducive to the preparation of high-performance plasma antennas; again, the SPiN diodes used in solid-state plasma reconfigurable antennas prepared by the present invention adopt a deep groove dielectric based on etching The isolation process effectively increases the breakdown voltage of the device and suppresses the influence of leakage current on the performance of the device.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. a kind of preparation method of SiGe base frequency reconfigurable sleeve dipole antenna, it is characterized in that, described antenna comprises SiGeOI substrate, SPiN diode antenna arm, the first SPiN diode sleeve, the second SPiN diode sleeve , coaxial feeder, DC bias line; wherein, the preparation method includes: Select SiGeOI substrate; making a plurality of SPiN diode strings on the SiGeOI substrate according to the structure of the sleeve dipole antenna; making a DC bias line to connect the SPiN diode strings to a DC bias power supply; making the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve; The coaxial feeder is made to connect the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve, finally forming the sleeve dipole antenna. 2. preparation method according to claim 2, make a plurality of SPiN diode strings according to the structure of described sleeve dipole antenna on described SiGeOI substrate, comprising: (a) setting an isolation region on the SiGeOI substrate according to the structure of the sleeve dipole antenna; (b) etching the SiGeOI substrate to form a P-type trench and an N-type trench; (c) forming a first P-type active region and a first N-type active region by ion implantation in the P-type trench and the N-type trench; (d) filling the P-type trench and the N-type trench, and forming a second P-type active region and a second N-type active region in the top layer SiGe of the SiGeOI substrate by ion implantation; (e) forming leads on the SiGeOI substrate to form a lateral SPiN diode; (f) Photoetching the PAD to realize serial connection of a plurality of lateral SPiN diodes to form a plurality of SPiN diode strings. 3. preparation method according to claim 2, is characterized in that, step (a) comprises: (a1) forming a first protective layer on the surface of the SiGeOI substrate; (a2) forming a first isolation region pattern on the first protective layer by using a photolithography process; (a3) Etching the first protection layer and the SiGeOI substrate at a designated position of the first isolation region pattern by a dry etching process to form an isolation trench, and the depth of the isolation trench is greater than or equal to the specified position Describe the thickness of the top layer SiGe of SiGeOI substrate; (a4) Filling the isolation trench to form the isolation region. 4. preparation method according to claim 2, is characterized in that, step (c) comprises: (c1) oxidizing the P-type trench and the N-type trench to form an oxide layer on the inner walls of the P-type trench and the N-type trench; (c2) etching the oxide layer on the inner wall of the P-type trench and the N-type trench by a wet etching process to complete the planarization of the inner wall of the P-type trench and the N-type trench; (c3) performing ion implantation on the P-type trench and the N-type trench to form the first P-type active region and the first N-type active region. 5. The preparation method according to claim 3, wherein the first N-type active region is a region with a depth of less than 1 micron from the sidewall and bottom of the N-type trench along the direction of ion diffusion, and the The first P-type active region is a region whose depth is less than 1 micron from the sidewall and bottom of the P-type trench along the direction of ion diffusion. 6. the preparation method according to claim 3, is characterized in that, step (d), comprises: (d1) filling the P-type trench and the N-type trench with polysilicon to form a P+ region (27) and an N+ region (26); (d2) After planarizing the SiGeOI substrate, forming a polysilicon layer on the SiGeOI substrate; (d3) photoetching the polysilicon layer, and implanting P-type impurities and N-type impurities into the P+ region (27) and the N+ region (26) to form a second P-type active layer by implanting gelled ions. region and the second N-type active region and simultaneously form a P-type contact region and an N-type contact region; (d4)) removing the photoresist; (d5) Removing the polysilicon except for the P-type electrode and the N-type electrode by wet etching. 7. preparation method according to claim 2, is characterized in that, step (e) comprises: growing silicon dioxide on the SiGeOI substrate; activating impurities in the P-type active region and the N-type active region by an annealing process; Lead holes are photolithographically etched in the P+ region (27) and the N+ region (26) to form leads. 8. The preparation method according to claim 1, wherein preparing a DC bias line comprises: The DC bias line is formed by using copper, aluminum or highly doped polysilicon by using a CVD process. 9. The preparation method according to claim 1, characterized in that, the SPiN diode antenna arm, the first SPiN diode sleeve and the second SPiN diode sleeve all include the same number of serially connected The SPiN diode strings, and the corresponding SPiN diode strings include the same number of lateral SPiN diodes. 10. The preparation method according to claim 1, wherein making the coaxial feeder comprises: The inner core wire of the coaxial feeder is connected to the SPiN diode antenna arm and the outer conductor of the coaxial feeder is connected to the first SPiN diode sleeve and the second SPiN diode sleeve.