CN106816686A - The preparation method of the restructural dipole antenna based on heterogeneous SiGeSPiN diodes - Google Patents

Abstract

The invention relates to a preparation method of a reconfigurable dipole antenna based on a heterogeneous SiGeSPiN diode, wherein the reconfigurable dipole antenna includes: a SiGeOI substrate, a first SPiN diode antenna arm, a second SPiN diode An antenna arm, a coaxial feeder line and a DC bias line; the antenna preparation method includes: selecting a SiGeOI substrate of a certain crystal orientation; making a plurality of SPIN diodes on the SiGeOI substrate and connecting them end to end to form a SPIN diode string; The SPiN diode antenna arm, making a DC bias line; making a coaxial feeder on the SPIN diode antenna arm; and connecting the first SPiN diode antenna arm and the second SPiN diode antenna arm to form the reconfigurable dipole The sub-antenna, the reconfigurable dipole antenna prepared by the present invention, controls the conduction of the SPiN diode through the metal DC bias line to form an adjustable length of the plasma antenna arm, so as to realize the reconfigurable antenna operating frequency, which has the advantages of easy integration, It can be invisible and the frequency can be quickly changed.

Description

Fabrication Method of Reconfigurable Dipole Antenna Based on Heterogeneous SiGeSPiN Diodes

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a preparation method of a reconfigurable dipole antenna based on a heterogeneous SiGeSPiN diode.

Background technique

Today, with the rapid development of antenna technology, the development trend of the new generation of wireless communication systems includes the realization of high-speed data transmission, the interconnection of multiple wireless systems, the effective use of limited spectrum resources, and the ability to adapt to the surrounding environment. . The concept of reconfigurable antennas has been paid attention to and developed in order to break through the fact that the fixed performance of traditional antennas is difficult to meet diverse system requirements and complex and changeable application environments. Reconfigurable microstrip antennas have become a hotspot in the research of reconfigurable antennas because of their small size and low profile.

Since the design of the reconfigurable antenna needs to consider the mutual coupling between the various parts of the antenna, the difficulty of antenna design is increased. The solid-state plasma exists in the semiconductor medium. When the solid-state plasma is excited by the forward bias of the SPiN diode, it can be used for electromagnetic radiation of the antenna. When the SPiN diode is not biased and turned off, it presents a semiconductor medium state, which can solve the problem of the antenna. Stealth and mutual coupling problems are more conducive to the design of reconfigurable antennas.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a preparation method of a reconfigurable dipole antenna based on heterogeneous SiGeSPiN diodes. The technical problem to be solved in the present invention is realized through the following technical solutions:

An embodiment of the present invention provides a method for preparing a reconfigurable dipole antenna based on a heterogeneous SiGeSPiN diode, wherein the reconfigurable dipole antenna includes: a SiGeOI substrate, a first SPiN diode antenna arm, The second SPiN diode antenna arm, coaxial feeder and DC bias line; wherein, the preparation method includes:

Select a SiGeOI substrate with a certain crystal orientation;

Manufacturing a plurality of SPiN diodes on the SiGeOI substrate and connecting them end to end to form an SPiN diode string;

making the first SPiN diode antenna arm and the second SPiN diode antenna arm;

making a DC bias line to connect the SPiN diode strings to a DC bias power supply;

making a coaxial feeder on the SPiN diode antenna arm; and connecting the first SPiN diode antenna arm and the second SPiN diode antenna arm to form the reconfigurable dipole antenna.

In one embodiment of the present invention, the first SPiN diode antenna arm and the second SPiN diode antenna arm are respectively composed of three sections of SPiN diode strings, and each SPiN diode string has a DC bias line externally connected to the positive voltage; the antenna arm The length is one quarter of the wavelength.

In one embodiment of the present invention, the coaxial feeder adopts a low-loss coaxial cable, and the inner core wire and the outer conductor (shielding layer) of the coaxial feeder are respectively welded on the metal contacts of the SPiN diode antenna arm and are connected at two places. The welding points are respectively connected with a DC bias line as a common negative pole.

In one embodiment of the present invention, described SPiN diode preparation method comprises the steps:

(a) setting an isolation region on the SiGeOI substrate;

(b) etching the substrate to form a P-type trench and an N-type trench, the depth of the P-type trench and the N-type trench is less than the thickness of the top layer SiGe of the substrate;

(c) oxidizing the P-type trench and the N-type trench to form an oxide layer on the inner walls of the P-type trench and the N-type trench;

(d) etching the oxide layer on the inner wall of the P-type trench and the N-type trench by a wet etching process to complete the planarization of the inner wall of the P-type trench and the N-type trench;

(e) filling the P-type trench and the N-type trench.

(f) Leads are formed on the substrate to complete the preparation of heterogeneous SiGeSPiN diodes.

On the basis of the foregoing embodiments, an isolation region is set on the SiGeOI substrate, including:

(a1) forming a first protection layer on the SiGe surface;

(a2) forming a first isolation region pattern on the first protective layer by using a photolithography process;

(a3) using a dry etching process to etch the first protective layer and the substrate at a designated position of the first isolation region pattern to form an isolation groove, and the depth of the isolation groove is greater than or equal to the The thickness of the top SiGe layer of the substrate;

(a4) filling the isolation trench to form the isolation region of the plasma pin diode.

On the basis of the above embodiments, the first protective layer includes a first silicon dioxide layer and a first silicon nitride layer; correspondingly, step (a1) includes:

(a11) generating silicon dioxide on the surface of the SiGe layer to form a first silicon dioxide layer;

(a12) growing silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.

On the basis of above-mentioned embodiment, step (b) comprises:

(b1) forming a second protective layer on the surface of the substrate;

(b2) forming a second isolation region pattern on the second protective layer by using a photolithography process;

(b3) Etching the second protection layer and the substrate at a designated position of the second isolation region pattern by a dry etching process to form the P-type trench and the N-type trench.

On the basis of the above embodiments, the second protective layer includes a second silicon dioxide layer and a second silicon nitride layer; correspondingly, step (b1) includes:

(b11) generating silicon dioxide on the surface of the substrate to form a second silicon dioxide layer;

(b12) growing silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.

On the basis of above-mentioned embodiment, step (f) comprises:

(f1) growing silicon dioxide on said substrate;

(f2) activating impurities in the active region by an annealing process;

(f3) Lithographically etching lead holes in the P-type contact region and the N-type contact region to form leads;

(f4) passivation treatment and photolithography of PAD to complete the preparation of the heterogeneous SiGeSPiN diode.

Compared with prior art, the beneficial effect of the present invention:

The reconfigurable dipole antenna of the heterogeneous SiGeSPiN diode prepared by the present invention has small volume, low profile, simple structure, easy processing, no complicated feed source structure, rapid frequency jump, and the antenna will be in an electromagnetic wave stealth state when it is turned off , can be used in various frequency hopping stations or equipment; because all its components are on the side of the semiconductor substrate, it is a planar structure, easy to form an array, and can be used as the basic component of a phased array antenna.

Description of drawings

FIG. 1 is a schematic structural diagram of a reconfigurable dipole antenna of a heterogeneous SiGeSPiN diode provided by an embodiment of the present invention;

2 is a schematic diagram of a method for preparing a reconfigurable dipole antenna of a heterogeneous SiGeSPiN diode provided by an embodiment of the present invention;

Fig. 3 is the schematic diagram of the preparation method of a kind of SPiN diode provided by the embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a heterogeneous SiGeSPiN diode provided by an embodiment of the present invention;

5 is a schematic structural diagram of a heterogeneous SiGeSPiN diode string provided by an embodiment of the present invention;

6a-6r are schematic diagrams of a method for preparing a heterogeneous SiGeSPiN diode according to an embodiment of the present invention.

detailed description

The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.

Embodiment one

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a reconfigurable dipole antenna based on a heterogeneous SiGeSPiN diode provided by an embodiment of the present invention, wherein the reconfigurable dipole antenna includes: a SiGeOI substrate, a second One SPiN diode antenna arm, the second SPiN diode antenna arm, coaxial feeder and DC bias line; Please refer to Fig. 2, Fig. 2 is the preparation method schematic diagram of the reconfigurable dipole antenna of heterogeneous SiGeSPiN diode, described preparation Methods include:

Select a SiGeOI substrate with a certain crystal orientation;

Manufacturing a plurality of SPiN diodes on the SiGeOI substrate and connecting them end to end to form an SPiN diode string;

making the first SPiN diode antenna arm and the second SPiN diode antenna arm;

making a DC bias line to connect the SPiN diode strings to a DC bias power supply;

making a coaxial feeder on the SPiN diode antenna arm; and connecting the first SPiN diode antenna arm and the second SPiN diode antenna arm to form the reconfigurable dipole antenna.

In one embodiment of the present invention, the first SPiN diode antenna arm and the second SPiN diode antenna arm are respectively composed of three sections of SPiN diode strings, and each SPiN diode string has a DC bias line externally connected to the positive voltage; the antenna arm The length is one quarter of the wavelength.

In one embodiment of the present invention, the coaxial feeder adopts a low-loss coaxial cable, and the inner core wire and the outer conductor (shielding layer) of the coaxial feeder are respectively welded on the metal contacts of the SPiN diode antenna arm and are connected at two places. The welding points are respectively connected with a DC bias line as a common negative pole.

Please refer to Figure 3, Figure 3 is a schematic diagram of the preparation method of the SPiN diode, the steps include:

(a) setting an isolation region on the SiGeOI substrate;

(b) etching the substrate to form a P-type trench and an N-type trench, the depth of the P-type trench and the N-type trench is less than the thickness of the top layer SiGe of the substrate;

(c) oxidizing the P-type trench and the N-type trench to form an oxide layer on the inner walls of the P-type trench and the N-type trench;

(d) etching the oxide layer on the inner wall of the P-type trench and the N-type trench by a wet etching process to complete the planarization of the inner wall of the P-type trench and the N-type trench;

(e) filling the P-type trench and the N-type trench.

(f) Leads are formed on the substrate to complete the preparation of heterogeneous SiGeSPiN diodes.

Among them, for step (a), the reason for using SiGeOI substrate is that solid-state plasma antennas require good microwave characteristics, and solid-state plasma pin diodes need to have good isolation characteristics and carriers that are solid-state in order to meet this requirement. Plasma confinement ability, and SiGeOI substrate is preferred to use SiGeOI because it has a pin isolation region that can be easily formed with isolation grooves, and silicon dioxide (SiO2) can also confine carriers, that is, solid-state plasma, in the top layer SiGe As a substrate for solid-state plasmonic pin diodes. Moreover, the carrier mobility of the SiGe material is relatively large, which can improve device performance.

Wherein, for step (d), the planarization treatment can adopt the following steps: oxidize the P-type trench and the N-type trench so that the inner walls of the P-type trench and the N-type trench form an oxide layer; utilize a wet etching process to etch Etching the oxide layer on the inner wall of the P-type trench and the N-type trench to complete the planarization of the inner wall of the P-type trench and the N-type trench. The advantage of doing this is that it can prevent the protrusion of the trench side wall from forming an electric field concentration area, causing breakdown of the Pi and Ni junctions.

On the basis of the foregoing embodiments, an isolation region is set on the SiGeOI substrate, including:

(a1) forming a first protection layer on the SiGe surface;

Specifically, the first protective layer includes a first silicon dioxide (SiO2) layer and a first silicon nitride (SiN) layer; then the formation of the first protective layer includes: generating silicon dioxide (SiO2) on the SiGe surface to form the first A silicon dioxide (SiO2) layer; growing silicon nitride (SiN) on the surface of the first silicon dioxide (SiO2) layer to form the first silicon nitride (SiN) layer. The advantage of this is that the stress of silicon nitride (SiN) is isolated by using the loose characteristics of silicon dioxide (SiO2), so that it cannot be conducted into the top layer SiGe, which ensures the stability of the performance of the top layer SiGe; based on silicon nitride (SiN ) and SiGe in dry etching have a high selectivity ratio, and silicon nitride (SiN) is used as a masking film for dry etching, which is easy to process. Of course, it can be understood that the number of layers of the protective layer and the material of the protective layer are not limited here, as long as the protective layer can be formed.

(a2) forming a first isolation region pattern on the first protective layer by using a photolithography process;

(a3) using a dry etching process to etch the first protective layer and the substrate at a designated position of the first isolation region pattern to form an isolation groove, and the depth of the isolation groove is greater than or equal to the The thickness of the top SiGe layer of the substrate;

(a4) filling the isolation trench to form the isolation region of the plasma pin diode.

On the basis of the above embodiments, the first protective layer includes a first silicon dioxide layer and a first silicon nitride layer; correspondingly, step (a1) includes:

(a11) generating silicon dioxide on the surface of the SiGe layer to form a first silicon dioxide layer;

(a12) growing silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.

On the basis of above-mentioned embodiment, step (b) comprises:

(b1) forming a second protective layer on the surface of the substrate;

Specifically, the second protective layer includes a second silicon dioxide (SiO2) layer and a second silicon nitride (SiN) layer; then the formation of the second protective layer includes: generating silicon dioxide (SiO2) on the surface of the substrate to form a second silicon dioxide (SiO2) layer; generating silicon nitride (SiN) on the surface of the second silicon dioxide (SiO2) layer to form a second silicon nitride (SiN) layer. The benefits of doing this are similar to the role of the first protective layer, so I won't repeat them here.

(b2) forming a second isolation region pattern on the second protective layer by using a photolithography process;

(b3) Etching the second protection layer and the substrate at a designated position of the second isolation region pattern by a dry etching process to form the P-type trench and the N-type trench.

Wherein, the depth of the P-type trench and the N-type trench is greater than the thickness of the second protection layer and less than the sum of the thickness of the second protection layer and the SiGe layer on the top of the substrate. Preferably, the distance between the bottom of the P-type trench and the bottom of the N-type trench and the bottom of the top layer SiGe of the substrate is 0.5 micron to 30 microns, forming a generally considered deep trench, so that when forming the P-type and N-type active regions P and N regions with uniform impurity distribution and high doping concentration and steep Pi-Ni junctions can be formed to help increase the plasma concentration in the i region.

On the basis of the above embodiments, the second protective layer includes a second silicon dioxide layer and a second silicon nitride layer; correspondingly, step (b1) includes:

(b11) generating silicon dioxide on the surface of the substrate to form a second silicon dioxide layer;

(b12) growing silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.

On the basis of above-mentioned embodiment, step (f) comprises:

(f1) growing silicon dioxide on said substrate;

(f2) activating impurities in the active region by an annealing process;

(f3) Lithographically etching lead holes in the P-type contact region and the N-type contact region to form leads;

(f4) passivation treatment and photolithography of PAD to complete the preparation of the heterogeneous SiGeSPiN diode.

The preparation method of the heterogeneous SiGe-based plasma pin diode provided by the present invention has the following advantages:

(1) The SiGe material used in the pin diode can effectively increase the solid-state plasma concentration of the pin diode due to its high mobility and large carrier lifetime characteristics;

(2) The pin diode adopts a heterojunction structure. Since the I region is SiGe, its carrier mobility is high and the band gap is narrow. The P and N regions are filled with polysilicon to form a heterojunction structure. The band gap of the silicon material Greater than SiGe, it can produce high injection ratio and improve device performance;

(3) The pin diode adopts an etching-based deep trench dielectric isolation process, which effectively improves the breakdown voltage of the device and suppresses the influence of leakage current on device performance.

Embodiment two

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of an SOI fundamental frequency reconfigurable dipole antenna based on SPiN diodes provided by the present invention. As shown in Figure 1, the antenna includes: a Si-based SOI semiconductor substrate 1;

The first antenna arm 2, the second antenna arm 3 and the coaxial feeder 4 fixed on the Si-based SOI semiconductor substrate 1; preferably, the coaxial feeder adopts a low-loss coaxial cable.

The first antenna arm 2 and the second antenna arm 3 are respectively arranged on both sides of the coaxial feeder 4 and include a plurality of SPiN diode strings. The turn-on and turn-off of the SPiN diode string realizes the adjustment of the length of the antenna arm.

The embodiments of the present invention realize that the frequency of the antenna can be reconfigured and the structure has no complicated feed source structure, and the structure is simple and easy to process.

Further, referring to FIG. 1, the first antenna arm 2 includes a first SPiN diode string w1, a second SPiN diode string w2, and a third SPiN diode string w3 connected in series, and the second antenna arm 3 includes a first SPiN diode string w3 connected in series. Four SPiN diode strings w4, the fifth SPiN diode string w5 and the sixth SPiN diode string w6;

Wherein, the length of the first SPiN diode string w1 is equal to the length of the sixth SPiN diode string w6, the length of the second SPiN diode string w2 is equal to the length of the fifth SPiN diode string w5, and the length of the third SPiN diode string w3 is equal to the length of the fourth SPiN diode string. The length of the diode string w4.

Further, please refer to FIG. 1, the antenna also includes a first DC bias line 5, a second DC bias line 6, a third DC bias line 7, a fourth DC bias line 8, a fifth DC bias line Line 9, the sixth DC bias line 10, the seventh DC bias line 11, and the eighth DC bias line 12, wherein,

The first DC bias line 5 is set at one end of the third diode string w3, the second DC bias line 6 is set at one end of the fourth diode string w4, and the third DC bias line 7 is set at the first One end of the SPiN diode string w1, the eighth DC bias line 12 is arranged at one end of the sixth SPiN diode string w6;

The fifth DC bias line 9 is arranged at the node formed by the series connection of the third diode string w3 and the second diode string w2, and the sixth DC bias line 10 is arranged at the fourth SPiN diode string w4 and the fifth SPiN diode string At the node formed by the series connection of the diode string w5, the fourth DC bias line 8 is set at the node formed by the series connection of the first SPiN diode string w1 and the second SPiN diode string w2, and the seventh DC bias line 11 is set at the fifth At the node formed by the series connection of the SPiN diode string w5 and the sixth SPiN diode string w6 .

Preferably, the first DC bias line 5, the second DC bias line 6, the third DC bias line 7, the fourth DC bias line 8, the fifth DC bias line 9, and the sixth DC bias line 10. The seventh DC bias line 11 and the eighth DC bias line 12 are fixed on the Si-based SOI semiconductor substrate 1 by chemical vapor deposition, and the material is any of copper, aluminum or doped polysilicon. A sort of.

Further, please refer to FIG. 1, the inner core wire of the coaxial feeder 4 is welded to the metal sheet of the first antenna arm 2, and the metal sheet of the first antenna arm 2 is connected to the DC bias line 5; the shielding layer of the coaxial feeder 4 Welded to the metal sheet of the second antenna arm 3, the metal sheet of the second antenna arm 3 is connected to the second DC bias line 6; the first DC bias line 5 and the second DC bias line 6 are connected to the DC bias line The negative poles of the voltages are connected to form a common negative pole.

Please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a schematic structural diagram of an SPiN diode provided by the present invention; FIG. 5 is a schematic structural diagram of an SPiN diode string provided by an embodiment of the present invention. Each SPiN diode string includes a plurality of SPiN diodes, and these SPiN diodes are connected in series. The SPiN diode in the SPiN diode string includes a P+ region 27, an N+ region 26 and an intrinsic region 22, and also includes a first metal contact region 23 and a second metal contact region 24; wherein,

The first metal contact region 23 is electrically connected to the P+ region 27, the second metal contact region 24 is electrically connected to the N+ region 26, the metal contact region 23 of the SPiN diode at one end of the SPiN diode string is connected to the positive pole of the DC bias, and is in the SPiN diode string The metal contact region 24 of the SPiN diode at the other end is connected to the cathode of the DC bias voltage, so that all the SPiN diodes of the corresponding SPiN diode string are in the forward conduction state after the DC bias voltage is applied.

In another embodiment of the present invention, the number of SPiN diode strings included in the first antenna arm 2 is the same as the number of SPiN diode strings included in the second antenna arm 3, the diode strings of the first antenna arm 2 and the second antenna arm The diode strings of 3 are symmetrically distributed with the coaxial feeder 4 as the symmetry axis, and any SPiN diode string of the first antenna arm 2 is equal in length to the corresponding SPiN diode string of the second antenna arm 3 which is symmetrical to the SPiN diode string.

In this embodiment, the number of diode strings included in the first antenna arm 2 and the second antenna arm 3 can be adjusted according to actual needs. During the working process, the arm lengths of the first antenna arm 2 and the second antenna arm 3 can be adjusted by controlling whether each diode string is turned on or not.

The frequency reconfigurable dipole antenna adopting this embodiment is small in size, simple in structure, easy to process, has no complicated feed source structure, and the frequency can jump quickly, and when the antenna is turned off, it will be in the state of electromagnetic wave stealth, and can be used for various frequency hopping Radio or equipment; because all its components are on the side of the semiconductor substrate, it is a planar structure, easy to form an array, and can be used as the basic component of a phased array antenna.

Embodiment three

Please refer to Fig. 6a-Fig. 6r. Fig. 6a-Fig. 6r is a schematic diagram of a method for preparing a heterogeneous SiGe-based plasmonic pin diode according to an embodiment of the present invention. A solid-state plasma pin diode with a solid-state plasma region length of 100 microns) is used as an example to describe in detail, and the specific steps are as follows:

Step 1, substrate material preparation steps:

(1a) As shown in Figure 6a, select a SiGeOI substrate 101 with a (100) crystal orientation, the doping type is p-type, the doping concentration is 1014cm-3, and the thickness of the top layer SiGe is 50 μm;

(1b) As shown in FIG. 6b, a first SiO2 layer 201 with a thickness of 40nm is deposited on the SiGe layer by chemical vapor deposition (Chemical vapor deposition, CVD for short);

(1c) Depositing a first Si3N4/SiN layer 202 with a thickness of 2 μm on the substrate by chemical vapor deposition;

Step 2, isolation preparation steps:

(2a) As shown in Figure 6c, an isolation region is formed on the above-mentioned protective layer by a photolithography process, and the first Si3N4/SiN layer 202 in the isolation region is wet-etched to form an isolation region pattern; dry etching is used to form an isolation region pattern; forming a deep isolation trench 301 with a width of 5 μm and a depth of 50 μm;

(2b) As shown in Fig. 6d, adopt the method of CVD, deposit SiO2 401 and fill up this deep isolation groove;

(2c) As shown in FIG. 6e, the first Si3N4/SiN layer 202 and the first SiO2 layer 201 on the surface are removed by using a chemical mechanical polishing (CMP) method to make the surface of the substrate smooth;

Step 3, preparation steps of deep grooves in P and N regions:

(3a) As shown in Fig. 6f, adopt CVD method to continuously deposit and extend two layers of materials on the substrate, the first layer is the second SiO2 layer 601 with a thickness of 300nm, and the second layer is the second Si3N4/SiN with a thickness of 500nm layer 602;

(3b) As shown in Figure 6g, photolithography of deep grooves in the P and N regions, wet etching the second Si3N4/SiN layer 602 and the second SiO2 layer 601 in the P and N regions to form patterns in the P and N regions; use dry method Etching, forming a deep groove 701 with a width of 4 μm and a depth of 5 μm in the P and N regions, and the length of the grooves in the P and N regions is determined according to the application in the prepared antenna;

(3c) As shown in Figure 6h, at 850°C, high temperature treatment for 10 minutes, an oxide layer 801 is formed on the inner wall of the oxidation tank, so that the inner wall of the tank in the P and N regions is smooth;

(3d) As shown in FIG. 6i , the oxide layer 801 on the inner wall of the trench in the P and N regions is removed by a wet etching process.

Step 4, P, N contact region preparation steps:

(4a) As shown in FIG. 6j, using CVD method, depositing polysilicon 1001 in the grooves of the P and N regions, and filling the grooves;

(4b) As shown in FIG. 6k, CMP is used to remove the surface polysilicon 1001 and the second Si3N4/SiN layer 602 to make the surface smooth;

(4c) As shown in FIG. 61, a layer of polysilicon 1201 is deposited on the surface by CVD, with a thickness of 200-500 nm;

(4d) As shown in Figure 6m, the active region of the P region is photolithographically, and p+ implantation is performed by the ion implantation method with glue, so that the doping concentration of the active region of the P region reaches 0.5×1020cm-3, and the photoresist is removed to form a P Contact 1301;

(4e) Lithographically engraving the active region of the N region, performing n+ implantation by using the ion implantation method with glue, so that the doping concentration of the active region of the N region is 0.5×1020cm-3, removing the photoresist, and forming an N contact 1302;

(4f) As shown in FIG. 6n, wet etching is used to etch away the polysilicon 1201 outside the P and N contact regions to form P and N contact regions;

(4g) As shown in Fig. 6o, adopt the method of CVD, deposit SiO21501 on the surface, the thickness is 800nm;

(4h) Annealing at 1000°C for 1 minute to activate the ion-implanted impurities and advance the impurities in the polysilicon;

Step 5, forming the PIN diode steps:

(5a) As shown in FIG. 6p, photolithographic lead holes 1601 are formed in the P and N contact areas;

(5b) As shown in Figure 6q, metal is sputtered on the surface of the substrate, a metal silicide 1701 is formed at 750° C., and the metal on the surface is etched away;

(5c) sputtering metal on the surface of the substrate, and photoetching leads;

(5d) As shown in FIG. 6r , deposit Si3N4/SiN to form a passivation layer 1801, photolithographically PAD, and form a PIN diode as a solid-state plasma antenna material.

In this embodiment, the above-mentioned various process parameters are all examples, and the transformations made according to the conventional means of those skilled in the art are within the protection scope of the present application.

The pin diode used in the solid-state plasma reconfigurable antenna prepared by the present invention, firstly, the SiGe material used improves the solid-state plasma concentration of the pin diode due to its high mobility and large carrier lifetime characteristics; in addition, The P region and N region of the heterogeneous SiGe-based pin diode adopt the polysilicon damascene process based on etching deep groove etching, which can provide abrupt junction pi and ni junctions, and can effectively improve the junction of pi junction and ni junction. Deep, the controllability of the concentration and distribution of solid-state plasma is enhanced, which is conducive to the preparation of high-performance plasma antennas; and the pin diode applied to solid-state plasma reconfigurable antennas prepared by the present invention uses an etching-based The deep trench dielectric isolation process effectively improves the breakdown voltage of the device and suppresses the influence of leakage current on the performance of the device.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. A preparation method of a reconfigurable dipole antenna based on heterogeneous SiGeSPiN diodes is characterized in that the reconfigurable dipole antenna comprises the following steps: the antenna comprises a SiGeOI substrate, a first SPiN diode antenna arm, a second SPiN diode antenna arm, a coaxial feeder line and a direct current bias line; wherein the preparation method comprises the following steps:

selecting a SiGeOI substrate with a certain crystal orientation;

manufacturing a plurality of SPiN diodes on the SiGeOI substrate, and sequentially connecting the SPiN diodes end to form a SPiN diode string;

manufacturing the first SPiN diode antenna arm and the second SPiN diode antenna arm;

manufacturing a direct current bias line to connect the SPiN diode string and a direct current bias power supply;

manufacturing a coaxial feeder on the SPiN diode antenna arm; and connecting the first SPiN diode antenna arm and the second SPiN diode antenna arm to form the reconfigurable dipole antenna.

2. The manufacturing method according to claim 1, wherein the first SPiN diode antenna arm and the second SPiN diode antenna arm are respectively composed of three SPiN diode strings, and each SPiN diode string is provided with a DC bias line and an external voltage anode; the antenna arms are one quarter of a wavelength long.

3. The preparation method according to claim 1, wherein a low-loss coaxial cable is adopted as the coaxial feeder, the inner core wire and the outer conductor (shielding layer) of the coaxial feeder are respectively welded on the metal contact of the SPiN diode antenna arm, and the two welding points are respectively connected with a direct current bias wire as a common cathode.

4. The method of manufacturing of claim 1, wherein the SPiN diode manufacturing method comprises the steps of:

(a) arranging an isolation region on the SiGeOI substrate;

(b) etching the substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of top SiGe of the substrate;

(c) oxidizing the P-type groove and the N-type groove to enable the inner walls of the P-type groove and the N-type groove to form an oxide layer;

(d) etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove;

(e) and filling the P-type groove and the N-type groove.

(f) And forming a lead on the substrate to complete the preparation of the heterogeneous SiGeSPiN diode.

5. The method of claim 3, wherein providing isolation regions on the SiGeOI substrate comprises:

(a1) forming a first protective layer on the surface of the SiGe;

(a2) forming a first isolation region pattern on the first protection layer by utilizing a photoetching process;

(a3) etching the first protective layer and the substrate at the designated position of the first isolation region graph by using a dry etching process to form an isolation groove, wherein the depth of the isolation groove is more than or equal to the thickness of top SiGe of the substrate;

(a4) filling the isolation trench to form the isolation region of the plasma pin diode.

6. The method according to claim 4, wherein the first protective layer comprises a first silicon dioxide layer and a first silicon nitride layer; accordingly, step (a1) includes:

(a11) generating silicon dioxide on the surface of the SiGe layer to form a first silicon dioxide layer;

(a12) and generating silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.

7. The method of claim 5, wherein step (b) comprises:

(b1) forming a second protective layer on the surface of the substrate;

(b2) forming a second isolation region pattern on the second protective layer by utilizing a photoetching process;

(b3) and etching the second protective layer and the substrate at the designated position of the second isolation region pattern by using a dry etching process to form the P-type groove and the N-type groove.

8. The manufacturing method according to claim 6, wherein the second protective layer includes a second silicon oxide layer and a second silicon nitride layer; accordingly, step (b1) includes:

(b11) generating silicon dioxide on the surface of the substrate to form a second silicon dioxide layer;

(b12) and generating silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.

9. The method of claim 7, wherein step (f) comprises:

(f1) generating silicon dioxide on the substrate;

(f2) activating impurities in the active region by using an annealing process;

(f3) photoetching lead holes in the P-type contact area and the N-type contact area to form leads;

(f4) passivating and photoetching PAD to finish the preparation of the heterogeneous SiGeSPiN diode.