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CN106816683A - For the manufacture method of the SPIN diodes of U wave band restructural loop aerial - Google Patents

For the manufacture method of the SPIN diodes of U wave band restructural loop aerial Download PDF

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Publication number
CN106816683A
CN106816683A CN201611184384.2A CN201611184384A CN106816683A CN 106816683 A CN106816683 A CN 106816683A CN 201611184384 A CN201611184384 A CN 201611184384A CN 106816683 A CN106816683 A CN 106816683A
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China
Prior art keywords
region
soi substrate
spin diode
layer
spin
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Inventor
尹晓雪
张亮
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Xian Cresun Innovation Technology Co Ltd
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Xian Cresun Innovation Technology Co Ltd
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Priority to CN201611184384.2A priority Critical patent/CN106816683A/en
Publication of CN106816683A publication Critical patent/CN106816683A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q7/00Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/50PIN diodes 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明属于固态等离子体和微带天线技术领域,具体涉及一种用于U波段可重构环形天线的SPIN二极管的制造方法,所述SPIN二极管用于制备U波段可重构环形天线,所述SPIN二极管的制造方法包括:选择SOI衬底(101);刻蚀所述SOI衬底(101)形成隔离槽,填充所述隔离槽形成隔离区(301);刻蚀所述SOI衬底(101)形成P区深槽(501)和N区深槽(502);在所述P区深槽(501)及所述N区深槽(502)内采用离子注入的方式形成P+有源区(601)和N+有源区(602);在所述SOI衬底(101)上生成引线。用该方法制备的环形天线具有体积小、可重构、易于集成、结构简单、馈电容易、频率可快速跳变的有益效果。

The invention belongs to the technical field of solid-state plasmas and microstrip antennas, and in particular relates to a method for manufacturing a SPIN diode for a U-band reconfigurable loop antenna. The SPIN diode is used to prepare a U-band reconfigurable loop antenna. The manufacturing method of SPIN diode comprises: select SOI substrate (101); Etch described SOI substrate (101) to form isolation groove, fill described isolation groove to form isolation region (301); Etch described SOI substrate (101 ) to form a P-region deep trench (501) and an N-region deep trench (502); a P+ active region ( 601) and N+ active region (602); generating leads on the SOI substrate (101). The loop antenna prepared by this method has the beneficial effects of small size, reconfigurability, easy integration, simple structure, easy feeding, and fast frequency jumping.

Description

For the manufacture method of the SPIN diodes of U wave band restructural loop aerial
Technical field
The invention belongs to solid state plasma and microstrip antenna technical field, and in particular to one kind is used for U wave band restructural The manufacture method of the SPIN diodes of loop aerial.
Background technology
With the further development of science and technology, wireless communication technology plays more and more important in the life of people Effect.Radio communication is operated using radio wave, and the reception of radio wave and transmission are completed by antenna, the performance of antenna Directly affect whole wireless communication system.
As wireless system is to Large Copacity, the development in multi-functional, multiband/ultra wide band direction, different communication systems are mutual Fusion so that the information subsystem quantity carried in identical platform increases, antenna amount also accordingly increases, but antenna amount Increasing the aspects such as Electro Magnetic Compatibility, cost, weight to communication system has larger negative effect.Therefore, wireless communication system It is required that antenna can change its electrical characteristics according to practical service environment, that is, realize " restructural " of antenna performance.Reconfigurable antenna Function with multiple antennas, reduces the quantity of antenna in system.Wherein, reconstructable microstrip aerial is cutd open because of its small volume The low advantage in face is paid close attention to by reconfigurable antenna research field.
The each several part of current frequency reconfigurable microstrip antenna has mutual coupling, and frequency hopping is slow, and feed structure is complicated, hidden Body performance is not good, and section is high, and manufacture, the difficulty processed are high.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides one kind for U wave band restructural annular The manufacture method of the SPIN diodes of antenna, wherein, loop aerial includes:Semiconductor chip (1);Dielectric-slab (2);First SPIN Diode ring (3), the 2nd SPIN diode rings (4), the first direct current biasing line (5) and the second direct current biasing line (6), may be contained within On semiconductor chip (1);Manifold type feed (7), is arranged on dielectric-slab (2);
Wherein, the manufacture method of the SPIN diodes of the restructural loop aerial comprises the following steps:
Selection SOI substrate (101);
Etching SOI substrate (101) forms isolation channel, and filling isolation channel forms isolated area (301);
Etching SOI substrate (101) forms P areas' deep trouth (501) and N areas deep trouth (502);
P+ active areas (601) and N+ are formed by the way of ion implanting in P areas deep trouth (501) and N areas deep trouth (502) Active area (602);
Lead is generated in SOI substrate (101).
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, carve Erosion SOI substrate (101) forms isolation channel, including:
The first protective layer is formed on SOI substrate (101) surface;
The first isolated area figure is formed on the first protective layer using photoetching process;
Specified location using dry etch process in the first isolated area figure etches the first protective layer and SOI substrate (101) forming isolation channel.
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, bag Include:
Materials at two layers is grown using the method for CVD is continuous in SOI substrate (101), wherein, ground floor is SiO2 layers (201), the second layer is SiN layer (202).
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, carve Erosion SOI substrate (101) forms P areas' deep trouth (501) and N areas deep trouth (502), including:
The second protective layer is formed on SOI substrate (101) surface;
The second isolated area figure is formed on the second protective layer using photoetching process;
Specified location using dry etch process in the second isolated area figure etches the second protective layer and SOI substrate (101) forming P areas deep trouth (501) and N areas deep trouth (502);Wherein, the depth in P areas deep trouth (501) and N areas deep trouth (502) is 0.5 micron~30 microns.
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, SOI substrate (101) surface forms the second protective layer, including:
Materials at two layers is grown using the method for CVD is continuous in SOI substrate (101), wherein, ground floor is SiO2 layers (401), the second layer is SiN layer (402).
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, in P P+ active areas (601) and N+ active areas are formed by the way of ion implanting in area's deep trouth (501) and N areas deep trouth (502) (602), including:
Planarizing P areas' deep trouth (501) and N areas deep trouth (502);
Carry out ion implanting to P areas deep trouth (501) and N areas deep trouth (502) has to form a P+ active areas and a N+ Source region;P areas' deep trouth (501) and N areas deep trouth (502) is filled to form P contact zones and N contact zones;To P contact zones and N contact zones Region carries out ion implanting to form the 2nd P+ active areas and the 2nd N+ active areas in the top layer silicon of SOI substrate (101);
Wherein, a N+ active areas are micro- less than 1 away from N areas deep trouth (502) side wall and bottom depth along ion dispersal direction The region of rice, a P+ active areas are to be less than 1 micron away from P areas deep trouth (501) side wall and bottom depth along ion dispersal direction Region.
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, SOI substrate generates lead on (101), including:
Silica is generated in SOI substrate (101);
The impurity in P+ active areas (601) and N+ active areas (602) is activated using annealing process;
In P contact zones and N contact zones lithography fair lead forming lead;
Passivation Treatment and photoetching PAD are forming SPIN diodes.
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, half Semiconductor substrate (1) is Si base soi semiconductor pieces, and a SPIN diode rings (3) include SPIN diodes string (8), second SPIN diode rings (4) include the 2nd SPIN diodes string (9), and a SPIN diode rings (3) and the 2nd SPIN diodes The girth of ring (4) is equal to the electromagnetic wavelength to be received signal.
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, First SPIN diodes string (8) and the 2nd SPIN diodes string (9) two ends are provided with the first direct current biasing line (5) and the second direct current Offset line (6), the first direct current biasing line (5) and the second direct current biasing line (6) are produced on semiconductor-based using heavily doped polysilicon On piece (1).
In a kind of manufacture method of SPIN diodes for U wave band restructural loop aerial that the present invention is provided, it is situated between The upper surface of scutum (2) is metal micro-strip paster (10), and lower surface is metal ground plate (11);Also, metal micro-strip paster (10) including major branch section (12), the first branch section (13) and the second branch section (14), wherein, the width and medium of major branch section (12) The thickness of plate (2) determines by the impedance matching of manifold type feed (7), the length of the first branch section (13) and the second branch section (14) Determined by the impedance matching of antenna respectively with width, the distance between semiconductor chip (1) and dielectric-slab (2) by antenna gain Determine.
The SPIN diodes obtained using the present invention program are used to manufacture loop aerial, the advantage bag of the loop aerial Include:
1st, the frequency reconfigurable couple feed loop aerial small volume, low section, simple structure, easy to process.
2nd, using heavily doped polysilicon as direct current biasing line, it is to avoid influence of the metal feeder to antenna performance.
3rd, need to be only turned on or off by controlling it as the basic component units of antenna using SPIN diodes, you can Realize the restructural of frequency.
Brief description of the drawings
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become obvious.But should know Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to Appended claims.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to concept Ground explanation structure described herein and flow.
Fig. 1 is a kind of manufacture of SPIN diodes for U wave band restructural loop aerial provided in an embodiment of the present invention Method flow schematic diagram;
Fig. 2 is a kind of SOI fundamental frequency restructural couple feed rings based on SPIN diodes provided in an embodiment of the present invention The structural representation of shape antenna;
Fig. 3 is a kind of SPIN diode structures schematic diagram provided in an embodiment of the present invention;
Fig. 4 is a kind of SOI fundamental frequency restructural couple feed rings based on SPIN diodes provided in an embodiment of the present invention The semiconductor substrate structures schematic diagram of shape antenna;
Fig. 5 is a kind of SOI fundamental frequency restructural couple feed rings based on SPIN diodes provided in an embodiment of the present invention The medium plate structure schematic diagram of shape antenna;
Fig. 6 is a kind of SPIN diodes string schematic diagram provided in an embodiment of the present invention;
Fig. 7 a- Fig. 7 l are a kind of SPIN diodes for U wave band restructural loop aerial provided in an embodiment of the present invention Manufacture method flowsheet simulation schematic diagram;
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to This.
Below in conjunction with accompanying drawing, specific embodiment of the invention is described in detail:
Embodiment one
It is that a kind of U wave band frequency based on SPIN diodes provided in an embodiment of the present invention can to refer to Fig. 1 and Fig. 2, Fig. 1 Reconstruct the manufacture method schematic flow sheet of loop aerial;Fig. 2 is provided in an embodiment of the present invention a kind of based on SPIN diodes The structural representation of SOI fundamental frequency restructural couple feed loop aerials, the SPIN diodes are mainly used in frequency reconfigurable Dipole antenna, the antenna includes:Semiconductor chip 1, dielectric-slab 2, a SPIN diode rings 3, the 2nd SPIN diode rings 4, the first direct current biasing line 5, the second direct current biasing line 6 may be contained within semiconductor chip 1;Manifold type feed 7, is arranged at Jie On scutum 2.Specifically, the manufacture method of SPIN diodes comprises the following steps:
Selection SOI substrate 101;
Etching SOI substrate 101 forms isolation channel, and filling isolation channel forms isolated area 301;
Etching SOI substrate 101 forms P areas deep trouth 501 and N areas deep trouth 502;
P+ active areas 601 and N+ active areas are formed by the way of ion implanting in deep trouth 501 and N areas deep trouth 502 in P areas 602;
Lead is generated in SOI substrate 101.
Using this implementation provide frequency reconfigurable dipole antenna small volume, simple structure, it is easy to process, without complexity present Source structure, frequency can rapid jumping, effectively overcome the deficiencies in the prior art.
Further, wherein, etching SOI substrate 101 formed isolation channel, specifically can also be in the following way:
The first protective layer is formed on the surface of SOI substrate 101;
The first isolated area figure is formed on the first protective layer using photoetching process;
Specified location using dry etch process in the first isolated area figure etches the first protective layer and SOI substrate 101 forming isolation channel.
Further, in the present embodiment, the first protective layer is formed on the surface of SOI substrate 101, can is specifically:
Materials at two layers is grown using the method for CVD is continuous in SOI substrate 101, wherein, ground floor is SiO2 layers 201, the Two layers is SiN layer 202.
Further, wherein, etching SOI substrate 101 forms P areas deep trouth 501 and N areas deep trouth 502, can be specifically:
The second protective layer is formed on the surface of SOI substrate 101;
The second isolated area figure is formed on the second protective layer using photoetching process;
Specified location using dry etch process in the second isolated area figure etches the second protective layer and SOI substrate 101 forming P areas deep trouth 501 and N areas deep trouth 502;Wherein, the depth of P areas deep trouth 501 and N areas deep trouth 502 be 0.5 micron~ 30 microns.
Further, in the present embodiment, the second protective layer is formed on the surface of SOI substrate 101, can is specifically:
Materials at two layers is grown using the method for CVD is continuous in SOI substrate 101, wherein, ground floor is SiO2 layers 401, the Two layers is SiN layer 402
Further, wherein, in deep trouth 501 and N areas deep trouth 502 P+ is formed by the way of ion implanting in P areas active Area 601 and N+ active areas 602, specifically can also be in the following way:
Planarizing P areas deep trouth 501 and N areas deep trouth 502;
P areas deep trouth 501 and N areas deep trouth 502 are carried out ion implanting to form a P+ active areas and a N+ active areas; P areas deep trouth 501 and N areas deep trouth 502 are filled to form P contact zones and N contact zones;P contact zones and N contact zones region are entered Row ion implanting is with formation the 2nd P+ active areas and the 2nd N+ active areas in the top layer silicon of SOI substrate 101;
Wherein, a N+ active areas are to be less than 1 micron away from the side wall of N areas deep trouth 502 and bottom depth along ion dispersal direction Region, a P+ active areas are the region less than 1 micron along ion dispersal direction away from the side wall of P areas deep trouth 501 and bottom depth.
Further, wherein, lead is generated in SOI substrate 101, specifically can also be in the following way:
Silica is generated in SOI substrate 101;
Using the impurity in annealing process activation P+ active areas 601 and N+ active areas 602;
In P contact zones and N contact zones lithography fair lead forming lead;
Passivation Treatment and photoetching PAD are forming SPIN diodes.
Further, wherein, P areas deep trouth 501 and N areas deep trouth 502 are carried out ion implanting to form a P+ active areas With a N+ active areas;P areas deep trouth 501 and N areas deep trouth 502 are filled to form P contact zones and N contact zones;To P contact zones and N Contact zone region carry out ion implanting with the top layer silicon of substrate 101 formed the 2nd P+ active areas and the 2nd N+ it is active Area, specifically can also be in the following way:
The photoetching P areas deep trouth 501 and side wall to P areas deep trouth 501 by the way of with glue ion implanting carries out P+ injections, P+ active areas 601 are formed on the side wall and photoresist is removed;Photoetching N areas deep trouth 502 and by the way of with glue ion implanting to N The side wall of area's deep trouth 502 carries out N+ injections, and N+ active areas 602 are formed on the side wall and photoresist is removed;
Deposited in P areas deep trouth 501 and N areas deep trouth 502 and fill up polysilicon 701 using the method for CVD;
Photoetching P+ active areas 601 simultaneously carry out P+ injections by the way of with glue ion implanting, so that P+ active areas 601 reach First doping concentration simultaneously removes photoresist to form P contact zones 801;Photoetching N+ active areas 602 are simultaneously used with glue ion implanting Mode carries out N+ injections, so that N+ active areas 602 reach the second doping concentration and remove photoresist to form N contact zones 802;
Polysilicon beyond P contact zones 801 and N contact zones 802 are etched by the way of the wet etching;
Using CVD method P contact zones 801 and N contact zones 802 SiO2 layers 901 of surface deposition silica.
Further, in another embodiment of the present invention, a SPIN diode rings 3, second of loop aerial SPIN diode rings 4, the first direct current biasing line 5 and the second direct current biasing line 6 are produced on semiconductor chip 1 using semiconductor technology On, its semiconductor chip 1 and dielectric-slab 2 are Si base soi semiconductor pieces.
Said frequencies restructural couple feed loop aerial, a SPIN diode rings 3 include a SPIN diode strings 8, the 2nd SPIN diode rings 4 include the 2nd SPIN diodes string 9, and a SPIN diode rings 3 and the 2nd SPIN diodes The girth of ring 4 is equal to the electromagnetic wavelength to be received signal.
Said frequencies restructural couple feed loop aerial, a SPIN diodes string 8 is provided with the first direct current biasing line 5, the 2nd SPIN diodes string 9 is provided with the second direct current biasing line 6, and the first direct current biasing line 5 and the second direct current biasing line 6 are adopted It is produced on semiconductor chip 1 with heavily doped polysilicon.
Said frequencies restructural couple feed loop aerial, the upper surface of dielectric-slab 2 is metal micro-strip paster, and lower surface is Metal ground plate.
Said frequencies restructural couple feed loop aerial, metal micro-strip paster includes major branch section 12, the first branch section 13 And the second branch section 14.
Said frequencies restructural couple feed loop aerial, the width of major branch section 12 and the thickness of dielectric-slab 2 are by manifold type The impedance matching of feed 7 determines that the length and width of the first branch section 13 and the second branch section 14 is respectively by the impedance of antenna With decision.Wherein, it is preferred that the impedance of feed 7 is 50 Ω.
The distance between said frequencies restructural couple feed loop aerial, semiconductor chip 1 and dielectric-slab 2 are by antenna Gain is determined.
Said frequencies restructural couple feed loop aerial, the number of a SPIN diode rings 3 is at least one, second The number of SPIN diode rings 4 is at least one.
In the present embodiment, by designing a kind of SOI fundamental frequency restructurals couple feed annular day based on SPIN diodes The mode of line, solves the problems, such as the mutual coupling between the run into antenna sections of communication at present, brings loop aerial small volume, can weigh Structure, be easily integrated, simple structure, feed easily, frequency can rapid jumping, can be used for the beneficial effect of various frequency hopping radio sets or equipment Really.
Fig. 3 is referred to, Fig. 3 is a kind of SPIN diode structures schematic diagram provided in an embodiment of the present invention, the poles of SPIN bis- Guan You P+ areas 27, N+ areas 26 and intrinsic region 22 are constituted, and the first metal contact zone 23 is located at P+ areas 27, is connected to direct current biasing Positive pole, the second metal contact zone 24 is located at N+ areas 26, is connected to the negative pole of direct current biasing, by apply DC voltage can make it is whole All SPIN diodes are in forward conduction state in individual SPIN diodes string.It is solid when being excited using the biasing of SPIN diode forwards During state plasma, can be used for the electromagnetic radiation of antenna.And SPIN diodes are not added with biasing when closing, then semiconductor medium is presented State, it is possible to resolve the mutual coupling problem between antenna, the more conducively design of reconfigurable antenna.
As shown in figure 4, a SPIN diode rings 3 are made up of a SPIN diodes string 8, its ring girth is equal to be connect The electromagnetic wavelength of receipts, one end of a SPIN diodes string 8 is provided with the first direct current biasing line 5, another to be connected to common.
As shown in figure 4, the 2nd SPIN diode rings 4 are made up of the 2nd SPIN diodes string 9, its ring girth is equal to be connect The electromagnetic wavelength (frequency) of receipts, the one end of the 2nd SPIN diodes string 9 is provided with the second direct current biasing line 6, another to be connected to public affairs Holding altogether.
As shown in figure 4, the first direct current biasing line 5, the second direct current biasing line 6 are respectively connected to positive polarity, and any work Moment can only have one group of direct current biasing line to be connected to positive polarity, by controlling the first direct current biasing line 5 or the second direct current biasing line 6 On voltage optionally make a SPIN diodes string 8 or the 2nd SPIN diodes string 9 in forward conduction state, lead Logical SPIN diodes will produce solid state plasma in intrinsic region, and it has metalloid characteristic, can serve as the radiation of antenna Structure.When different SPIN diodes strings works, the electric size length of antenna can be changed, so as to realize operating frequency of antenna Restructural.
As shown in figure 5, manifold type feed 7 is made on dielectric-slab 2 using chemical gas-phase deposition method, upper surface is metal Microband paste 10, lower surface is metal ground plate 11, and metal micro-strip paster 10 includes a major branch section 12, the first branch section 13 And the second branch section 14.The width of major branch section 10 and the thickness of dielectric-slab 2 are determined by 50 Ω impedance matchings of feed, are additionally coupled to interior The energy of outer shroud is bigger, then the width of major branch section 12 is bigger.First branch section 13 and the length and width of the second branch section 14 are by antenna Impedance matching determine, the standing wave of regulation antenna can be changed by the first branch section 13 and the length and width of the second branch section 14. The distance between semiconductor chip and dielectric-slab are determined by the gain of antenna.
The SPIN diodes obtained using the present embodiment are used to manufacture loop aerial, and the advantage of the loop aerial includes: Small volume, restructural, be easily integrated, simple structure, feed easily, frequency can rapid jumping, can be used for various frequency hopping radio sets or Equipment.
Embodiment two
Refer to Fig. 7 a- Fig. 7 l, the present embodiment on the basis of above-described embodiment, to the system of SPIN diodes of the invention Preparation Method is described in detail, and specifically, the manufacture of SPIN diodes is realized using following steps:
As shown in Figure 7a, SOI substrate 101 is chosen.
As shown in Figure 7b, using the method for chemical vapor deposition (Chemical vapor deposition, abbreviation CVD), The continuous growth materials at two layers in SOI substrate 101, ground floor can be silica (SiO2) layer of thickness in 300~500nm 201, the second layer can be silicon nitride (SiN) layer 202 of thickness at 1~3 μm.
As shown in Figure 7 c, isolated area is formed on above-mentioned protective layer by photoetching process.Etched using wet-etching technology Silicon nitride (SiN) layer, forms isolated area figure, then using dry etching, forms for example a width of 2~10 μm, deep 1~81 μm Isolated area 301.
As shown in figure 7d, using the method for CVD, the continuous materials at two layers long on substrate, ground floor be thickness 300~ Silica (SiO2) layer 401 of 500nm, the second layer is silicon nitride (SiN) layer 402 of thickness in 400~600nm.
As shown in figure 7e, photoetching P, N areas deep trouth, wet etching P, N areas silicon nitride (SiN) floor forms P, N area figure, does Method is etched, and forms deep trouth 501 wide 2~8 μm, deep 0.4~10 μm.
As depicted in fig. 7f, photoetching P areas deep trouth, p+ injections are carried out using the method with glue ion implanting to P areas groove sidewall, are made Thin p+ active areas 601 are formed on the wall of side, concentration reaches 0.5~5 × 1020cm-3, removes photoresist;Photoetching N areas deep trouth, adopts N+ injections are carried out to N areas groove sidewall with the method with glue ion implanting, makes to form thin n+ active areas 602 on the wall of side, concentration reaches To 0.5~5 × 1020cm-3, photoresist is removed.
As shown in figure 7g, using the method for CVD, the depositing polysilicon 701 in P, N area groove, and groove is filled up.
As shown in Fig. 7 h, p+ injections can be carried out using band glue ion injection method by photoetching P areas active area, make P areas Active area doping concentration reaches 0.5~5 × 1020cm-3, removes photoresist, forms P contacts 801;Photoetching N areas active area, uses Band glue ion implanting carries out n+ injections, makes N areas active area doping concentration be 0.5~5 × 1020cm-3, removes photoresist, and shape Into N contacts 802.
As shown in figure 7i, using wet etching, the polysilicon beyond P, N contact zone is etched away, forms P, N contact zone.
As shown in Fig. 7 j, using the method for CVD, in surface deposition silica (SiO2) layer 901.
As shown in Fig. 7 k, the lithography fair lead 1001 on silica (SiO2) layer.
As shown in Fig. 7 l, passivation layer 1101, photoetching PAD are formed by deposit silicon nitride (SiN).
The SPIN diodes obtained using the present embodiment are used to manufacture loop aerial, and the advantage of the loop aerial includes:
1st, small volume, section are low, simple structure, easy to process.
2nd, using coaxial cable as feed, without complicated feed structure.
3rd, need to be only turned on or off by controlling it as the basic component units of antenna using SPIN diodes, you can Realize the restructural of frequency.
4th, all constituents are in semiconductor chip side, it is easy to plate-making processing.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to assert Specific implementation of the invention is confined to these explanations.For general technical staff of the technical field of the invention, On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should be all considered as belonging to of the invention Protection domain.

Claims (10)

1.一种用于U波段可重构环形天线的SPIN二极管的制造方法,其特征在于,所述SPIN二极管用于制备U波段可重构环形天线,所述环形天线包括:1. a kind of manufacture method for the SPIN diode of U band reconfigurable loop antenna, it is characterized in that, described SPIN diode is used for preparing U band reconfigurable loop antenna, and described loop antenna comprises: 半导体基片(1);A semiconductor substrate (1); 介质板(2);Dielectric board (2); 第一SPIN二极管环(3)、第二SPIN二极管环(4)、第一直流偏置线(5)及第二直流偏置线(6),均设置于所述半导体基片(1)上;The first SPIN diode ring (3), the second SPIN diode ring (4), the first DC bias line (5) and the second DC bias line (6), are all arranged on the semiconductor substrate (1) superior; 耦合式馈源(7),设置于所述介质板(2)上;A coupled feed (7), arranged on the dielectric board (2); 其中,所述可重构环形天线的SPIN二极管的制造方法包括如下步骤:Wherein, the manufacturing method of the SPIN diode of the reconfigurable loop antenna includes the following steps: 选择SOI衬底(101);Select SOI substrate (101); 刻蚀所述SOI衬底(101)形成隔离槽,填充所述隔离槽形成隔离区(301);Etching the SOI substrate (101) to form isolation grooves, filling the isolation grooves to form isolation regions (301); 刻蚀所述SOI衬底(101)形成P区深槽(501)和N区深槽(502);Etching the SOI substrate (101) to form a P-region deep groove (501) and an N-region deep groove (502); 在所述P区深槽(501)及所述N区深槽(502)内采用离子注入的方式形成P+有源区(601)和N+有源区(602);Forming a P+ active region (601) and an N+ active region (602) in the P-region deep trench (501) and the N-region deep trench (502) by means of ion implantation; 在所述SOI衬底(101)上生成引线。Leads are generated on said SOI substrate (101). 2.如权利要求1所述的方法,其特征在于,刻蚀所述SOI衬底(101)形成隔离槽,包括:2. The method according to claim 1, wherein etching the SOI substrate (101) to form isolation grooves comprises: 在所述SOI衬底(101)表面形成第一保护层;forming a first protective layer on the surface of the SOI substrate (101); 利用光刻工艺在所述第一保护层上形成第一隔离区图形;forming a first isolation region pattern on the first protective layer by using a photolithography process; 利用干法刻蚀工艺在所述第一隔离区图形的指定位置处刻蚀所述第一保护层及所述SOI衬底(101)以形成所述隔离槽。The first protection layer and the SOI substrate (101) are etched at a designated position of the first isolation region pattern by a dry etching process to form the isolation groove. 3.如权利要求2所述的方法,其特征在于,在所述SOI衬底(101)表面形成第一保护层,包括:3. The method according to claim 2, wherein forming a first protective layer on the surface of the SOI substrate (101) comprises: 采用CVD的方法在所述SOI衬底(101)上连续生长两层材料,其中,第一层为SiO2层(201),第二层为SiN层(202)。Two layers of materials are continuously grown on the SOI substrate (101) by means of CVD, wherein the first layer is a SiO2 layer (201), and the second layer is a SiN layer (202). 4.如权利要求1所述的方法,其特征在于,刻蚀所述SOI衬底(101)形成P区深槽(501)和N区深槽(502),包括:4. The method according to claim 1, wherein etching the SOI substrate (101) to form a P-region deep trench (501) and an N-region deep trench (502) comprises: 在所述SOI衬底(101)表面形成第二保护层;forming a second protective layer on the surface of the SOI substrate (101); 利用光刻工艺在所述第二保护层上形成第二隔离区图形;forming a second isolation region pattern on the second protection layer by using a photolithography process; 利用干法刻蚀工艺在所述第二隔离区图形的指定位置处刻蚀所述第二保护层及所述SOI衬底(101)以形成所述P区深槽(501)和所述N区深槽(502);其中,所述P区深槽(501)和N区深槽(502)的深度为0.5微米~30微米。Etch the second protection layer and the SOI substrate (101) at the designated position of the second isolation region pattern by dry etching process to form the P region deep groove (501) and the N Deep grooves in the region (502); wherein, the depths of the deep grooves in the P region (501) and the deep grooves in the N region (502) are 0.5 microns to 30 microns. 5.如权利要求4所述的方法,其特征在于,在所述SOI衬底(101)表面形成第二保护层,包括:5. The method according to claim 4, wherein forming a second protective layer on the surface of the SOI substrate (101) comprises: 采用CVD的方法在所述SOI衬底(101)上连续生长两层材料,其中,第一层为SiO2层(401),第二层为SiN层(402)。Two layers of materials are continuously grown on the SOI substrate (101) by CVD, wherein the first layer is a SiO2 layer (401), and the second layer is a SiN layer (402). 6.如权利要求1所述的方法,其特征在于,在所述P区深槽(501)及所述N区深槽(502)内采用离子注入的方式形成P+有源区(601)和N+有源区(602),包括:6. The method according to claim 1, characterized in that, forming a P+ active region (601) and a P+ active region (601) and N+ active region (602), comprising: 平整化所述P区深槽(501)和所述N区深槽(502);planarizing the P-region deep trenches (501) and the N-region deep trenches (502); 对所述P区深槽(501)和所述N区深槽(502)进行离子注入以形成第一P+有源区和第一N+有源区;填充所述P区深槽(501)和所述N区深槽(502)以形成P接触区和N接触区;对所述P接触区和所述N接触区所在区域进行离子注入以在所述SOI衬底(101)的顶层硅内形成第二P+有源区和第二N+有源区;performing ion implantation on the P-region deep trench (501) and the N-region deep trench (502) to form a first P+ active region and a first N+ active region; filling the P-region deep trench (501) and Deep grooves (502) in the N region to form a P contact region and an N contact region; ion implantation is performed on the region where the P contact region and the N contact region are located to form the top silicon layer of the SOI substrate (101) forming a second P+ active region and a second N+ active region; 其中,所述第一N+有源区为沿离子扩散方向距所述N区深槽(502)侧壁和底部深度小于1微米的区域,所述第一P+有源区为沿离子扩散方向距所述P区深槽(501)侧壁和底部深度小于1微米的区域。Wherein, the first N+ active region is a region with a depth of less than 1 micron from the sidewall and bottom of the N-region deep groove (502) along the direction of ion diffusion, and the first P+ active region is a region along the direction of ion diffusion from The deep groove (501) in the P region is a region where the sidewall and bottom depth are less than 1 micron. 7.如权利要求1所述的方法,其特征在于,所述在所述SOI衬底(101)上生成引线,包括:7. The method according to claim 1, wherein said generating leads on said SOI substrate (101) comprises: 在所述SOI衬底(101)上生成二氧化硅;growing silicon dioxide on the SOI substrate (101); 利用退火工艺激活所述P+有源区(601)和所述N+有源区(602)中的杂质;activating impurities in the P+ active region (601) and the N+ active region (602) by an annealing process; 在P接触区和N接触区光刻引线孔以形成引线;Lead holes are photolithographically formed in the P contact area and the N contact area to form leads; 钝化处理并光刻PAD以形成所述SPIN二极管。The PAD is passivated and photolithographically formed to form the SPIN diode. 8.根据权利要求1所述的方法,其特征在于,所述半导体基片(1)为Si基SOI半导体片,所述第一SPIN二极管环(3)包括第一SPIN二极管串(8),所述第二SPIN二极管环(4)包括第二SPIN二极管串(9),且所述第一SPIN二极管环(3)及所述第二SPIN二极管环(4)的周长等于所要接收信号的电磁波波长。8. method according to claim 1, it is characterized in that, described semiconductor substrate (1) is Si base SOI semiconductor chip, and described first SPIN diode ring (3) comprises first SPIN diode string (8), The second SPIN diode ring (4) includes a second SPIN diode string (9), and the circumference of the first SPIN diode ring (3) and the second SPIN diode ring (4) is equal to the signal to be received electromagnetic wavelength. 9.根据权利要求8所述的方法,其特征在于,在所述第一SPIN二极管串(8)及所述第二SPIN二极管串(9)两端设置有第一直流偏置线(5)及第二直流偏置线(6),所述第一直流偏置线(5)及所述第二直流偏置线(6)采用重掺杂多晶硅制作在所述半导体基片上(1)。9. The method according to claim 8, characterized in that a first DC bias line (5) is provided at both ends of the first SPIN diode string (8) and the second SPIN diode string (9) ) and the second DC bias line (6), the first DC bias line (5) and the second DC bias line (6) are fabricated on the semiconductor substrate (1 by heavily doped polysilicon) ). 10.根据权利要求9所述的方法,其特征在于,所述介质板(2)的上表面为金属微带贴片(10),下表面为金属接地板(11);并且,所述金属微带贴片(10)包括主枝节(12)、第一分枝节(13)及第二分枝节(14),其中,所述主枝节(12)的宽度和所述介质板(2)的厚度由所述耦合式馈源(7)的阻抗匹配决定,所述第一分枝节(13)及所述第二分枝节(14)的长度和宽度分别由天线的阻抗匹配决定,所述半导体基片(1)与所述介质板(2)之间的距离由天线的增益决定。10. The method according to claim 9, characterized in that, the upper surface of the dielectric plate (2) is a metal microstrip patch (10), and the lower surface is a metal ground plate (11); and, the metal The microstrip patch (10) includes a main branch (12), a first branch (13) and a second branch (14), wherein the width of the main branch (12) and the width of the medium plate (2) The thickness is determined by the impedance matching of the coupled feed (7), the length and width of the first branch (13) and the second branch (14) are respectively determined by the impedance matching of the antenna, and the semiconductor The distance between the substrate (1) and the dielectric plate (2) is determined by the gain of the antenna.
CN201611184384.2A 2016-12-20 2016-12-20 For the manufacture method of the SPIN diodes of U wave band restructural loop aerial Pending CN106816683A (en)

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