CN106802777A - A kind of flash translation layer (FTL) control method for solid storage device - Google Patents

Abstract

The invention discloses a flash memory conversion layer control method for a solid-state storage device, comprising the following steps: Step S1: setting a minimum management unit in the flash memory conversion layer (FTL), and N minimum management units just constitute a flash memory physical page space, wherein, N is a positive integer greater than 0; step S2: mapping between the logical address and the physical address with the smallest management unit; step S3: FTL gives each smallest management unit data an address identifier for management; step S4: When the host writes data, it waits for the continuously written data to reach a complete flash physical page space, and then writes a complete blank flash physical page at one time. Compared with the prior art, the present invention adopts a 4KB data block mapping algorithm, so that the random writing speed can be effectively improved, and at the same time, larger and larger mapping tables can be realized in limited on-chip storage space.

Description

A flash memory conversion layer control method for solid-state storage devices

technical field

The invention relates to the field of storage technology, in particular to a method for controlling a flash conversion layer of a solid-state storage device.

Background technique

With the advancement of semiconductor technology, the capacity of flash memory is getting bigger and bigger, but the price is getting cheaper and cheaper. Solid-state drives (SSDs) are replacing traditional mechanical hard drives (HDDs) with magnetic tape as the medium in more and more fields. The biggest difference between a solid-state drive and a mechanical hard drive is that there are no mechanical parts in a solid-state drive. Therefore, compared with traditional hard drives, SSDs have lower latency and energy consumption, faster data processing speeds, better shock resistance, higher reliability and durability.

The storage device of solid-state hard disk uses flash memory, and NAND flash memory has the following characteristics:

① The basic unit of reading and writing is Page, and the unit of erasing is Block; the size of a page is nKB (KB unit is 1024 bytes), and n is usually equal to 2, 4, 8 or 16. Each block contains m pages, m is usually 64, 128 or 256.

②Each physical block must be erased before data can be written.

③Each block has a certain lifespan, that is, the number of erasures is limited. For example, for SLC (Single Level Cell) Flash, that is, single logic unit flash memory, the lifespan is 10,00,00 times; and for MLC (Multi-Level Cell) Flash, the typical lifespan is 1500-3,000 times.

Based on the above-mentioned characteristics of flash memory, a flash translation layer FTL is introduced into the solid-state hard disk for storage control of flash memory. For example, Flash writing data can only write 1 as 0, erasing data is writing all data as 1, so if you write new data on the Flash that already has data, you must first erase the whole block (all storage is all 1), and then write new data. This also determines that the smallest unit suitable for reading and writing SSD is Page. In the past mechanical hard disk era, the operating system considered the disk as a series of sectors (Sector, including 512Byte storage space), which is the smallest unit for hard disk operations. The limitations of this series of physical characteristics require FTL to bear the characteristics of backward compatibility. FTL is located between the file system and the physical medium, and virtualizes the operating habits of Flash to operate on the 512Byte sector of the traditional hard disk. The operating system can operate in the traditional sector mode without worrying about the erase/read/write problems mentioned earlier. All logic-to-physics conversions are done by FTL, as shown in Figure 1.

The FTL layer is responsible for converting the read and write requests of the upper file system into read and write operation commands at the physical level of the flash memory, and at the same time completes the corresponding management according to the operating characteristics of the flash memory. The FTL algorithm, especially its corresponding FMT (FlashMapping Table) mechanism, is the key to affecting the performance of solid-state drives.

Traditional data mapping methods use block mapping and page mapping. As the size of the flash memory page increases, the insufficient speed of page mapping and block mapping in random read and write becomes apparent. Page mapping is to map a logical page to any physical page (Physical Page) in Flash. If the logical block address (Logical Block Address, LBA) is divided into many operation units with physical page size as the unit, the mapping algorithm has high management flexibility and small garbage collection load when the physical page is less than or equal to 4KB. However, with the improvement of technology, the physical pages of Flash gradually increase. At present, the mainstream is basically 16KB physical pages, and there is a tendency to expand to 32KB. When the physical page is larger than 4KB, writing small files randomly (usually the measurement of IOPS is based on random data blocks of 4KB size) will cause a physical page to only use up 4KB space, and the remaining physical page space will supplement other data. When the write amplification WA (Write Amplification) coefficient will become larger, as the physical page size increases, the disadvantage of this algorithm will become greater and greater. Obviously, such a simple mapping method cannot meet the requirements of writing speed, and at the same time, it also greatly consumes the "life" of the flash memory.

Therefore, in view of the above-mentioned defects existing in the current prior art, it is necessary to conduct research to provide a solution to solve the defects existing in the prior art.

Contents of the invention

In view of this, it is indeed necessary to provide a flash memory conversion layer control method for solid-state storage devices, so that the speed of random read and write can be improved, and the service life of the flash memory can be increased.

In order to overcome the defective of prior art, technical scheme of the present invention is as follows:

A flash memory conversion layer control method for a solid-state storage device, comprising the following steps:

Step S1: setting the minimum management unit in the flash memory translation layer (FTL), and N minimum management units just form the space of a flash memory physical page, where N is a positive integer greater than 0;

Step S2: Mapping between the logical address and the physical address with the smallest management unit;

Step S3: FTL gives each minimum management unit data an address identifier for management;

Step S4: When the host writes data, wait for the continuously written data to reach a complete physical page space of the flash memory, and then write a complete blank physical page of the flash memory at one time.

Preferably, in the step S3, an independent address code is set for each minimum management unit data in the flash memory mapping table (FMT).

Preferably, the minimum management unit adopts a storage capacity of 4KB.

Preferably, the flash memory mapping table (FMT) adopts a segmented scheduling method to read the relevant part of the flash memory mapping table that needs to be used into the memory, and store the rest of the flash memory mapping table in the external storage space.

Preferably, the Flash Mapping Table (FMT) is stored in an external DRAM space.

Preferably, the flash mapping table (FMT) is stored in the flash memory.

Compared with the prior art, the flash memory conversion layer control method for solid-state storage devices provided by the present invention uses a 4KB data block mapping algorithm, thereby effectively improving the random read and write speed, and at the same time being able to use the limited on-chip storage space To achieve larger and larger mapping tables.

Description of drawings

FIG. 1 is an FTL mapping diagram in the prior art.

FIG. 2 is a flowchart of a method for controlling a flash conversion layer of a solid-state storage device according to the present invention.

Figure 3 shows the random write FLASH storage distribution in the page mapping mode.

Figure 4 shows the random write FLASH storage distribution in the 4KB mapping mode.

FIG. 5 is a PMT mapping diagram of traditional page mapping.

FIG. 6 is a PMT mapping diagram of 4KB mapping in a preferred implementation manner of the present invention.

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

detailed description

A flash conversion layer control method for a solid-state storage device provided by the present invention will be further described below in conjunction with the accompanying drawings.

With the increase of the physical page size of the flash memory, the traditional page mapping method will lead to a larger write amplification WA (Write Amplification) coefficient, which cannot meet the requirements of the write speed. At the same time, it also greatly consumes the "lifetime" of the flash memory.

To give a simple example of write amplification, assuming that the Page size is 16KB, and each write is 4KB, the basic requirements are:

① Read out the 12KB that does not need to be modified in this Page;

②Find a new physical Page and write complete 16KB data (including 12KB read and 4KB newly written). That is to say, writing 4KB actually needs to write 16KB, and the write amplification factor is

In order to overcome the above-mentioned technical defects, referring to Fig. 2, it is shown as a flow chart of a flash conversion layer control method for a solid-state storage device of the present invention, including the following steps:

Step S1: Set the minimum management unit in the flash translation layer (FTL), and N minimum management units just form the space of a flash memory physical page, wherein, N is a positive integer greater than 0; preferably, the minimum management unit usually adopts 4KB Storage capacity, usually the minimum unit for reading and writing data by the operating system is 4KB. At the same time, the measurement of IOPS is also based on random data blocks of 4KB.

Step S2: Mapping between the logical address and the physical address with the smallest management unit;

Step S3: FTL gives each minimum management unit data an address identifier for management;

Step S4: When the host writes data, wait for the continuously written data to reach a complete physical page space of the flash memory, and then write a complete blank physical page of the flash memory at one time.

Referring to Fig. 3 and Fig. 4, it shows the FLASH storage distribution of random writing under the page mapping mode and the 4KB mapping mode respectively. It can be seen from FIG. 3 that in the prior art page mapping, only 4KB is written into a Page, and the remaining part is filled with other data, and only 4KB of valid data is recorded in the 16KB space. It can be seen from FIG. 4 that with the 4KB mapping proposed by the present invention, a Page can store 16KB of data. The basic principle is: write data from the host, each 4KB is assigned an address for management; when several consecutive 4KB reaches the data volume of a complete flash memory Page, write them into a complete flash memory Page at one time. Especially when the Flash read and write adopts 4KB random read and write (4KB Random R/W), the write advantage of 4KB mapping is particularly obvious. Since the minimum unit of random read and write data is 4KB, the minimum management unit of FTL is also adaptively adjusted so that every 4KB data block is the minimum unit for mapping and management. In a rational state, the write amplification factor WA=1. The random writing speed is almost close to the writing of continuous data stream, which greatly improves the performance of random writing.

In the flash memory mapping table (FMT), the most important table is the page mapping table (Paging Mapping Table, PMT). PMT is the core of the algorithm, which includes at least logical page to physical page mapping (Logic Page To Physical PageMapping), see Figure 5 , shows the PMT mapping diagram of traditional page mapping. The memory address represents the logical page number, and the memory value represents the physical page number. Each physical address information stored in the PMT corresponds to a physical page of flash memory. The physical page number can be obtained according to the logical page number .

In a preferred implementation manner, in the step S3, an independent address code is set for each minimum management unit data in the flash memory mapping table (FMT). That is, in the PMT, an independent physical address is set for each 4KB space. Referring to FIG. 6, each physical address information stored in the PMT corresponds to a 4KB space in the flash memory.

In the above technical solution, the mapping of 4KB is used as the unit, thereby greatly improving the writing performance, but since an independent physical address is set for each 4KB space, the mapping with 4KB as the smallest unit causes the storage space of the mapping table to double big. Refer to the following formula for the size of the mapping table:

Assuming that the hard disk storage space is 128GB, the number of address representation bytes of each mapping unit is 4, that is, the address of a mapping unit is represented by a 4-byte address, and the mapping table size is 32MB when using 16KB Page mapping; while using 4KB mapping, then The mapping table size is 128MB.

In addition, in the above technical solution, since an independent physical address is set for each 4KB space, the search at the time of reading becomes a search every 4KB. In the case of mapping with 16KB Page as a unit, a search of the mapping table can read 16KB of data, that is, the flash memory mapping table is searched every 16KB. Therefore, the increase in random write performance is compromised to a certain extent by reducing the random read performance. However, under the premise that the hardware performance is greatly improved, the search speed (efficiency) is very high, and the reduction of random read speed is compared with the improvement of random write performance, and the reduction of write amplification factor WA (thus improving the service life of flash memory), is Well worth it.

In a preferred embodiment, the flash memory mapping table (FMT) adopts a segmented scheduling method, and the relevant part of the flash memory mapping table that needs to be used at present is read into the memory, while the rest of the flash memory mapping table is stored in the external storage space. Since the mapping table needs to be scheduled and used in the integrated circuit chip, the cache in the chip is generally implemented by SRAM. The SRAM space of more than 1MB needs to occupy a large space for the current integrated circuit thin chip, and the cost performance is not high. The problem can be solved by adopting segment scheduling. That is to read the part of the table currently needed into the SRAM, and store the rest in the external space of the chip. There are two forms of storage in the external space of the chip:

Stored in the external DRAM (Dynamic Random Access Memory) space. The advantage is that the access speed is fast and the performance is superior. The disadvantage is that additional hardware resources and costs are required, which increases the complexity of the chip and the cost of additional DRAM chips; in the case of unstable power supply (including abnormal power failure), it is difficult to back up and protect a large amount of table data in DRAM in time , It is easy to cause the loss of the hard disk mapping table and cause hard disk damage. It is suitable for hard disks and systems with stable power supply and pursuit of ultimate read and write performance, such as first-level hard disk arrays of high-speed computers or servers, and hot data storage.

Store in flash memory (Flash Memory). The advantage is that there is no additional hardware cost; in the case of abnormal power supply problems, it is easy to protect the mapping table from loss, or it is easy to rebuild itself after loss, and has high reliability. The disadvantage is that the access speed is relatively slow, causing a certain degree of decline in read and write performance; this method also causes an additional flash memory write burden (the WA coefficient is slightly increased). It is suitable for hard disks and systems that pursue reliability and require general read and write performance, such as industrial equipment and cold data storage of large databases.

The following is a calculation and analysis of the read and write speed and performance analysis of 4KB mapped storage management. Assuming that four pieces of 4KB data are randomly written, and the page size of Flash is 16KB, the speeds of page mapping and 4KB mapping are respectively calculated below.

When four pieces of 4KB data are randomly written, the maximum write speed of the 4KB mapping algorithm (without changing the mapping table):

Minimum write speed (every 4KB must replace all mapping tables):

In formula (3) and formula (4), Tx0 refers to the time for writing 16KB data to move data through the bus; Tw is the programming waiting time when writing to the flash memory (reflected as the total busy time of the flash memory bus); in this paper In the chip, the SRAM resources are used to store the 4KB Mapping mapping table with a size of 13KB (8KB is direct address mapping, and 3KB is other auxiliary information), the time to move the mapping table is Tx1, and the bus waiting time for reading the flash memory (reflected as The bus is busy (busy time) is Tr, if it is necessary to update the mapping table (calling and updating the mapping table in the current SRAM) between two 4KBs, the time is Tm=Tr+Tx1.

When four pieces of 4KB data are randomly written, the maximum write speed of the page mapping algorithm (without changing the mapping table):

Minimum write speed (every 4KB must replace all mapping tables):

In formula (5) and formula (6), because the page mapping (Page Mapping) every time the system writes 4KB data to the hard disk, the hard disk controller chip needs to complete the other 12KB data, so a 12KB data migration time is required Tp, and a read delay time Tr (the bus waiting time when reading 12KB from the flash memory, reflected in the busy bus, that is, the BUSY time).

Comparing formulas (3) and (5), (4) and (6), it is known that the writing speed of 4KB mapping is higher than that of page mapping.

For the 128GB solid-state hard drive, the flash memory mapping table (FMT table) is 32MB in total. According to the 8KBSRAM memory given by the chip resource in this article, there are 4M "mapping table segments" (each 8KB in size), of which only one 8KB mapping table segment is imported into the control The processor chip memory SRAM (called "current memory table segment") can be searched and queried at any time. Therefore, four 4KB data randomly written, there are four possible distributions corresponding to falling into the FMT:

All four 4KB data fall into the same mapping table segment, then there is only one busy time when writing data at this time, and the probability is:

(2) All four 4KB data fall into two mapping table segments, and there are two busy times, the probability is:

(3) All four 4KB data fall into three mapping table segments, and there are three busy times, the probability is:

All four 4KB data fall into four mapping table segments, and there are four busy times, the probability is:

When writing four 4KB data, the average probability is:

When Page Mapping randomly writes four 4KB data, it first transfers 4KB valid data to the page of the corresponding address (the page size is 16KB). Flash reads and writes in units of pages, and the rest of the page The space is filled with all 1s or all 0s. Since the data is written randomly, and it is page mapping, the address of each random write of 4KB is different, it will be written into another page like the first 4KB data, and each time 16KB is written into Flash, Effective data is only 4KB, so its transmission efficiency is 25%. According to the analysis results at the end of the first chapter, the write amplification factor WA>4.

In contrast, based on the 4KB mapping method, when four 4KB data are randomly written, it will wait for the four 4KB data to be written in a 16KB page before writing to Flash, that is to say, this page writes All of them are four valid data of 4KB that need to be transmitted, so the theoretical value of the transmission efficiency is 100%. The corresponding write amplification factor WA>1 and close to 1.

Based on the idea of 4KB mapping algorithm, the present invention realizes the design of a solid-state hard disk controller chip. The chip adopts 110nm process and has been mass-produced on 8-inch silicon wafers. The chip size is 3.908mm*3.746mm, using SATA PHY, with a data transmission rate of 3Gb/s. The power management circuit integrated on the chip can convert the 5V power supply to the 3.3V voltage required by the I/O circuit and the flash memory chip, and also generate the 1.2V power supply required inside the chip. The storage of the mapping table discussed in the present invention is realized by SRAM.

In order to check the effect of the algorithm described in the present invention, two NAND flash memory models of M company commonly used in the market are used here to test and compare, wherein the flash memory page size (Page Size) of one model is 8KB, and the flash memory page size of another model It is 16KB, because the same series of products from the same company, the other nominal parameters are basically the same, such as the read waiting time is 75us, and the programming (writing) waiting time is 1300us. Use the speed measurement software to test the writing speed of these two Flashes using page mapping and 4KB mapping to randomly transmit 4KB data, as shown in Table 1. It can be seen that no matter whether the page size is 8KB or 16KB, the average speed of 4KB mapping is obviously faster than that of page mapping, and the larger the page, the greater the gap between the speed of 4KB mapping and the speed of page mapping.

Table 1 Random write test speed using different mapping methods

The random write performance under the 4KB mapping method is discussed above. In the actual storage operation, the continuous write performance also needs to be considered. In the 4KB mapping method, since the FMT is updated more frequently, obviously, when writing large data, compared with the page mapping method, its writing efficiency will decrease instead.

In order to overcome the above-mentioned technical defects, in a preferred embodiment of the present invention, it also includes the step of obtaining the size of the file written by the host, and when the data volume of the file is greater than the storage space of a single flash memory physical page, page mapping is used for flash memory management. When the amount of data in the file is smaller than the storage space of a single physical page of the flash memory, the data in the file is first divided into units of the smallest management unit, and then mapped to the smallest management unit for flash memory management. That is, the combination of page mapping and 4KB mapping is adopted, thereby improving the random write performance and continuous write performance of the flash translation layer.

The descriptions of the above embodiments are only used to help understand the method and core idea of the present invention. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, some improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. a kind of flash translation layer (FTL) control method for solid storage device, it is characterised in that comprise the following steps：

Step S1：Minimum administrative unit is set in flash translation layer (FTL) (FTL), and N number of minimum administrative unit just constitutes one The space of flash memory Physical Page, wherein, N is the positive integer more than 0；

Step S2：Mapped with minimum administrative unit between logical address and physical address；

Step S3：FTL is managed for each minimum management cell data gives an address mark；

Step S4：When main frame writes data, wait is continuously written into after data reach a complete flash memory Physical Page space, then The complete blank flash memory Physical Page of one-time write one.

2. the flash translation layer (FTL) control method for solid storage device according to claim 1, it is characterised in that described In step S3, for each minimum management cell data sets an independent address code in Flash table (FMT).

3. the flash translation layer (FTL) control method for solid storage device according to claim 1, it is characterised in that described Minimum administrative unit uses 4KB memory capacity.

4. the flash translation layer (FTL) control method for solid storage device according to claim 2, it is characterised in that flash memory By the way of subsection scheduling, the Flash table of relevant portion that will be currently needed for using reads in internal memory to mapping table (FMT), and Remainder Flash table is stored in external memory space.

5. the flash translation layer (FTL) control method for solid storage device according to claim 4, it is characterised in that flash memory Mapping table (FMT) is stored in the dram space of outside.

6. the flash translation layer (FTL) control method for solid storage device according to claim 4, it is characterised in that flash memory Mapping table (FMT) is stored in flash memory.