CN104423892A - Data writing method, disk module and data writing system - Google Patents

Abstract

The invention provides a data writing method, a hard disk module and a data writing system, wherein the data writing method is used for writing data into the hard disk module, and the hard disk module comprises a plurality of memory units. The data writing method includes the following steps. And receiving the cache data and judging the data type of the cache data. If the data type of the cache data belongs to the first type, the cache data is distributed and written into the memory unit. If the data type of the cache data belongs to the second type, the cache data is written into one of the memory units.

Description

Data writing method, disk module and data writing system

technical field

The present invention relates to a cache technology, and in particular to a data writing method, a hard disk module and a data writing system.

Background technique

At present, mass storage devices on the market can be mainly divided into traditional hard disks (Hard Driver disk, hereinafter referred to as HDD) composed of magnetic heads and disks, and solid state disks (Solid State Disk, hereinafter referred to as SSD) composed of memory. Generally speaking, due to the lower cost of manufacturing traditional hard disks, the capacity of traditional hard disks is generally greater than that of solid-state hard disks. However, in terms of data access speed, the data access speed of solid-state drives may be several times that of traditional hard drives. Therefore, more and more computer systems adopt the hybrid hard disk architecture of Solid State Hybrid Drive (SSHD), in which the traditional hard disk is used as the basic data storage space, and the solid state hard disk is used as the cache space (cache space). space) to use.

In the existing hybrid hard disk architecture, the memory of the solid-state hard disk is usually composed of multiple memory units, and in order to speed up data access, a single piece of data can be disassembled into multiple pieces of data to be processed simultaneously by each memory unit. access. Although such a parallelized access method can increase the read speed, however, since the data is scattered and written to different memory units, and each memory unit only stores a part of the data fragment, the memory unit will generate more Fragmented space. Therefore, when the storage space of the memory is insufficient and the garbage collection (GarbageCollection) function of memory management is required, the memory will have a high Write Amplification Factor (hereinafter referred to as WAF), thereby reducing the service life of the SSD.

Based on this, how to effectively take into account the high data access speed of solid-state drives and the service life of solid-state drives is one of the important issues for related companies when developing products.

Contents of the invention

The present invention provides a data writing method, a hard disk module and a data writing system, which can provide different writing methods according to the data type of cached data, so as to effectively improve the data access speed and prolong the service life of the hard disk module .

The invention proposes a data writing method, which is suitable for a hard disk module, wherein the hard disk module includes a plurality of memory units, and the data writing method includes the following steps. Receive cached data and determine the data category to which the cached data belongs. If the data category of the cached data belongs to the first category, the cached data is allocated and written into the memory unit. If the data category of the cached data belongs to the second category, then write the cached data into one of the memory units.

The invention further provides a hard disk module, which includes a memory controller and a plurality of memory units. The memory units are respectively coupled to the memory controller through data channels. Wherein, the memory controller receives the cached data, and judges the data category to which the cached data belongs. If the data category of the cached data belongs to the first category, the cached data is allocated and written into the memory unit. If the data category of the cached data belongs to the second category, then write the cached data into one of the memory units.

The present invention further provides a data writing system, which includes a host and a first hard disk module, wherein the first hard disk module is coupled to the host. The first hard disk module includes a memory controller and a plurality of memory units, and the memory units are respectively coupled to the memory controller through data channels. Wherein, the memory controller receives the cached data from the host, and determines the data category to which the cached data belongs. If the data category of the cached data belongs to the first category, the memory controller allocates and writes the cached data into the memory unit. If the data category of the cached data belongs to the second category, the memory controller writes the cached data into one of the memory units.

Based on the above, the data writing method, hard disk module and data writing system of the present invention can allocate and write the cached data to multiple memory units according to the data type of the cached data, or write the cached data to the same memory unit, so as to effectively increase the data access speed and prolong the service life of the hard disk module.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a block diagram of a data writing system according to an embodiment of the present invention;

FIG. 2 is a flowchart of a data writing method according to an embodiment of the present invention;

FIG. 3 is a block diagram of a data writing system according to an embodiment of the present invention;

FIG. 4 is a flowchart of a data writing method according to an embodiment of the invention.

Explanation of reference signs:

1000, 3000: data written into the system;

10, 30: Host;

100, 300A: the first hard disk module;

110, 310: memory controller;

121, 122, 123, 124, 321, 322, 323, 324: memory units;

300B: the second hard disk module;

CH1, CH2, CH3, CH4: data channel;

S202, S204, S206, S208, S402, S404, S406, S408, S410, S412, S414: each step of the data writing method.

Detailed ways

In the solid-state hybrid hard disk, cache data with high access frequency is generally cached in the solid-state hard disk, so as to improve the overall data access speed of the computer system through the high data access speed characteristics of the solid-state hard disk. As for the cached data accessed to the SSD, based on the frequency of use, further distinctions can be made between performance-oriented (Performance Orientation) cached data and reliability-oriented (Reliability Orientation) cached data. Oriented cache data requires high data access speed. If the solid-state hard drive can write cached data in different ways according to the data type of the above-mentioned cached data, it is bound to take into account the data access speed and the service life of the solid-state hard drive. The present invention is a data writing method, a hard disk module and a data writing system proposed based on the above viewpoint. In order to make the content of the present invention more clear, the following specific examples are given as examples in which the present invention can indeed be implemented.

FIG. 1 is a block diagram of a data writing system according to an embodiment of the present invention. Please refer to FIG. 1 , a data writing system 1000 includes a host 10 and a first hard disk module 100 .

The host 10 is, for example, a desktop computer, a notebook computer, a tablet computer, a personal digital assistant (hereinafter referred to as PDA), a mobile phone, a digital camera, a game machine, or various electronic devices with computing and processing capabilities, and it is not limited here. type. In addition, the host 10 has an operating system and a central processing unit (Central Processing Unit, referred to as CPU hereinafter) to manage hardware and software resources of the host 10 .

The first hard disk module 100 can be used as a cache space (cache space) for storing and placing various cache data (cache data), wherein the first hard disk module 100 is, for example, a flash memory with a flash memory (flash memory) as a storage medium. device, such as a solid state disk (Solid State Disk, hereinafter referred to as SSD). In addition, the first hard disk module 100 can be disposed inside the host 10 and electrically connected to the host 10 . Alternatively, the first hard disk module 100 may also be electrically connected to the host 10 in an external manner, for example, electrically connected to the host 10 through various buses such as a Universal Serial Bus (hereinafter referred to as USB), etc. The present invention is not limited thereto.

The first hard disk module 100 includes a memory controller 110 and a plurality of memory units. For the convenience of description, the memory units 121 , 122 , 123 and 124 are taken as examples here, but this embodiment does not limit the number of memory units.

The memory controller 110 can be implemented by an embedded system chip (System On Chip, hereinafter referred to as SOC), which is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and according to the host 10 The instructions in the memory units 121 , 122 , 123 and 124 perform operations such as writing, reading and erasing data. Here, the memory controller 110 writes data into the memory units 121 , 122 , 123 and 124 according to the data writing method of this embodiment. In addition, the memory controller 110 will maintain a logical to physical address mapping table (logical to physical address mapping table) to record the mapping relationship between the logical address and the physical address of the cached data, and when the host 10 wants to access a certain logical address, The memory controller 110 can then access data in the corresponding memory units 121 , 122 , 123 and 124 according to the logical-to-physical address mapping table.

Memory units 121, 122, 123, and 124 are, for example, single-level storage unit (Single Level Cell, SLC) NAND flash memory, multi-level storage unit (Multi Level Cell, hereinafter referred to as MLC) NAND flash memory, third-level storage unit, etc. Cell (Trinary Level Cell, hereinafter referred to as TLC) NAND flash memory or other flash memory with the same characteristics. Among them, each storage unit of the SLC NAND flash memory can store 1 bit of data (that is, "1" and "0"), and each storage unit of the MLC NAND flash memory can store 2 bits of data, However, each storage unit of the TLC NAND flash memory can store 3 bits of data. In addition, the memory units 121, 122, 123, and 124 are respectively coupled to the memory controller 110 through data channels CH1, CH2, CH3, and CH4, and each of the memory units 121, 122, 123, and 124 has a plurality of physical blocks to Data written by the host 10 is stored. Each of the physical blocks has a plurality of physical pages, wherein the physical pages belonging to the same physical block can be written independently and erased simultaneously.

In this embodiment, when the first hard disk module 100 receives cached data from the host 10, the memory controller 110 will determine the data category to which the cached data belongs. If the cached data belongs to the cached data that attaches great importance to the reading speed (that is, performance-oriented), such as the execution file of the windows application program, etc., the memory controller 110 will pass the cached data through different data channels CH1, CH2, CH3 and CH4 are written into different memory units 121 , 122 , 123 and 124 so as to utilize the high data access speed performance of the first hard disk module 100 . On the other hand, if the cached data belongs to the cached data that does not attach great importance to the read speed (that is, reliability-oriented), or the file size of the cached data exceeds a preset value (for example, 128KB), the memory controller 110 will store this The cached data is written into the same memory unit through the same data channel, so as to prolong the service life of the first hard disk module 100 and improve the reliability.

The steps of the data writing method of this embodiment will be described below in conjunction with the data writing system 1000 described above. FIG. 2 is a flowchart of a data writing method according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2 , in step S202 , the memory controller 110 receives cached data. In step S204, the memory controller 110 determines the data category to which the cached data belongs. Specifically, the data category to which the cached data belongs is classified into the first category or the second category according to the writing method of the cached data to the memory units 121 , 122 , 123 and 124 . That is, the cached data belonging to the first category will be allocated by the memory controller 110 and written into the memory units 121, 122, 123, and 124, while the cached data belonging to the second category will be written into the memory unit 110 by the memory controller 110. One of the memory units 121 , 122 , 123 and 124 . In this embodiment, the cache data of the first category is, for example, performance-oriented cache data that attaches great importance to read speed, and the cache data of the second category is, for example, reliability-oriented cache data that does not attach great importance to read speed. .

It should be noted that the host 10 can set the data category of the cached data as the first category or the second category, so as to set which type of cached data is to be allocated by the memory controller 110 and written into different memory units 121 , 122, 123 and 124, or are written to the same memory unit by the memory controller 110. For example, the host 10 can set the data category of the cached data according to the file type, file size, usage frequency, etc. of the cached data. For example, if the cached data is an executable file of a windows application program, etc., it will be set as the first category by the host 10; if the cached data is a user file (for example, its file format is ^* .docx, ^* .pdf or ^* . etc.), because the probability that the file will be continuously and frequently opened is small, it will be set as the second category by the host computer 10. For another example, if the file size of the cached data does not exceed 128KB, it will be set as the first category by the host 10; if the file size of the cached data exceeds 128KB, it will be set as the second category by the host 10. Certainly, the host computer 10 can also set the cache data that is highly valued on the read speed as the first category, and set the cache data that is not very important on the read speed as the second category according to the settings of the user. The above method of setting the data type of the cached data is an example, and this embodiment is not limited thereto.

In this embodiment, the host 10 can mark different flag values in preset bits of the cached data according to the file type, file size, usage frequency, etc. of the cached data, so as to set the data category to which the cached data belongs. In this way, the memory controller 110 can determine whether the data category of the cached data belongs to the first category or the second category according to the flag value in the preset bit of the cached data. For example, if the host 10 sets the flag value of the preset bit of the cached data to a first value, such as “0”, the memory controller 110 will determine that the data category of the cached data belongs to the first category. On the other hand, if the host 10 sets the flag value of the preset bit of the cached data to a second value, such as “1”, the memory controller 110 will determine that the data category of the cached data belongs to the second category. It must be understood that the tag value in this embodiment is not limited to "0" or "1", and the memory controller 110 can also determine the data category of the cached data according to any other aspect marked in the cached data. first class or second class.

Next, in step S204, if the memory controller 110 determines that the data category of the cached data belongs to the first category, then as shown in step S206, the memory controller 110 will allocate and write the cached data to the memory units 121, 122, 123 and 124 in. Here, the memory controller 110 obtains a plurality of first physical addresses corresponding to a plurality of logical addresses (for example, a logical block address (hereinafter referred to as LBA) of the cached data according to the logical-to-physical address mapping table, wherein These first physical addresses belong to different memory units 121, 122, 123, and 124 respectively. And, the memory controller 110 will cache multiple data fragments corresponding to the above-mentioned logical addresses according to the above-mentioned first physical addresses, through Each data channel CH1 , CH2 , CH3 and CH4 is written into different memory units 121 , 122 , 123 and 124 .

For example, Table 1 below illustrates the mapping relationship between the logical address and the first physical address in the logical-to-physical address mapping table. Please refer to Table 1, assuming that the data segments in the cache data correspond to logical addresses L(100), L(101), L(102) and L(103), respectively, and the logical addresses L(100), L(101), L(102) and L(103) are respectively mapped to the first physical addresses P(201), P(301), P(401) and P(501), wherein the first physical addresses P(201), P(301) , P(401) and P(501) belong to memory cells 121, 122, 123 and 124 in sequence. Here, the memory controller 110 transfers the data segments located at the logical addresses L(100), L(101), L(102) and L(103) according to the first physical addresses P(201), P(301) , P(401) and P(501), and write to the memory units 121, 122, 123 and 124 respectively. In other words, assuming that the file size of the cached data is 10MB, the memory controller 110 may divide the cached data into four pieces of data, wherein the file size of each piece of data is, for example, 2.5MB, or each piece of data may have a different file size . And, the memory controller 110 writes these four pieces of data into the memory units 121 , 122 , 123 and 124 respectively. In this way, according to the concept of data allocation, the memory controller 110 can quickly and parallelize write the cached data to different memory units 121 , 122 , 123 and 124 through the data channels CH1 , CH2 , CH3 and CH4 . In addition, when the host 10 intends to read the cached data in the first hard disk module 100, the memory controller 110 can parallelize the read data distributed in the memory units 121, 122, 123 and 124 of each data segment of cached data. Thereby, the memory controller 110 can increase the speed of accessing cached data.

Table I

logical address first physical address L(100) P(201) L(101) P(301) L(102) P(401) L(103) P(501)

It should be noted that in step S204, this embodiment is not limited to write the cached data to all the memory units of the first hard disk module 100, that is, as long as the data segments in the cached data can be respectively written into More than two memory units in the first hard disk module 100 all belong to the scope of the present invention. In addition, in order to increase the speed of accessing the cached data, the memory controller 110 can evenly/unequally distribute the cached data to the multiple memory units of the first hard disk module 100 according to the number of memory units.

On the other hand, if the memory controller 110 determines that the data category of the cached data belongs to the second category, then as shown in step S208, the memory controller 110 will write the cached data into one of the memory units 121, 122, 123, and 124. a memory cell. Here, the memory controller 110 obtains a plurality of second physical addresses corresponding to the plurality of logical addresses of the cached data according to the logical-to-physical address mapping table, wherein the second physical addresses belong to the memory units 121, 122, 123 and One of the memory units in 124 (represented by memory unit P). Moreover, the memory controller 110 writes multiple data segments in the cached data into the memory unit P according to the second physical address.

For example, Table 2 below illustrates the mapping relationship between the logical address and the second physical address in the logical-to-physical address mapping table. Please refer to Table 2, assuming that the data segments in the cache data correspond to logical addresses L(100), L(101), L(102) and L(103), respectively, and the logical addresses L(100), L(101), L(102) and L(103) are respectively mapped to the second physical addresses P(201), P(202), P(203) and P(204), wherein it is assumed that the second physical addresses P(201), P(202 ), P(203) and P(204) all belong to the memory unit 121. Here, the memory controller 110 will transfer the data segments located at the logical addresses L(100), L(101), L(102) and L(103) according to the second physical addresses P(201), P(202) , P(203) and P(204), and are written into the memory unit 121. In other words, assuming that the file size of the cached data is 10MB, the memory controller 110 will write the entire 10MB cached data into the memory unit 121 . In this way, since the cache data written into the same memory unit can be continuous and complete, for the first hard disk module 100, the generation of fragmented space can be reduced, and garbage collection (Garbage Collection, hereinafter) can be reduced. GC for short) frequency and cost. In this way, this embodiment can reduce the erasing times (Erase count) of the storage unit in the first hard disk module 100, and effectively suppress the write amplification factor (Write Amplification Factor, hereinafter referred to as WAF), thereby extending the length of the first hard disk module 100. service life and improve the reliability of the first hard disk module 100 .

Table II

logical address second physical address L(100) P(201) L(101) P(202) L(102) P(203) L(103) P(204)

Based on the above, the memory controller 110 can break up the cached data belonging to the first category (for example, performance-oriented) into the memory units 121, 122, 123, and 124 in different writing methods according to the data category of the cached data. , and write cached data belonging to the second category (eg, reliability-oriented) to the same memory unit. In this way, when accessing performance-oriented cache data, the first hard disk module 100 can provide a higher data access speed, and when accessing reliability-oriented cache data, the first hard disk module 100 can effectively suppress writes. Enter the magnification factor. In this way, the present embodiment can simultaneously take into account the data access speed and the service life of the first hard disk module 100 .

FIG. 3 is a block diagram of a data writing system according to an embodiment of the present invention. Referring to FIG. 3 , the data writing system 3000 includes a host 30 , a first hard disk module 300A and a second hard disk module 300B, wherein the data access speed of the first hard disk module 300A is higher than that of the second hard disk module 300B. In this embodiment, the functions of the host 30 and the first hard disk module 300A are the same or similar to those of the host 10 and the first hard disk module 100 in the foregoing embodiments, so they are not repeated here.

Different from the foregoing embodiments, the data writing system 3000 is further configured with a second hard disk module 300B. The second hard disk module 300B is, for example, a disk storage unit using a disk as a storage medium, such as a Hard Disk Drive (hereinafter referred to as HDD). In addition, the second hard disk module 300B and the first hard disk module 300A can be integrated into a data storage device composed of any two or more storage media with different data access speeds, such as a solid state hybrid hard disk (Solid StateHybrid Drive, hereinafter referred to as SSHD), for users to store various data. In this embodiment, since the data access speed of the first hard disk module 300A is higher than that of the second hard disk module 300B, the first hard disk module 300A can be used as a cache space for storing and placing various cache data, The second hard disk module 300B can be used as a basic storage space for storing most of the data.

The steps of the data writing method of this embodiment will be described below in conjunction with the data writing system 3000 described above. FIG. 4 is a flowchart of a data writing method according to an embodiment of the invention. Referring to FIG. 3 and FIG. 4 , in step S402 , the host 30 obtains the data access type of the data to be written. Wherein, the host 30 judges whether the data access type of the data to be written belongs to the cache data with high data access speed according to the file type, file size, usage frequency or write command of the data to be written, for example. In step S404, the host 30 selects to write the data to be written into the first hard disk module 300A or the second hard disk module 300B according to the data type of the data to be written. If the data to be written does not belong to cache data, as shown in step S406, the host 30 will write the data to be written into the second hard disk module 300B. Here, since the second hard disk module 300B can provide higher storage capacity, it can meet the user's demand for storage capacity.

On the other hand, if the data to be written belongs to cache data, as shown in step S408 , the host 30 will write the data to be written into the first hard disk module 300A, so as to provide higher data access speed. Next, in step S410 , the memory controller 310 in the first hard disk module 300A determines the data category to which the cached data belongs. Moreover, if the memory controller 310 determines that the data category of the cached data belongs to the first category, as shown in step S412 , the memory controller 410 allocates and writes the cached data to the memory units 421 , 422 , 423 and 424 . On the other hand, if the memory controller 310 determines that the data category of the cached data belongs to the second category, then as shown in step S414, the memory controller 410 will write the cached data into one of the memory units 421, 422, 423, and 424. a memory cell. The above-mentioned steps S408-S414 are the same or similar to the steps S202-S208 of the foregoing embodiment, so they will not be repeated here.

In this embodiment, the host 30 can properly choose to write the data to be written into the first hard disk module 300A or the second hard disk module 300B, thereby taking advantages of different types of hard disk modules. In addition, the first hard disk module 300A can further classify the written data so that the data can be distributed and written to different memory units 421 , 422 , 423 and 424 or the same memory unit in the first hard disk module 300A. Thus, this embodiment can simultaneously take into account the data access speed and prolong the service life of the first hard disk module 300A.

To sum up, in the data writing method, hard disk module, and data writing system of this embodiment, the host will write the cached data to the hard disk module using the memory as the storage medium according to the data access type of the data to be written. . Wherein, the memory controller of the hard disk module can further determine whether the cached data belongs to performance-oriented (ie, the first category) or reliability-oriented (ie, the second category) cache data according to the data category of the cached data. Moreover, the memory controller uses the concept of data allocation to write performance-oriented cache data into different memory units, and sequentially writes reliability-oriented cache data into the same memory unit. In this way, when the hard disk module accesses performance-oriented cache data, the hard disk module can provide higher data access speed, and when the hard disk module accesses reliability-oriented cache data, the hard disk module can effectively suppress the write amplification factor . Thereby, the present invention can simultaneously take into account the data access speed and the service life of the hard disk module.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above method embodiments can be completed by program instructions and related hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (16)

1. a method for writing data, is applicable to a hard disc module, and wherein this hard disc module comprises multiple memory cell, it is characterized in that, comprising:

Receive one data cached;

Judge this data cached affiliated data category;

If this this data cached data category belongs to a first category, then this data cached distribution is write in those memory cells; And

If this this data cached data category belongs to one second classification, then by this one of them writing in those memory cells data cached.

2. method for writing data according to claim 1, is characterized in that, is judging that the step of this data cached this affiliated data category comprises:

According to a mark value, judge this data cached this affiliated data category;

If this mark value belongs to one first value, then judge that this data cachedly belongs to this first category; And

If this mark value belongs to one second value, then judge that this data cachedly belongs to this second classification.

3. method for writing data according to claim 2, is characterized in that, this mark value is decided by this data cached file type, file size or frequency of utilization.

4. method for writing data according to claim 1, is characterized in that, if this this data cached data category belongs to this first category, then by this data cached distribution and the step write in those memory cells comprise:

Turn physical address mapping table according to a logic, obtain multiple first physical addresss corresponding to these data cached multiple logical addresses, wherein those first physical addresss belong to those different memory cells; And

Multiple data slots during this is data cached, according to those the first physical addresss, write in those memory cells.

5. method for writing data according to claim 1, is characterized in that, if this this data cached data category belongs to this second classification, then comprises in the step of one of them write in those memory cells that this is data cached:

Turn physical address mapping table according to a logic, obtain multiple second physical addresss corresponding to these data cached multiple logical addresses, wherein those second physical addresss belong to one of them in those memory cells; And

Multiple data slots during this is data cached, according to those the second physical addresss, write in this memory cell.

6. a hard disc module, is characterized in that, comprising:

One Memory Controller; And

Multiple memory cell, those memory cells are coupled to this Memory Controller respectively by a data channel, wherein this Memory Controller receives one data cached, Bing judges this data cached affiliated data category, if this this data cached data category belongs to a first category, then this data cached distribution is write in those memory cells, if and this this data cached data category belongs to one second classification, then by this one of them writing in those memory cells data cached.

7. hard disc module according to claim 6, this Memory Controller is according to a mark value, judge this data cached this affiliated data category, it is characterized in that, if this mark value belongs to the first value, then this Memory Controller judges that this data cachedly belongs to this first category, and if this mark value belong to the second value, then this Memory Controller judges that this data cachedly belongs to this second classification.

8. hard disc module according to claim 7, is characterized in that, this mark value is decided by this data cached file type, file size, frequency of utilization or a preset value.

9. hard disc module according to claim 6, it is characterized in that, if this this data cached data category belongs to this first category, then this Memory Controller turns physical address mapping table according to a logic, obtain multiple first physical addresss corresponding to these data cached multiple logical addresses, wherein those first physical addresss belong to those different memory cells, and this Memory Controller this is data cached in multiple data slots, according to those the first physical addresss, write in those memory cells.

10. hard disc module according to claim 6, it is characterized in that, if this this data cached data category belongs to this second classification, then this Memory Controller turns physical address mapping table according to a logic, obtain multiple second physical addresss corresponding to these data cached multiple logical addresses, wherein those second physical addresss belong to one of them in those memory cells, and this Memory Controller this is data cached in multiple data slots, according to those the second physical addresss, write in this memory cell.

11. 1 kinds of data writing systems, is characterized in that, comprising:

One main frame; And

One first hard disc module, be coupled to this main frame, this first hard disc module comprises a Memory Controller and multiple memory cell, and those memory cells are coupled to this Memory Controller respectively by a data channel, wherein this Memory Controller receives one data cached from this main frame, and judge this data cached affiliated data category, if this this data cached data category belongs to a first category, then this data cached distribution Bing writes in those memory cells by this Memory Controller, if and this this data cached data category belongs to one second classification, then this Memory Controller is by this one of them writing in those memory cells data cached.

12. data writing systems according to claim 11, it is characterized in that, this Memory Controller is according to a mark value, judge this data cached this affiliated data category, if this mark value belongs to one first value, then this Memory Controller judges that this data cachedly belongs to this first category, and if this mark value belong to one second value, then this Memory Controller judges that this data cachedly belongs to this second classification.

13. data writing systems according to claim 12, is characterized in that, this mark value is decided by this data cached file type, file size, frequency of utilization or a preset value.

14. data writing systems according to right characteristic 11, it is characterized in that, if this this data cached data category belongs to this first category, then this Memory Controller turns physical address mapping table according to a logic, obtain multiple first physical addresss corresponding to these data cached multiple logical addresses, wherein those first physical addresss belong to those different memory cells, and this Memory Controller this is data cached in multiple data slots, according to those the first physical addresss, write in those memory cells.

15. data writing systems according to right characteristic 11, it is characterized in that, if this this data cached data category belongs to this second classification, then this Memory Controller turns physical address mapping table according to a logic, obtain multiple second physical addresss corresponding to these data cached multiple logical addresses, wherein those second physical addresss belong to one of them in those memory cells, and this Memory Controller this is data cached in multiple data slots, according to those the second physical addresss, write in this memory cell.

16. data writing systems according to right characteristic 11, is characterized in that, also comprise:

One second hard disc module, be coupled to this main frame, and a data access speed of this first hard disc module is higher than this second hard disc module, wherein this main frame judges whether one belong to for the data access types of write data that this is data cached, if this wish write data belong to, this is data cached, then this wish write data are write to this first hard disc module by this main frame, if this wish write data do not belong to, this is data cached, then this wish is write data and writes to this second hard disc module by this main frame.